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GET /api/patches/2224124/?format=api
{ "id": 2224124, "url": "http://patchwork.ozlabs.org/api/patches/2224124/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416210508.30686-5-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260416210508.30686-5-philmd@linaro.org>", "list_archive_url": null, "date": "2026-04-16T21:05:08", "name": "[v4,4/4] target/mips: Check alignment for microMIPS pre-R6 LD/ST multiple", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "5e2a101506cb0d206ad7b4732c2a8af5c1ba3514", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416210508.30686-5-philmd@linaro.org/mbox/", "series": [ { "id": 500206, "url": "http://patchwork.ozlabs.org/api/series/500206/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500206", "date": "2026-04-16T21:05:04", "name": "target/mips: Replace cpu_ld/st_mmuidx_ra() calls in LD/ST Multiple", "version": 4, "mbox": "http://patchwork.ozlabs.org/series/500206/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224124/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224124/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=m5+RshzO;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42a;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Pre-REL6 microMIPS requires alignment while REL6 microMIPS does not.\nPass the MemOp alignment as argument to gen_ldst_multiple(). Keep\nusing MO_UNALN for REL6 decoder but use MO_ALIGN for the pre-REL6\npart.\n\nFixes: 3c824109da0 (\"target-mips: microMIPS ASE support\")\nReported-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/mips/tcg/micromips_translate.c.inc | 16 +++++++++-------\n 1 file changed, 9 insertions(+), 7 deletions(-)", "diff": "diff --git a/target/mips/tcg/micromips_translate.c.inc b/target/mips/tcg/micromips_translate.c.inc\nindex fb107eb91fe..efd9781c53b 100644\n--- a/target/mips/tcg/micromips_translate.c.inc\n+++ b/target/mips/tcg/micromips_translate.c.inc\n@@ -690,10 +690,9 @@ static void gen_andi16(DisasContext *ctx)\n }\n \n static void gen_ldst_multiple(DisasContext *ctx, uint32_t opc, int reglist,\n- int base, int16_t offset)\n+ int base, int16_t offset, MemOp mop)\n {\n TCGv t0, t1;\n- MemOp mop = MO_UNALN;\n MemOpIdx oi;\n \n if (ctx->hflags & MIPS_HFLAG_BMASK) {\n@@ -772,7 +771,7 @@ static void gen_pool16c_insn(DisasContext *ctx)\n int offset = ZIMM(ctx->opcode, 0, 4);\n \n gen_ldst_multiple(ctx, LWM32, lwm_convert[(ctx->opcode >> 4) & 0x3],\n- 29, offset << 2);\n+ 29, offset << 2, MO_ALIGN);\n }\n break;\n case SWM16 + 0:\n@@ -784,7 +783,7 @@ static void gen_pool16c_insn(DisasContext *ctx)\n int offset = ZIMM(ctx->opcode, 0, 4);\n \n gen_ldst_multiple(ctx, SWM32, swm_convert[(ctx->opcode >> 4) & 0x3],\n- 29, offset << 2);\n+ 29, offset << 2, MO_ALIGN);\n }\n break;\n case JR16 + 0:\n@@ -887,7 +886,8 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)\n {\n int lwm_converted = 0x11 + extract32(ctx->opcode, 8, 2);\n int offset = extract32(ctx->opcode, 4, 4);\n- gen_ldst_multiple(ctx, LWM32, lwm_converted, 29, offset << 2);\n+ gen_ldst_multiple(ctx, LWM32, lwm_converted, 29, offset << 2,\n+ MO_UNALN);\n }\n break;\n case R6_JRC16: /* JRCADDIUSP */\n@@ -927,7 +927,8 @@ static void gen_pool16c_r6_insn(DisasContext *ctx)\n {\n int swm_converted = 0x11 + extract32(ctx->opcode, 8, 2);\n int offset = extract32(ctx->opcode, 4, 4);\n- gen_ldst_multiple(ctx, SWM32, swm_converted, 29, offset << 2);\n+ gen_ldst_multiple(ctx, SWM32, swm_converted, 29, offset << 2,\n+ MO_UNALN);\n }\n break;\n case JALRC16: /* BREAK16, SDBBP16 */\n@@ -1861,7 +1862,8 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx)\n /* fall through */\n case LWM32:\n case SWM32:\n- gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12));\n+ gen_ldst_multiple(ctx, minor, rt, rs, SIMM(ctx->opcode, 0, 12),\n+ MO_ALIGN);\n break;\n default:\n MIPS_INVAL(\"pool32b\");\n", "prefixes": [ "v4", "4/4" ] }