[{"id":3678427,"web_url":"http://patchwork.ozlabs.org/comment/3678427/","msgid":"","list_archive_url":null,"date":"2026-04-16T23:07:20","subject":"Re: [PATCH v4 4/4] target/mips: Check alignment for microMIPS pre-R6\n LD/ST multiple","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/17/26 07:05, Philippe Mathieu-Daudé wrote:\n> Pre-REL6 microMIPS requires alignment while REL6 microMIPS does not.\n> Pass the MemOp alignment as argument to gen_ldst_multiple(). Keep\n> using MO_UNALN for REL6 decoder but use MO_ALIGN for the pre-REL6\n> part.\n> \n> Fixes: 3c824109da0 (\"target-mips: microMIPS ASE support\")\n> Reported-by: Richard Henderson\n> Signed-off-by: Philippe Mathieu-Daudé\n> ---\n> target/mips/tcg/micromips_translate.c.inc | 16 +++++++++-------\n> 1 file changed, 9 insertions(+), 7 deletions(-)\n\nReviewed-by: Richard Henderson \n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=MnjYbu4F;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxYZL6mhKz1yCv\n\tfor ; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::532;\n envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3678466,"web_url":"http://patchwork.ozlabs.org/comment/3678466/","msgid":"<4aa2a069-a7c3-48cd-b8ca-4b03adaa1227@linaro.org>","list_archive_url":null,"date":"2026-04-17T03:29:59","subject":"Re: [PATCH v4 4/4] target/mips: Check alignment for microMIPS pre-R6\n LD/ST multiple","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 17/4/26 01:07, Richard Henderson wrote:\n> On 4/17/26 07:05, Philippe Mathieu-Daudé wrote:\n>> Pre-REL6 microMIPS requires alignment while REL6 microMIPS does not.\n>> Pass the MemOp alignment as argument to gen_ldst_multiple(). Keep\n>> using MO_UNALN for REL6 decoder but use MO_ALIGN for the pre-REL6\n>> part.\n>>\n>> Fixes: 3c824109da0 (\"target-mips: microMIPS ASE support\")\n>> Reported-by: Richard Henderson\n>> Signed-off-by: Philippe Mathieu-Daudé\n>> ---\n>>   target/mips/tcg/micromips_translate.c.inc | 16 +++++++++-------\n>>   1 file changed, 9 insertions(+), 7 deletions(-)\n> \n> Reviewed-by: Richard Henderson \n\nI'm not sure about our testing coverage here; I think I should\nuse default_tcg_memop_mask in a previous patch, see\nmips_tr_init_disas_context():\n\n ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&\n (ctx->insn_flags & (ISA_MIPS_R6 |\n INSN_LOONGSON3A))) ? MO_UNALN\n : MO_ALIGN;","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=ZbsZVYML;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxgS52b3Lz1yHp\n\tfor ; Fri, 17 Apr 2026 13:32:37 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDZuI-0003Hw-Ed; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2a00:1450:4864:20::436;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3678468,"web_url":"http://patchwork.ozlabs.org/comment/3678468/","msgid":"","list_archive_url":null,"date":"2026-04-17T03:37:58","subject":"Re: [PATCH v4 4/4] target/mips: Check alignment for microMIPS pre-R6\n LD/ST multiple","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/17/26 13:29, Philippe Mathieu-Daudé wrote:\n> On 17/4/26 01:07, Richard Henderson wrote:\n>> On 4/17/26 07:05, Philippe Mathieu-Daudé wrote:\n>>> Pre-REL6 microMIPS requires alignment while REL6 microMIPS does not.\n>>> Pass the MemOp alignment as argument to gen_ldst_multiple(). Keep\n>>> using MO_UNALN for REL6 decoder but use MO_ALIGN for the pre-REL6\n>>> part.\n>>>\n>>> Fixes: 3c824109da0 (\"target-mips: microMIPS ASE support\")\n>>> Reported-by: Richard Henderson\n>>> Signed-off-by: Philippe Mathieu-Daudé\n>>> ---\n>>>   target/mips/tcg/micromips_translate.c.inc | 16 +++++++++-------\n>>>   1 file changed, 9 insertions(+), 7 deletions(-)\n>>\n>> Reviewed-by: Richard Henderson \n> \n> I'm not sure about our testing coverage here; I think I should\n> use default_tcg_memop_mask in a previous patch, see\n> mips_tr_init_disas_context():\n> \n>    ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&\n>                                   (ctx->insn_flags & (ISA_MIPS_R6 |\n>                                   INSN_LOONGSON3A))) ? MO_UNALN\n>                                                      : MO_ALIGN;\n\nThat sounds good as well.\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=GTf39ZKm;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxgZv06P0z1yGt\n\tfor ; Fri, 17 Apr 2026 13:38:29 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDa1y-0005cz-Jf; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::632;\n envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3678469,"web_url":"http://patchwork.ozlabs.org/comment/3678469/","msgid":"","list_archive_url":null,"date":"2026-04-17T03:43:34","subject":"Re: [PATCH v4 4/4] target/mips: Check alignment for microMIPS pre-R6\n LD/ST multiple","submitter":{"id":85046,"url":"http://patchwork.ozlabs.org/api/people/85046/","name":"Philippe Mathieu-Daudé","email":"philmd@linaro.org"},"content":"On 17/4/26 05:29, Philippe Mathieu-Daudé wrote:\n> On 17/4/26 01:07, Richard Henderson wrote:\n>> On 4/17/26 07:05, Philippe Mathieu-Daudé wrote:\n>>> Pre-REL6 microMIPS requires alignment while REL6 microMIPS does not.\n>>> Pass the MemOp alignment as argument to gen_ldst_multiple(). Keep\n>>> using MO_UNALN for REL6 decoder but use MO_ALIGN for the pre-REL6\n>>> part.\n>>>\n>>> Fixes: 3c824109da0 (\"target-mips: microMIPS ASE support\")\n>>> Reported-by: Richard Henderson\n>>> Signed-off-by: Philippe Mathieu-Daudé\n>>> ---\n>>>   target/mips/tcg/micromips_translate.c.inc | 16 +++++++++-------\n>>>   1 file changed, 9 insertions(+), 7 deletions(-)\n>>\n>> Reviewed-by: Richard Henderson \n> \n> I'm not sure about our testing coverage here; I think I should\n> use default_tcg_memop_mask in a previous patch, see\n> mips_tr_init_disas_context():\n> \n>    ctx->default_tcg_memop_mask = (!(ctx->insn_flags & ISA_NANOMIPS32) &&\n>                                   (ctx->insn_flags & (ISA_MIPS_R6 |\n>                                   INSN_LOONGSON3A))) ? MO_UNALN\n>                                                      : MO_ALIGN;\n\nThis comes from commit be3a8c53b4f (\"target-mips: Misaligned memory\naccesses for R6\").\n\nThinking about it, 'default_tcg_memop_mask' might be a misleading name.\n\n'[default_]mo_align' is clearly more explicit. Or maybe even better\nwould be to make it explicit in the relevant call paths?","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=R418J8F3;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fxgjT5ZvWz1yDF\n\tfor ; Fri, 17 Apr 2026 13:44:12 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wDa7O-0006Jm-6K; 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