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GET /api/patches/2224107/?format=api
{ "id": 2224107, "url": "http://patchwork.ozlabs.org/api/patches/2224107/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416200513.27100-3-philmd@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260416200513.27100-3-philmd@linaro.org>", "list_archive_url": null, "date": "2026-04-16T20:05:13", "name": "[v5,2/2] target/mips: Use probe_access_full() in Atomic Load/Store helpers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "022daac2206f8aeb1ad9b963c7fd5eae7dd25756", "submitter": { "id": 85046, "url": "http://patchwork.ozlabs.org/api/people/85046/?format=api", "name": "Philippe Mathieu-Daudé", "email": "philmd@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260416200513.27100-3-philmd@linaro.org/mbox/", "series": [ { "id": 500201, "url": "http://patchwork.ozlabs.org/api/series/500201/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500201", "date": "2026-04-16T20:05:11", "name": "target/mips: Use probe_access_full() in Atomic Load/Store helpers", "version": 5, "mbox": "http://patchwork.ozlabs.org/series/500201/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2224107/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2224107/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=QEhotvu2;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Received-SPF": "pass client-ip=2a00:1450:4864:20::42b;\n envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Let the probe_access() API check the address alignment\n(request MO_ALIGN in the MemOp bits).\n\nMove env->CP0_LLAddr and env->lladdr assignments so we\ndon't update them when an alignment fault occurs.\n\nSince we have a handy MemOpIdx, replace the legacy\ncpu_ld*_mmuidx_ra() calls by cpu_ld*_mmu() equivalent.\n\nSuggested-by: Richard Henderson <richard.henderson@linaro.org>\nSigned-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>\n---\n target/mips/tcg/ldst_helper.c | 21 +++++++++++++++------\n target/mips/tcg/translate.c | 2 +-\n 2 files changed, 16 insertions(+), 7 deletions(-)", "diff": "diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c\nindex b725c6d0333..4ebf72d610e 100644\n--- a/target/mips/tcg/ldst_helper.c\n+++ b/target/mips/tcg/ldst_helper.c\n@@ -28,23 +28,32 @@\n #include \"internal.h\"\n \n #ifndef CONFIG_USER_ONLY\n+#include \"accel/tcg/probe.h\"\n+#include \"exec/tlb-flags.h\"\n \n #define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \\\n target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, \\\n uint32_t memop_idx) \\\n { \\\n- MemOpIdx oi = memop_idx; \\\n- unsigned mem_idx = get_mmuidx(oi); \\\n- if (arg & almask) { \\\n+ MemOpIdx oi = memop_idx; \\\n+ unsigned mem_idx = get_mmuidx(oi); \\\n+ unsigned size = memop_size(get_memop(oi)); \\\n+ uintptr_t ra = GETPC(); \\\n+ CPUTLBEntryFull *full; \\\n+ void *host_unused; \\\n+ int flags; \\\n+ \\\n+ env->llval = do_cast cpu_##insn##_mmu(env, arg, oi, ra); \\\n+ flags = probe_access_full(env, arg, size, MMU_DATA_LOAD, mem_idx, \\\n+ true, &host_unused, &full, ra); \\\n+ if (unlikely(flags & TLB_INVALID_MASK)) { \\\n if (!(env->hflags & MIPS_HFLAG_DM)) { \\\n env->CP0_BadVAddr = arg; \\\n } \\\n do_raise_exception(env, EXCP_AdEL, GETPC()); \\\n } \\\n- env->CP0_LLAddr = cpu_mips_translate_address(env, arg, MMU_DATA_LOAD, \\\n- GETPC()); \\\n+ env->CP0_LLAddr = full->phys_addr; \\\n env->lladdr = arg; \\\n- env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \\\n return env->llval; \\\n }\n HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t))\ndiff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c\nindex 839bfe18bab..4889bd1e518 100644\n--- a/target/mips/tcg/translate.c\n+++ b/target/mips/tcg/translate.c\n@@ -1936,7 +1936,7 @@ static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx_ignored, \\\n static inline void op_ld_##insn(TCGv ret, TCGv arg1, int mem_idx, \\\n DisasContext *ctx) \\\n { \\\n- MemOpIdx oi = make_memop_idx(memop, mem_idx); \\\n+ MemOpIdx oi = make_memop_idx(memop | MO_ALIGN, mem_idx); \\\n gen_helper_##insn(ret, tcg_env, arg1, tcg_constant_i32(oi)); \\\n }\n #endif\n", "prefixes": [ "v5", "2/2" ] }