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GET /api/patches/2222983/?format=api
{ "id": 2222983, "url": "http://patchwork.ozlabs.org/api/patches/2222983/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260414065214.3085209-1-yadu.mg@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260414065214.3085209-1-yadu.mg@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-04-14T06:52:14", "name": "PCI: dwc: Initialize pp->lock before MSI domain registration", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8e02f2494ebd2928e0d8ba68bca4247f837be906", "submitter": { "id": 93138, "url": "http://patchwork.ozlabs.org/api/people/93138/?format=api", "name": "Yadu M G", "email": "yadu.mg@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260414065214.3085209-1-yadu.mg@oss.qualcomm.com/mbox/", "series": [ { "id": 499787, "url": "http://patchwork.ozlabs.org/api/series/499787/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=499787", "date": "2026-04-14T06:52:14", "name": "PCI: dwc: Initialize pp->lock before MSI domain registration", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/499787/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222983/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222983/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-52475-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=A0pCNWU8;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=jyZCbn1v;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-52475-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"A0pCNWU8\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"jyZCbn1v\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.168.131", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com" ], "Received": [ "from tor.lore.kernel.org (tor.lore.kernel.org\n [IPv6:2600:3c04:e001:36c::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4fvw225f97z1y2d\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 14 Apr 2026 16:52:26 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby tor.lore.kernel.org (Postfix) with ESMTP id C96DE3015A4D\n\tfor <incoming@patchwork.ozlabs.org>; Tue, 14 Apr 2026 06:52:23 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 919EB332EBC;\n\tTue, 14 Apr 2026 06:52:23 +0000 (UTC)", "from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com\n [205.220.168.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 2564133FE15\n\tfor <linux-pci@vger.kernel.org>; Tue, 14 Apr 2026 06:52:20 +0000 (UTC)", "from pps.filterd (m0279866.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 63E6V9lj1479046\n\tfor <linux-pci@vger.kernel.org>; Tue, 14 Apr 2026 06:52:20 GMT", "from mail-pg1-f198.google.com (mail-pg1-f198.google.com\n [209.85.215.198])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4dh87j1e9n-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor <linux-pci@vger.kernel.org>; Tue, 14 Apr 2026 06:52:20 +0000 (GMT)", "by mail-pg1-f198.google.com with SMTP id\n 41be03b00d2f7-c769b25315eso6364284a12.2\n for <linux-pci@vger.kernel.org>; Mon, 13 Apr 2026 23:52:20 -0700 (PDT)", "from hu-ymg-blr.qualcomm.com\n (blr-bdr-fw-01_GlobalNAT_AllZones-Outside.qualcomm.com. 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However,\nsome DWC glue drivers like those on Qcom firmware managed platforms\nallocate MSI domains from their .msi_init callback by calling\ndw_pcie_allocate_domains() directly, bypassing dw_pcie_host_init(). This\nleaves pp->lock without a lockdep key and triggers the warning when MSI\nvectors are later allocated.\n\nInitialize pp->lock in dw_pcie_allocate_domains() immediately before\nregistering the MSI IRQ domain so the lock is always initialized for\nevery caller path.\n\nSigned-off-by: Yadu M G <yadu.mg@oss.qualcomm.com>\n---\n drivers/pci/controller/dwc/pcie-designware-host.c | 10 ++++++++--\n 1 file changed, 8 insertions(+), 2 deletions(-)", "diff": "diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c\nindex c9517a348836..8acd671bbc8c 100644\n--- a/drivers/pci/controller/dwc/pcie-designware-host.c\n+++ b/drivers/pci/controller/dwc/pcie-designware-host.c\n@@ -215,6 +215,14 @@ int dw_pcie_allocate_domains(struct dw_pcie_rp *pp)\n \t\t.host_data\t= pp,\n \t};\n \n+\t/*\n+\t * Initialize the lock here rather than in dw_pcie_host_init() so that\n+\t * drivers using a custom msi_init() callback that call\n+\t * dw_pcie_allocate_domains() directly also have the lock properly\n+\t * initialized before dw_pcie_irq_domain_alloc() can be invoked.\n+\t */\n+\traw_spin_lock_init(&pp->lock);\n+\n \tpp->irq_domain = msi_create_parent_irq_domain(&info, &dw_pcie_msi_parent_ops);\n \tif (!pp->irq_domain) {\n \t\tdev_err(pci->dev, \"Failed to create IRQ domain\\n\");\n@@ -573,8 +581,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp)\n \tstruct pci_host_bridge *bridge;\n \tint ret;\n \n-\traw_spin_lock_init(&pp->lock);\n-\n \tbridge = devm_pci_alloc_host_bridge(dev, 0);\n \tif (!bridge)\n \t\treturn -ENOMEM;\n", "prefixes": [] }