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GET /api/patches/2222940/?format=api
{ "id": 2222940, "url": "http://patchwork.ozlabs.org/api/patches/2222940/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/patch/CAMe9rOq+_EEsMPh2RZwEeVU7vHyeOk-Y8c2undYyPj4APUngmQ@mail.gmail.com/", "project": { "id": 17, "url": "http://patchwork.ozlabs.org/api/projects/17/?format=api", "name": "GNU Compiler Collection", "link_name": "gcc", "list_id": "gcc-patches.gcc.gnu.org", "list_email": "gcc-patches@gcc.gnu.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<CAMe9rOq+_EEsMPh2RZwEeVU7vHyeOk-Y8c2undYyPj4APUngmQ@mail.gmail.com>", "list_archive_url": null, "date": "2026-04-14T04:22:13", "name": "[v2] x86: Zero ZMM16-31 when zeroing all call used registers", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b455a410cce9733b9fcfa7d3fa445b2df49ec0ef", "submitter": { "id": 4387, "url": "http://patchwork.ozlabs.org/api/people/4387/?format=api", "name": "H.J. Lu", "email": "hjl.tools@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/gcc/patch/CAMe9rOq+_EEsMPh2RZwEeVU7vHyeOk-Y8c2undYyPj4APUngmQ@mail.gmail.com/mbox/", "series": [ { "id": 499774, "url": "http://patchwork.ozlabs.org/api/series/499774/?format=api", "web_url": "http://patchwork.ozlabs.org/project/gcc/list/?series=499774", "date": "2026-04-14T04:22:13", "name": "[v2] x86: Zero ZMM16-31 when zeroing all call used registers", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/499774/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2222940/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2222940/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Delivered-To": [ "patchwork-incoming@legolas.ozlabs.org", "gcc-patches@gcc.gnu.org" ], "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=FKW6Ol/f;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org\n (client-ip=2620:52:6:3111::32; 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Mon, 13 Apr 2026\n 21:22:50 -0700 (PDT)", "MIME-Version": "1.0", "References": "\n <CAMe9rOqSgqth1hy3Gp8KUivtui8HpPvz5vSOtwsqsoNym5a1Ew@mail.gmail.com>\n <CAMZc-byfoxciwUYE+G8yJHWpJ+NAYX4UFbPtW+Bf=azuwSk2SQ@mail.gmail.com>", "In-Reply-To": "\n <CAMZc-byfoxciwUYE+G8yJHWpJ+NAYX4UFbPtW+Bf=azuwSk2SQ@mail.gmail.com>", "From": "\"H.J. Lu\" <hjl.tools@gmail.com>", "Date": "Tue, 14 Apr 2026 12:22:13 +0800", "X-Gm-Features": "AQROBzCcn2ce8334zGZnx2l4JzRKgds7iHFWuI0gJyr2CVMTXpeeNuATh6zu8nA", "Message-ID": "\n <CAMe9rOq+_EEsMPh2RZwEeVU7vHyeOk-Y8c2undYyPj4APUngmQ@mail.gmail.com>", "Subject": "[PATCH v2] x86: Zero ZMM16-31 when zeroing all call used registers", "To": "Hongtao Liu <crazylht@gmail.com>", "Cc": "GCC Patches <gcc-patches@gcc.gnu.org>, Uros Bizjak <ubizjak@gmail.com>,\n Hongtao Liu <hongtao.liu@intel.com>, thiago@kde.org", "Content-Type": "multipart/mixed; boundary=\"000000000000c23bd7064f63f309\"", "X-BeenThere": "gcc-patches@gcc.gnu.org", "X-Mailman-Version": "2.1.30", "Precedence": "list", "List-Id": "Gcc-patches mailing list <gcc-patches.gcc.gnu.org>", "List-Unsubscribe": "<https://gcc.gnu.org/mailman/options/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=unsubscribe>", "List-Archive": "<https://gcc.gnu.org/pipermail/gcc-patches/>", "List-Post": "<mailto:gcc-patches@gcc.gnu.org>", "List-Help": "<mailto:gcc-patches-request@gcc.gnu.org?subject=help>", "List-Subscribe": "<https://gcc.gnu.org/mailman/listinfo/gcc-patches>,\n <mailto:gcc-patches-request@gcc.gnu.org?subject=subscribe>", "Errors-To": "gcc-patches-bounces~incoming=patchwork.ozlabs.org@gcc.gnu.org" }, "content": "On Tue, Apr 14, 2026 at 11:33 AM Hongtao Liu <crazylht@gmail.com> wrote:\n>\n> On Tue, Apr 14, 2026 at 11:15 AM H.J. Lu <hjl.tools@gmail.com> wrote:\n> >\n> > When zeroing all call used registers with AVX512F enabled, zero ZMM16-31\n> > explicitly since vzeroall doesn't touch ZMM16-31. Also add a test for\n> > zeroing all call used registers with both AVX512F and APX enabled.\n> >\n> /* first, let's see whether we can zero all vector registers together. */\n> - rtx zero_all_vec_insn = zero_all_vector_registers (need_zeroed_hardregs);\n> + rtx zero_all_vec_insn\n> + = zero_all_vector_registers (need_zeroed_hardregs,\n> + need_zero_xmm16_to_31);\n> if (zero_all_vec_insn)\n> {\n> emit_insn (zero_all_vec_insn);\n> all_sse_zeroed = true;\n> + if (need_zero_xmm16_to_31)\n>\n> Can we just have if (TARGET_64BIT && TARGET_AVX512F) here?\n> And adjust comments of zero_all_vector_registers since it only zero xmm1-xmm15.\n>\n\nChecking if (TARGET_64BIT && TARGET_AVX512F) is the simplest change.\nHere is the v2 patch.\n\nWhen zeroing all call used registers with AVX512F enabled, zero ZMM16-31\nexplicitly since vzeroall doesn't touch ZMM16-31. Also add a test for\nzeroing all call used registers with both AVX512F and APX enabled.\n\ngcc/\n\nPR target/124876\n* config/i386/i386.cc (ix86_zero_call_used_regs): Zero ZMM16-31\nif needed.\n\ngcc/testsuite/\n\nPR target/124876\n* gcc.target/i386/zero-scratch-regs-23.c: Scan vpxord on ZMM16-31.\n* gcc.target/i386/zero-scratch-regs-33.c: New test.", "diff": "From c9b366a4b5afa30e0f4dd5022ab74cbc47207ae7 Mon Sep 17 00:00:00 2001\nFrom: \"H.J. Lu\" <hjl.tools@gmail.com>\nDate: Tue, 14 Apr 2026 11:06:31 +0800\nSubject: [PATCH v2] x86: Zero ZMM16-31 when zeroing all call used registers\n\nWhen zeroing all call used registers with AVX512F enabled, zero ZMM16-31\nexplicitly since vzeroall doesn't touch ZMM16-31. Also add a test for\nzeroing all call used registers with both AVX512F and APX enabled.\n\ngcc/\n\n\tPR target/124876\n\t* config/i386/i386.cc (ix86_zero_call_used_regs): Zero ZMM16-31\n\tif needed.\n\ngcc/testsuite/\n\n\tPR target/124876\n\t* gcc.target/i386/zero-scratch-regs-23.c: Scan vpxord on ZMM16-31.\n\t* gcc.target/i386/zero-scratch-regs-33.c: New test.\n\nSigned-off-by: H.J. Lu <hjl.tools@gmail.com>\n---\n gcc/config/i386/i386.cc | 11 ++++\n .../gcc.target/i386/zero-scratch-regs-23.c | 16 +++++\n .../gcc.target/i386/zero-scratch-regs-33.c | 60 +++++++++++++++++++\n 3 files changed, 87 insertions(+)\n create mode 100644 gcc/testsuite/gcc.target/i386/zero-scratch-regs-33.c\n\ndiff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc\nindex dd017bc7ac3..c93ea383668 100644\n--- a/gcc/config/i386/i386.cc\n+++ b/gcc/config/i386/i386.cc\n@@ -4078,6 +4078,17 @@ ix86_zero_call_used_regs (HARD_REG_SET need_zeroed_hardregs)\n {\n emit_insn (zero_all_vec_insn);\n all_sse_zeroed = true;\n+ if (TARGET_64BIT && TARGET_AVX512F)\n+\t{\n+\t rtx zero = CONST0_RTX (V4SFmode);\n+\t for (unsigned int regno = XMM16_REG;\n+\t regno <= XMM31_REG;\n+\t regno++)\n+\t {\n+\t rtx reg = gen_rtx_REG (V4SFmode, regno);\n+\t emit_move_insn (reg, zero);\n+\t }\n+\t}\n }\n \n /* mm/st registers are shared registers set, we should follow the following\ndiff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c\nindex a3285bed8a0..397893faa6c 100644\n--- a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c\n+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-23.c\n@@ -7,6 +7,22 @@ foo (void)\n }\n \n /* { dg-final { scan-assembler \"vzeroall\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm16, %zmm16, %zmm16\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm17, %zmm17, %zmm17\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm18, %zmm18, %zmm18\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm19, %zmm19, %zmm19\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm20, %zmm20, %zmm20\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm21, %zmm21, %zmm21\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm22, %zmm22, %zmm22\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm23, %zmm23, %zmm23\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm24, %zmm24, %zmm24\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm25, %zmm25, %zmm25\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm26, %zmm26, %zmm26\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm27, %zmm27, %zmm27\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm28, %zmm28, %zmm28\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm29, %zmm29, %zmm29\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm30, %zmm30, %zmm30\" { target { ! ia32 } } } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm31, %zmm31, %zmm31\" { target { ! ia32 } } } } */\n /* { dg-final { scan-assembler-times \"fldz\" 8 } } */\n /* { dg-final { scan-assembler-times \"fstp\\[ \\t\\]+%st\\\\(0\\\\)\" 8 } } */\n /* { dg-final { scan-assembler-not \"%xmm\" } } */\ndiff --git a/gcc/testsuite/gcc.target/i386/zero-scratch-regs-33.c b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-33.c\nnew file mode 100644\nindex 00000000000..f40fe2a5377\n--- /dev/null\n+++ b/gcc/testsuite/gcc.target/i386/zero-scratch-regs-33.c\n@@ -0,0 +1,60 @@\n+/* { dg-do compile { target { *-*-linux* && { ! ia32 } } } } */\n+/* { dg-options \"-O2 -fzero-call-used-regs=all -march=corei7 -mavx512f -mapxf\" } */\n+\n+void\n+foo (void)\n+{\n+}\n+\n+/* { dg-final { scan-assembler \"vzeroall\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm16, %zmm16, %zmm16\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm17, %zmm17, %zmm17\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm18, %zmm18, %zmm18\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm19, %zmm19, %zmm19\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm20, %zmm20, %zmm20\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm21, %zmm21, %zmm21\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm22, %zmm22, %zmm22\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm23, %zmm23, %zmm23\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm24, %zmm24, %zmm24\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm25, %zmm25, %zmm25\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm26, %zmm26, %zmm26\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm27, %zmm27, %zmm27\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm28, %zmm28, %zmm28\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm29, %zmm29, %zmm29\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm30, %zmm30, %zmm30\" } } */\n+/* { dg-final { scan-assembler \"vpxord\\[ \\t\\]+%zmm31, %zmm31, %zmm31\" } } */\n+/* { dg-final { scan-assembler-times \"fldz\" 8 } } */\n+/* { dg-final { scan-assembler-times \"fstp\\[ \\t\\]+%st\\\\(0\\\\)\" 8 } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%eax, %eax\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%edx, %edx\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%ecx, %ecx\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%esi, %esi\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%edi, %edi\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r8d, %r8d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r9d, %r9d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r10d, %r10d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r11d, %r11d\" } } */\n+/* { dg-final { scan-assembler \"kxorw\\[ \\t\\]+%k0, %k0, %k0\" } } */\n+/* { dg-final { scan-assembler \"kxorw\\[ \\t\\]+%k1, %k1, %k1\" } } */\n+/* { dg-final { scan-assembler \"kxorw\\[ \\t\\]+%k2, %k2, %k2\" } } */\n+/* { dg-final { scan-assembler \"kxorw\\[ \\t\\]+%k3, %k3, %k3\" } } */\n+/* { dg-final { scan-assembler \"kxorw\\[ \\t\\]+%k4, %k4, %k4\" } } */\n+/* { dg-final { scan-assembler \"kxorw\\[ \\t\\]+%k5, %k5, %k5\" } } */\n+/* { dg-final { scan-assembler \"kxorw\\[ \\t\\]+%k6, %k6, %k6\" } } */\n+/* { dg-final { scan-assembler \"kxorw\\[ \\t\\]+%k7, %k7, %k7\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r16d, %r16d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r17d, %r17d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r18d, %r18d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r19d, %r19d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r20d, %r20d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r21d, %r21d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r22d, %r22d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r23d, %r23d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r24d, %r24d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r25d, %r25d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r26d, %r26d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r27d, %r27d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r28d, %r28d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r29d, %r29d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r30d, %r30d\" } } */\n+/* { dg-final { scan-assembler \"xorl\\[ \\t\\]+%r31d, %r31d\" } } */\n-- \n2.53.0\n\n", "prefixes": [ "v2" ] }