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GET /api/patches/1340954/?format=api
{ "id": 1340954, "url": "http://patchwork.ozlabs.org/api/patches/1340954/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/20200804173223.36280-2-svaidy@linux.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200804173223.36280-2-svaidy@linux.ibm.com>", "list_archive_url": null, "date": "2020-08-04T17:32:13", "name": "[v6,01/11] Add basic P9 fused core support", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "96b208cb17a4d3ff629625c5e242b8eb21909e24", "submitter": { "id": 76774, "url": "http://patchwork.ozlabs.org/api/people/76774/?format=api", "name": "Vaidyanathan Srinivasan", "email": "svaidy@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/20200804173223.36280-2-svaidy@linux.ibm.com/mbox/", "series": [ { "id": 194127, "url": "http://patchwork.ozlabs.org/api/series/194127/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/list/?series=194127", "date": "2020-08-04T17:32:14", "name": "Initial fused-core support for POWER9", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/194127/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1340954/comments/", "check": "success", "checks": "http://patchwork.ozlabs.org/api/patches/1340954/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4BLhls6MZPz9sTK\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 5 Aug 2020 03:37:29 +1000 (AEST)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4BLhls1HfpzDqNg\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 5 Aug 2020 03:37:29 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n [148.163.158.5])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhgY4jCCzDqY1\n for <skiboot@lists.ozlabs.org>; Wed, 5 Aug 2020 03:33:45 +1000 (AEST)", "from pps.filterd (m0098419.ppops.net [127.0.0.1])\n by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 074HXSvq025353; Tue, 4 Aug 2020 13:33:39 -0400", "from pps.reinject (localhost [127.0.0.1])\n by mx0b-001b2d01.pphosted.com with ESMTP id 32q9gmn49t-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 04 Aug 2020 13:33:39 -0400", "from m0098419.ppops.net (m0098419.ppops.net [127.0.0.1])\n by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HXcq0026045;\n Tue, 4 Aug 2020 13:33:38 -0400", "from ppma05fra.de.ibm.com (6c.4a.5195.ip4.static.sl-reverse.com\n [149.81.74.108])\n by mx0b-001b2d01.pphosted.com with ESMTP id 32q9gmn3tm-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 04 Aug 2020 13:33:38 -0400", "from pps.filterd (ppma05fra.de.ibm.com [127.0.0.1])\n by ppma05fra.de.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HPfqB027064;\n Tue, 4 Aug 2020 17:32:32 GMT", "from b06cxnps3075.portsmouth.uk.ibm.com\n (d06relay10.portsmouth.uk.ibm.com [9.149.109.195])\n by ppma05fra.de.ibm.com with ESMTP id 32n017t5f1-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 04 Aug 2020 17:32:32 +0000", "from b06wcsmtp001.portsmouth.uk.ibm.com\n (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160])\n by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n 074HWUQi28180826\n (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Tue, 4 Aug 2020 17:32:30 GMT", "from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 35B89A4060;\n Tue, 4 Aug 2020 17:32:30 +0000 (GMT)", "from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 2012FA4065;\n Tue, 4 Aug 2020 17:32:29 +0000 (GMT)", "from drishya.in.ibm.com (unknown [9.102.1.52])\n by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n Tue, 4 Aug 2020 17:32:28 +0000 (GMT)" ], "Authentication-Results": [ "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=linux.ibm.com", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5;\n helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com;\n receiver=<UNKNOWN>)", "lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=linux.ibm.com" ], "From": "Vaidyanathan Srinivasan <svaidy@linux.ibm.com>", "To": "\"Oliver O'Halloran\" <oohall@gmail.com>", "Date": "Tue, 4 Aug 2020 23:02:13 +0530", "Message-Id": "<20200804173223.36280-2-svaidy@linux.ibm.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20200804173223.36280-1-svaidy@linux.ibm.com>", "References": "<20200804173223.36280-1-svaidy@linux.ibm.com>", "MIME-Version": "1.0", "X-TM-AS-GCONF": "00", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-08-04_04:2020-08-03,\n 2020-08-04 signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n mlxlogscore=999 clxscore=1015\n priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0\n malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 spamscore=0\n suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2006250000 definitions=main-2008040126", "Subject": "[Skiboot] [PATCH v6 01/11] Add basic P9 fused core support", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n <mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n <mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Cc": "skiboot@lists.ozlabs.org, Michael Neuling <mikey@neuling.org>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n <skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "From: Ryan Grimm <grimm@linux.vnet.ibm.com>\n\nP9 cores can be configured into fused core mode where two core chiplets\nfunction as an 8-threaded, single core. So, bump four to eight in boot_entry\nwhen in fused core mode and cpu_thread_count in init_boot_cpu.\n\nThe HID, AMOR, TSCR, RPR require the first active thread on that core chiplet\nto load the copy for that core chiplet. So, send thread 1 of a fused core to\ninit_shared_sprs in boot_entry.\n\nThe code checks for fused core mode in the core thead state register and puts a\nfield in struct cpu_thread. This flag is checked when updating the HID and in\nXIVE code when setting the special bar.\n\nFor XSCOM, the core ID is the non-fused EX. So, create macros to arrange the\nbits. It's fairly verbose but somewhat readable.\n\nThis was tested on a P9 ZZ with 16 fused cores and ran HTX for over 24 hours.\n\nSigned-off-by: Ryan Grimm <grimm@linux.vnet.ibm.com>\nSigned-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>\nSigned-off-by: Michael Neuling <mikey@neuling.org>\nSigned-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>\n---\n asm/head.S | 25 ++++++++++++++++++++++---\n core/chip.c | 19 +++++++++++++------\n core/cpu.c | 31 ++++++++++++++++++++++++++-----\n hdata/test/hdata_to_dt.c | 9 ++++++++-\n hw/xive.c | 2 +-\n include/chip.h | 31 +++++++++++++++++++++++++++++++\n include/cpu.h | 6 ++++++\n include/xscom.h | 3 +++\n 8 files changed, 110 insertions(+), 16 deletions(-)", "diff": "diff --git a/asm/head.S b/asm/head.S\nindex 3b41815c..0b81bb51 100644\n--- a/asm/head.S\n+++ b/asm/head.S\n@@ -324,6 +324,7 @@ boot_offset:\n * r28 : PVR\n * r27 : DTB pointer (or NULL)\n * r26 : PIR thread mask\n+ * r25 : P9 fused core flag\n */\n .global boot_entry\n boot_entry:\n@@ -338,13 +339,22 @@ boot_entry:\n \tcmpwi\tcr0,%r3,PVR_TYPE_P8NVL\n \tbeq\t2f\n \tcmpwi\tcr0,%r3,PVR_TYPE_P9\n-\tbeq \t1f\n+\tbeq \t3f\n \tcmpwi\tcr0,%r3,PVR_TYPE_P9P\n-\tbeq \t1f\n+\tbeq \t3f\n \tattn\t\t/* Unsupported CPU type... what do we do ? */\n \tb \t.\t/* loop here, just in case attn is disabled */\n \n-\t/* P8 -> 8 threads */\n+\t/* Check for fused core and set flag */\n+3:\n+\tli\t%r3, 0x1e0\n+\tmtspr SPR_SPRC, %r3\n+\tmfspr\t%r3, SPR_SPRD\n+\tandi.\t%r25, %r3, 1\n+\tbeq 1f\n+\n+\t/* P8 or P9 fused -> 8 threads */\n+\n 2:\tli\t%r26,7\n \n \t/* Get our reloc offset into r30 */\n@@ -370,6 +380,15 @@ boot_entry:\n #endif\n \tmtmsrd\t%r3,0\n \n+\t/* If fused, t1 is primary chiplet and must init shared sprs */\n+\tandi.\t%r3,%r25,1\n+\tbeq\tnot_fused\n+\n+\tmfspr\t%r31,SPR_PIR\n+\tandi.\t%r3,%r31,1\n+\tbnel\tinit_shared_sprs\n+\n+not_fused:\n \t/* Check our PIR, avoid threads */\n \tmfspr\t%r31,SPR_PIR\n \tand.\t%r0,%r31,%r26\ndiff --git a/core/chip.c b/core/chip.c\nindex 191432d2..5c3276a4 100644\n--- a/core/chip.c\n+++ b/core/chip.c\n@@ -6,6 +6,7 @@\n #include <console.h>\n #include <device.h>\n #include <timebase.h>\n+#include <cpu.h>\n \n static struct proc_chip *chips[MAX_CHIPS];\n enum proc_chip_quirks proc_chip_quirks;\n@@ -22,9 +23,12 @@ uint32_t pir_to_chip_id(uint32_t pir)\n \n uint32_t pir_to_core_id(uint32_t pir)\n {\n-\tif (proc_gen == proc_gen_p9)\n-\t\treturn P9_PIR2COREID(pir);\n-\telse if (proc_gen == proc_gen_p8)\n+\tif (proc_gen == proc_gen_p9) {\n+\t\tif (this_cpu()->is_fused_core)\n+\t\t\treturn P9_PIRFUSED2NORMALCOREID(pir);\n+\t\telse\n+\t\t\treturn P9_PIR2COREID(pir);\n+\t} else if (proc_gen == proc_gen_p8)\n \t\treturn P8_PIR2COREID(pir);\n \telse\n \t\tassert(false);\n@@ -32,9 +36,12 @@ uint32_t pir_to_core_id(uint32_t pir)\n \n uint32_t pir_to_thread_id(uint32_t pir)\n {\n-\tif (proc_gen == proc_gen_p9)\n-\t\treturn P9_PIR2THREADID(pir);\n-\telse if (proc_gen == proc_gen_p8)\n+\tif (proc_gen == proc_gen_p9) {\n+\t\tif (this_cpu()->is_fused_core)\n+\t\t\treturn P9_PIR2FUSEDTHREADID(pir);\n+\t\telse\n+\t\t\treturn P9_PIR2THREADID(pir);\n+\t} else if (proc_gen == proc_gen_p8)\n \t\treturn P8_PIR2THREADID(pir);\n \telse\n \t\tassert(false);\ndiff --git a/core/cpu.c b/core/cpu.c\nindex 73777dd4..158f73e2 100644\n--- a/core/cpu.c\n+++ b/core/cpu.c\n@@ -932,6 +932,7 @@ static void init_cpu_thread(struct cpu_thread *t,\n #ifdef STACK_CHECK_ENABLED\n \tt->stack_bot_mark = LONG_MAX;\n #endif\n+\tt->is_fused_core = is_fused_core(mfspr(SPR_PVR));\n \tassert(pir == container_of(t, struct cpu_stack, cpu) - cpu_stacks);\n }\n \n@@ -1016,14 +1017,16 @@ void init_boot_cpu(void)\n \t\t \" (max %d threads/core)\\n\", cpu_thread_count);\n \t\tbreak;\n \tcase proc_gen_p9:\n-\t\tcpu_thread_count = 4;\n+\t\tif (is_fused_core(pvr))\n+\t\t\tcpu_thread_count = 8;\n+\t\telse\n+\t\t\tcpu_thread_count = 4;\n \t\tprlog(PR_INFO, \"CPU: P9 generation processor\"\n \t\t \" (max %d threads/core)\\n\", cpu_thread_count);\n \t\tbreak;\n \tdefault:\n \t\tprerror(\"CPU: Unknown PVR, assuming 1 thread\\n\");\n \t\tcpu_thread_count = 1;\n-\t\tcpu_max_pir = mfspr(SPR_PIR);\n \t}\n \n \tif (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) {\n@@ -1151,7 +1154,7 @@ void init_all_cpus(void)\n \n \t/* Iterate all CPUs in the device-tree */\n \tdt_for_each_child(cpus, cpu) {\n-\t\tunsigned int pir, server_no, chip_id;\n+\t\tunsigned int pir, server_no, chip_id, threads;\n \t\tenum cpu_thread_state state;\n \t\tconst struct dt_property *p;\n \t\tstruct cpu_thread *t, *pt;\n@@ -1181,6 +1184,14 @@ void init_all_cpus(void)\n \t\tprlog(PR_INFO, \"CPU: CPU from DT PIR=0x%04x Server#=0x%x\"\n \t\t \" State=%d\\n\", pir, server_no, state);\n \n+\t\t/* Check max PIR */\n+\t\tif (cpu_max_pir < (pir + cpu_thread_count - 1)) {\n+\t\t\tprlog(PR_WARNING, \"CPU: CPU potentially out of range\"\n+\t\t\t \"PIR=0x%04x MAX=0x%04x !\\n\",\n+\t\t\t pir, cpu_max_pir);\n+\t\t\tcontinue;\n+\t\t}\n+\n \t\t/* Setup thread 0 */\n \t\tassert(pir <= cpu_max_pir);\n \t\tt = pt = &cpu_stacks[pir].cpu;\n@@ -1206,11 +1217,21 @@ void init_all_cpus(void)\n \t\t/* Add the decrementer width property */\n \t\tdt_add_property_cells(cpu, \"ibm,dec-bits\", dec_bits);\n \n+\t\tif (t->is_fused_core)\n+\t\t\tdt_add_property(t->node, \"ibm,fused-core\", NULL, 0);\n+\n \t\t/* Iterate threads */\n \t\tp = dt_find_property(cpu, \"ibm,ppc-interrupt-server#s\");\n \t\tif (!p)\n \t\t\tcontinue;\n-\t\tfor (thread = 1; thread < (p->len / 4); thread++) {\n+\t\tthreads = p->len / 4;\n+\t\tif (threads > cpu_thread_count) {\n+\t\t\tprlog(PR_WARNING, \"CPU: Threads out of range for PIR 0x%04x\"\n+\t\t\t \" threads=%d max=%d\\n\",\n+\t\t\t pir, threads, cpu_thread_count);\n+\t\t\tthreads = cpu_thread_count;\n+\t\t}\n+\t\tfor (thread = 1; thread < threads; thread++) {\n \t\t\tprlog(PR_TRACE, \"CPU: secondary thread %d found\\n\",\n \t\t\t thread);\n \t\t\tt = &cpu_stacks[pir + thread].cpu;\n@@ -1396,7 +1417,7 @@ static int64_t cpu_change_all_hid0(struct hid0_change_req *req)\n \tassert(jobs);\n \n \tfor_each_available_cpu(cpu) {\n-\t\tif (!cpu_is_thread0(cpu))\n+\t\tif (!cpu_is_thread0(cpu) && !cpu_is_core_chiplet_primary(cpu))\n \t\t\tcontinue;\n \t\tif (cpu == this_cpu())\n \t\t\tcontinue;\ndiff --git a/hdata/test/hdata_to_dt.c b/hdata/test/hdata_to_dt.c\nindex 49357cdf..90d83f93 100644\n--- a/hdata/test/hdata_to_dt.c\n+++ b/hdata/test/hdata_to_dt.c\n@@ -38,7 +38,11 @@ struct spira_ntuple;\n static void *ntuple_addr(const struct spira_ntuple *n);\n \n /* Stuff which core expects. */\n-#define __this_cpu ((struct cpu_thread *)NULL)\n+struct cpu_thread *my_fake_cpu;\n+static struct cpu_thread *this_cpu(void)\n+{\n+\treturn my_fake_cpu;\n+}\n \n unsigned long tb_hz = 512000000;\n \n@@ -74,6 +78,7 @@ unsigned long tb_hz = 512000000;\n struct cpu_thread {\n \tuint32_t\t\t\tpir;\n \tuint32_t\t\t\tchip_id;\n+\tbool\t\t\t\tis_fused_core;\n };\n struct cpu_job *__cpu_queue_job(struct cpu_thread *cpu,\n \t\t\t\tconst char *name,\n@@ -95,6 +100,8 @@ static inline struct cpu_job *cpu_queue_job(struct cpu_thread *cpu,\n struct cpu_thread __boot_cpu, *boot_cpu = &__boot_cpu;\n static unsigned long fake_pvr = PVR_P8;\n \n+unsigned int cpu_thread_count = 8;\n+\n static inline unsigned long mfspr(unsigned int spr)\n {\n \tassert(spr == SPR_PVR);\ndiff --git a/hw/xive.c b/hw/xive.c\nindex 8d6095c0..626ec182 100644\n--- a/hw/xive.c\n+++ b/hw/xive.c\n@@ -3074,7 +3074,7 @@ static void xive_init_cpu(struct cpu_thread *c)\n \t * of a pair is present we just do the setup for each of them, which\n \t * is harmless.\n \t */\n-\tif (cpu_is_thread0(c))\n+\tif (cpu_is_thread0(c) || cpu_is_core_chiplet_primary(c))\n \t\txive_configure_ex_special_bar(x, c);\n \n \t/* Initialize the state structure */\ndiff --git a/include/chip.h b/include/chip.h\nindex b79b63ec..38fafcf4 100644\n--- a/include/chip.h\n+++ b/include/chip.h\n@@ -56,6 +56,26 @@\n * thus we have a 6-bit core number.\n *\n * Note: XIVE Only supports 4-bit chip numbers ...\n+ *\n+ * Upper PIR Bits\n+ * --------------\n+ *\n+ * Normal-Core Mode:\n+ * 57:61 CoreID\n+ * 62:63 ThreadID\n+ *\n+ * Fused-Core Mode:\n+ * 57:59 FusedQuadID\n+ * 60 FusedCoreID\n+ * 61:63 FusedThreadID\n+ *\n+ * FusedCoreID 0 contains normal-core chiplet 0 and 1\n+ * FusedCoreID 1 contains normal-core chiplet 2 and 3\n+ *\n+ * Fused cores have interleaved threads:\n+ * core chiplet 0/2 = t0, t2, t4, t6\n+ * core chiplet 1/3 = t1, t3, t5, t7\n+ *\n */\n #define P9_PIR2GCID(pir) (((pir) >> 8) & 0x7f)\n \n@@ -67,6 +87,17 @@\n \n #define P9_GCID2CHIPID(gcid) ((gcid) & 0x7)\n \n+#define P9_PIR2FUSEDQUADID(pir) (((pir) >> 4) & 0x7)\n+\n+#define P9_PIR2FUSEDCOREID(pir) (((pir) >> 3) & 0x1)\n+\n+#define P9_PIR2FUSEDTHREADID(pir) ((pir) & 0x7)\n+\n+#define P9_PIRFUSED2NORMALCOREID(pir) \\\n+\t(P9_PIR2FUSEDQUADID(pir) << 2) | \\\n+\t(P9_PIR2FUSEDCOREID(pir) << 1) | \\\n+\t(P9_PIR2FUSEDTHREADID(pir) & 1)\n+\n /* P9 specific ones mostly used by XIVE */\n #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff)\n #define P9_PIRFROMLOCALCPU(chip, cpu)\t(((chip) << 8) | (cpu))\ndiff --git a/include/cpu.h b/include/cpu.h\nindex c90b961f..1863d6ad 100644\n--- a/include/cpu.h\n+++ b/include/cpu.h\n@@ -42,6 +42,7 @@ struct cpu_thread {\n \tuint32_t\t\t\tserver_no;\n \tuint32_t\t\t\tchip_id;\n \tbool\t\t\t\tis_secondary;\n+\tbool\t\t\t\tis_fused_core;\n \tstruct cpu_thread\t\t*primary;\n \tenum cpu_thread_state\t\tstate;\n \tstruct dt_node\t\t\t*node;\n@@ -244,6 +245,11 @@ static inline bool cpu_is_thread0(struct cpu_thread *cpu)\n \treturn cpu->primary == cpu;\n }\n \n+static inline bool cpu_is_core_chiplet_primary(struct cpu_thread *cpu)\n+{\n+\treturn cpu->is_fused_core & (cpu_get_thread_index(cpu) == 1);\n+}\n+\n static inline bool cpu_is_sibling(struct cpu_thread *cpu1,\n \t\t\t\t struct cpu_thread *cpu2)\n {\ndiff --git a/include/xscom.h b/include/xscom.h\nindex bd8bb89a..db6d3fcd 100644\n--- a/include/xscom.h\n+++ b/include/xscom.h\n@@ -110,6 +110,9 @@\n \n /*\n * Additional useful definitions for P9\n+ *\n+ * Note: In all of these, the core numbering is the\n+ * *normal* (small) core number.\n */\n \n /*\n", "prefixes": [ "v6", "01/11" ] }