From patchwork Tue Aug 4 17:32:13 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340954 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLhls6MZPz9sTK for ; Wed, 5 Aug 2020 03:37:29 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLhls1HfpzDqNg for ; Wed, 5 Aug 2020 03:37:29 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhgY4jCCzDqY1 for ; Wed, 5 Aug 2020 03:33:45 +1000 (AEST) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074HXSvq025353; Tue, 4 Aug 2020 13:33:39 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com with ESMTP id 32q9gmn49t-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:33:39 -0400 Received: from m0098419.ppops.net (m0098419.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HXcq0026045; Tue, 4 Aug 2020 13:33:38 -0400 Received: from ppma05fra.de.ibm.com (6c.4a.5195.ip4.static.sl-reverse.com [149.81.74.108]) by mx0b-001b2d01.pphosted.com with ESMTP id 32q9gmn3tm-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:33:38 -0400 Received: from pps.filterd (ppma05fra.de.ibm.com [127.0.0.1]) by ppma05fra.de.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HPfqB027064; Tue, 4 Aug 2020 17:32:32 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma05fra.de.ibm.com with ESMTP id 32n017t5f1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:32 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HWUQi28180826 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:32:30 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 35B89A4060; Tue, 4 Aug 2020 17:32:30 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2012FA4065; Tue, 4 Aug 2020 17:32:29 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:28 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:13 +0530 Message-Id: <20200804173223.36280-2-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040126 Subject: [Skiboot] [PATCH v6 01/11] Add basic P9 fused core support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Ryan Grimm P9 cores can be configured into fused core mode where two core chiplets function as an 8-threaded, single core. So, bump four to eight in boot_entry when in fused core mode and cpu_thread_count in init_boot_cpu. The HID, AMOR, TSCR, RPR require the first active thread on that core chiplet to load the copy for that core chiplet. So, send thread 1 of a fused core to init_shared_sprs in boot_entry. The code checks for fused core mode in the core thead state register and puts a field in struct cpu_thread. This flag is checked when updating the HID and in XIVE code when setting the special bar. For XSCOM, the core ID is the non-fused EX. So, create macros to arrange the bits. It's fairly verbose but somewhat readable. This was tested on a P9 ZZ with 16 fused cores and ran HTX for over 24 hours. Signed-off-by: Ryan Grimm Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling Signed-off-by: Vaidyanathan Srinivasan --- asm/head.S | 25 ++++++++++++++++++++++--- core/chip.c | 19 +++++++++++++------ core/cpu.c | 31 ++++++++++++++++++++++++++----- hdata/test/hdata_to_dt.c | 9 ++++++++- hw/xive.c | 2 +- include/chip.h | 31 +++++++++++++++++++++++++++++++ include/cpu.h | 6 ++++++ include/xscom.h | 3 +++ 8 files changed, 110 insertions(+), 16 deletions(-) diff --git a/asm/head.S b/asm/head.S index 3b41815c..0b81bb51 100644 --- a/asm/head.S +++ b/asm/head.S @@ -324,6 +324,7 @@ boot_offset: * r28 : PVR * r27 : DTB pointer (or NULL) * r26 : PIR thread mask + * r25 : P9 fused core flag */ .global boot_entry boot_entry: @@ -338,13 +339,22 @@ boot_entry: cmpwi cr0,%r3,PVR_TYPE_P8NVL beq 2f cmpwi cr0,%r3,PVR_TYPE_P9 - beq 1f + beq 3f cmpwi cr0,%r3,PVR_TYPE_P9P - beq 1f + beq 3f attn /* Unsupported CPU type... what do we do ? */ b . /* loop here, just in case attn is disabled */ - /* P8 -> 8 threads */ + /* Check for fused core and set flag */ +3: + li %r3, 0x1e0 + mtspr SPR_SPRC, %r3 + mfspr %r3, SPR_SPRD + andi. %r25, %r3, 1 + beq 1f + + /* P8 or P9 fused -> 8 threads */ + 2: li %r26,7 /* Get our reloc offset into r30 */ @@ -370,6 +380,15 @@ boot_entry: #endif mtmsrd %r3,0 + /* If fused, t1 is primary chiplet and must init shared sprs */ + andi. %r3,%r25,1 + beq not_fused + + mfspr %r31,SPR_PIR + andi. %r3,%r31,1 + bnel init_shared_sprs + +not_fused: /* Check our PIR, avoid threads */ mfspr %r31,SPR_PIR and. %r0,%r31,%r26 diff --git a/core/chip.c b/core/chip.c index 191432d2..5c3276a4 100644 --- a/core/chip.c +++ b/core/chip.c @@ -6,6 +6,7 @@ #include #include #include +#include static struct proc_chip *chips[MAX_CHIPS]; enum proc_chip_quirks proc_chip_quirks; @@ -22,9 +23,12 @@ uint32_t pir_to_chip_id(uint32_t pir) uint32_t pir_to_core_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) - return P9_PIR2COREID(pir); - else if (proc_gen == proc_gen_p8) + if (proc_gen == proc_gen_p9) { + if (this_cpu()->is_fused_core) + return P9_PIRFUSED2NORMALCOREID(pir); + else + return P9_PIR2COREID(pir); + } else if (proc_gen == proc_gen_p8) return P8_PIR2COREID(pir); else assert(false); @@ -32,9 +36,12 @@ uint32_t pir_to_core_id(uint32_t pir) uint32_t pir_to_thread_id(uint32_t pir) { - if (proc_gen == proc_gen_p9) - return P9_PIR2THREADID(pir); - else if (proc_gen == proc_gen_p8) + if (proc_gen == proc_gen_p9) { + if (this_cpu()->is_fused_core) + return P9_PIR2FUSEDTHREADID(pir); + else + return P9_PIR2THREADID(pir); + } else if (proc_gen == proc_gen_p8) return P8_PIR2THREADID(pir); else assert(false); diff --git a/core/cpu.c b/core/cpu.c index 73777dd4..158f73e2 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -932,6 +932,7 @@ static void init_cpu_thread(struct cpu_thread *t, #ifdef STACK_CHECK_ENABLED t->stack_bot_mark = LONG_MAX; #endif + t->is_fused_core = is_fused_core(mfspr(SPR_PVR)); assert(pir == container_of(t, struct cpu_stack, cpu) - cpu_stacks); } @@ -1016,14 +1017,16 @@ void init_boot_cpu(void) " (max %d threads/core)\n", cpu_thread_count); break; case proc_gen_p9: - cpu_thread_count = 4; + if (is_fused_core(pvr)) + cpu_thread_count = 8; + else + cpu_thread_count = 4; prlog(PR_INFO, "CPU: P9 generation processor" " (max %d threads/core)\n", cpu_thread_count); break; default: prerror("CPU: Unknown PVR, assuming 1 thread\n"); cpu_thread_count = 1; - cpu_max_pir = mfspr(SPR_PIR); } if (is_power9n(pvr) && (PVR_VERS_MAJ(pvr) == 1)) { @@ -1151,7 +1154,7 @@ void init_all_cpus(void) /* Iterate all CPUs in the device-tree */ dt_for_each_child(cpus, cpu) { - unsigned int pir, server_no, chip_id; + unsigned int pir, server_no, chip_id, threads; enum cpu_thread_state state; const struct dt_property *p; struct cpu_thread *t, *pt; @@ -1181,6 +1184,14 @@ void init_all_cpus(void) prlog(PR_INFO, "CPU: CPU from DT PIR=0x%04x Server#=0x%x" " State=%d\n", pir, server_no, state); + /* Check max PIR */ + if (cpu_max_pir < (pir + cpu_thread_count - 1)) { + prlog(PR_WARNING, "CPU: CPU potentially out of range" + "PIR=0x%04x MAX=0x%04x !\n", + pir, cpu_max_pir); + continue; + } + /* Setup thread 0 */ assert(pir <= cpu_max_pir); t = pt = &cpu_stacks[pir].cpu; @@ -1206,11 +1217,21 @@ void init_all_cpus(void) /* Add the decrementer width property */ dt_add_property_cells(cpu, "ibm,dec-bits", dec_bits); + if (t->is_fused_core) + dt_add_property(t->node, "ibm,fused-core", NULL, 0); + /* Iterate threads */ p = dt_find_property(cpu, "ibm,ppc-interrupt-server#s"); if (!p) continue; - for (thread = 1; thread < (p->len / 4); thread++) { + threads = p->len / 4; + if (threads > cpu_thread_count) { + prlog(PR_WARNING, "CPU: Threads out of range for PIR 0x%04x" + " threads=%d max=%d\n", + pir, threads, cpu_thread_count); + threads = cpu_thread_count; + } + for (thread = 1; thread < threads; thread++) { prlog(PR_TRACE, "CPU: secondary thread %d found\n", thread); t = &cpu_stacks[pir + thread].cpu; @@ -1396,7 +1417,7 @@ static int64_t cpu_change_all_hid0(struct hid0_change_req *req) assert(jobs); for_each_available_cpu(cpu) { - if (!cpu_is_thread0(cpu)) + if (!cpu_is_thread0(cpu) && !cpu_is_core_chiplet_primary(cpu)) continue; if (cpu == this_cpu()) continue; diff --git a/hdata/test/hdata_to_dt.c b/hdata/test/hdata_to_dt.c index 49357cdf..90d83f93 100644 --- a/hdata/test/hdata_to_dt.c +++ b/hdata/test/hdata_to_dt.c @@ -38,7 +38,11 @@ struct spira_ntuple; static void *ntuple_addr(const struct spira_ntuple *n); /* Stuff which core expects. */ -#define __this_cpu ((struct cpu_thread *)NULL) +struct cpu_thread *my_fake_cpu; +static struct cpu_thread *this_cpu(void) +{ + return my_fake_cpu; +} unsigned long tb_hz = 512000000; @@ -74,6 +78,7 @@ unsigned long tb_hz = 512000000; struct cpu_thread { uint32_t pir; uint32_t chip_id; + bool is_fused_core; }; struct cpu_job *__cpu_queue_job(struct cpu_thread *cpu, const char *name, @@ -95,6 +100,8 @@ static inline struct cpu_job *cpu_queue_job(struct cpu_thread *cpu, struct cpu_thread __boot_cpu, *boot_cpu = &__boot_cpu; static unsigned long fake_pvr = PVR_P8; +unsigned int cpu_thread_count = 8; + static inline unsigned long mfspr(unsigned int spr) { assert(spr == SPR_PVR); diff --git a/hw/xive.c b/hw/xive.c index 8d6095c0..626ec182 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -3074,7 +3074,7 @@ static void xive_init_cpu(struct cpu_thread *c) * of a pair is present we just do the setup for each of them, which * is harmless. */ - if (cpu_is_thread0(c)) + if (cpu_is_thread0(c) || cpu_is_core_chiplet_primary(c)) xive_configure_ex_special_bar(x, c); /* Initialize the state structure */ diff --git a/include/chip.h b/include/chip.h index b79b63ec..38fafcf4 100644 --- a/include/chip.h +++ b/include/chip.h @@ -56,6 +56,26 @@ * thus we have a 6-bit core number. * * Note: XIVE Only supports 4-bit chip numbers ... + * + * Upper PIR Bits + * -------------- + * + * Normal-Core Mode: + * 57:61 CoreID + * 62:63 ThreadID + * + * Fused-Core Mode: + * 57:59 FusedQuadID + * 60 FusedCoreID + * 61:63 FusedThreadID + * + * FusedCoreID 0 contains normal-core chiplet 0 and 1 + * FusedCoreID 1 contains normal-core chiplet 2 and 3 + * + * Fused cores have interleaved threads: + * core chiplet 0/2 = t0, t2, t4, t6 + * core chiplet 1/3 = t1, t3, t5, t7 + * */ #define P9_PIR2GCID(pir) (((pir) >> 8) & 0x7f) @@ -67,6 +87,17 @@ #define P9_GCID2CHIPID(gcid) ((gcid) & 0x7) +#define P9_PIR2FUSEDQUADID(pir) (((pir) >> 4) & 0x7) + +#define P9_PIR2FUSEDCOREID(pir) (((pir) >> 3) & 0x1) + +#define P9_PIR2FUSEDTHREADID(pir) ((pir) & 0x7) + +#define P9_PIRFUSED2NORMALCOREID(pir) \ + (P9_PIR2FUSEDQUADID(pir) << 2) | \ + (P9_PIR2FUSEDCOREID(pir) << 1) | \ + (P9_PIR2FUSEDTHREADID(pir) & 1) + /* P9 specific ones mostly used by XIVE */ #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff) #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) diff --git a/include/cpu.h b/include/cpu.h index c90b961f..1863d6ad 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -42,6 +42,7 @@ struct cpu_thread { uint32_t server_no; uint32_t chip_id; bool is_secondary; + bool is_fused_core; struct cpu_thread *primary; enum cpu_thread_state state; struct dt_node *node; @@ -244,6 +245,11 @@ static inline bool cpu_is_thread0(struct cpu_thread *cpu) return cpu->primary == cpu; } +static inline bool cpu_is_core_chiplet_primary(struct cpu_thread *cpu) +{ + return cpu->is_fused_core & (cpu_get_thread_index(cpu) == 1); +} + static inline bool cpu_is_sibling(struct cpu_thread *cpu1, struct cpu_thread *cpu2) { diff --git a/include/xscom.h b/include/xscom.h index bd8bb89a..db6d3fcd 100644 --- a/include/xscom.h +++ b/include/xscom.h @@ -110,6 +110,9 @@ /* * Additional useful definitions for P9 + * + * Note: In all of these, the core numbering is the + * *normal* (small) core number. */ /* From patchwork Tue Aug 4 17:32:14 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340945 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLhj927CSz9sTC for ; Wed, 5 Aug 2020 03:35:09 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLhj85Hf6zDqQC for ; Wed, 5 Aug 2020 03:35:08 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhfJ3YFVzDqYq for ; Wed, 5 Aug 2020 03:32:40 +1000 (AEST) Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074H334S019761; Tue, 4 Aug 2020 13:32:37 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 32q86r0kwj-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:32:37 -0400 Received: from m0098394.ppops.net (m0098394.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HNUkc108123; Tue, 4 Aug 2020 13:32:36 -0400 Received: from ppma04fra.de.ibm.com (6a.4a.5195.ip4.static.sl-reverse.com [149.81.74.106]) by mx0a-001b2d01.pphosted.com with ESMTP id 32q86r0kvf-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:32:36 -0400 Received: from pps.filterd (ppma04fra.de.ibm.com [127.0.0.1]) by ppma04fra.de.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HPkEM032357; Tue, 4 Aug 2020 17:32:34 GMT Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by ppma04fra.de.ibm.com with ESMTP id 32n018a57f-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:33 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HWVQP29032928 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:32:31 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 93BB3A405B; Tue, 4 Aug 2020 17:32:31 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7E93DA405C; Tue, 4 Aug 2020 17:32:30 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:30 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:14 +0530 Message-Id: <20200804173223.36280-3-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 clxscore=1011 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040126 Subject: [Skiboot] [PATCH v6 02/11] xive: Set the fused core mode properly X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt Set or clear the fused core mode bit in the XIVE inits properly. While HostBoot is supposed to do it, I prefer not depending on it doing the right thing, since we already configure that register ourselves anyway. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling Signed-off-by: Vaidyanathan Srinivasan --- hw/xive.c | 4 ++++ include/xive-p9-regs.h | 1 + 2 files changed, 5 insertions(+) diff --git a/hw/xive.c b/hw/xive.c index 626ec182..9d09500e 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -1531,6 +1531,10 @@ static bool xive_config_init(struct xive *x) val |= PC_TCTXT_CFG_LGS_EN; /* Disable pressure relief as we hijack the field in the VPs */ val &= ~PC_TCTXT_CFG_STORE_ACK; + if (this_cpu()->is_fused_core) + val |= PC_TCTXT_CFG_FUSE_CORE_EN; + else + val &= ~PC_TCTXT_CFG_FUSE_CORE_EN; xive_regw(x, PC_TCTXT_CFG, val); xive_dbg(x, "PC_TCTXT_CFG=%016llx\n", val); diff --git a/include/xive-p9-regs.h b/include/xive-p9-regs.h index 7d18a6bf..fff341cc 100644 --- a/include/xive-p9-regs.h +++ b/include/xive-p9-regs.h @@ -80,6 +80,7 @@ #define PC_TCTXT_CFG_TARGET_EN PPC_BIT(1) #define PC_TCTXT_CFG_LGS_EN PPC_BIT(2) #define PC_TCTXT_CFG_STORE_ACK PPC_BIT(3) +#define PC_TCTXT_CFG_FUSE_CORE_EN PPC_BIT(4) #define PC_TCTXT_CFG_HARD_CHIPID_BLK PPC_BIT(8) #define PC_TCTXT_CHIPID_OVERRIDE PPC_BIT(9) #define PC_TCTXT_CHIPID PPC_BITMASK(12,15) From patchwork Tue Aug 4 17:32:15 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340948 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLhjv6VKCz9sTH for ; Wed, 5 Aug 2020 03:35:47 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLhjv46MJzDqYq for ; Wed, 5 Aug 2020 03:35:47 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0b-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhfM5SqhzDqZS for ; Wed, 5 Aug 2020 03:32:42 +1000 (AEST) Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074HWLKJ041489; Tue, 4 Aug 2020 13:32:37 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 32qbw58d53-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:32:37 -0400 Received: from m0098421.ppops.net (m0098421.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HWN6W041936; Tue, 4 Aug 2020 13:32:37 -0400 Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 32qbw58d4e-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:32:37 -0400 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HQYtv006302; Tue, 4 Aug 2020 17:32:35 GMT Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by ppma04ams.nl.ibm.com with ESMTP id 32n0183hwb-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:35 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HWXXW9109782 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:32:33 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F1F9CA4054; Tue, 4 Aug 2020 17:32:32 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DC84AA405F; Tue, 4 Aug 2020 17:32:31 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:31 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:15 +0530 Message-Id: <20200804173223.36280-4-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 mlxlogscore=939 impostorscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 malwarescore=0 phishscore=0 adultscore=0 spamscore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040126 Subject: [Skiboot] [PATCH v6 03/11] chip: Fix pir_to_thread_id for fused cores X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt pir_to_core_id() and pir_to_thread_id() are extensively used by the direct controls code and are expected to return the "normal" (non-fused, aka EC) core/thread IDs. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling Signed-off-by: Vaidyanathan Srinivasan --- core/chip.c | 2 +- include/chip.h | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/core/chip.c b/core/chip.c index 5c3276a4..c57694ab 100644 --- a/core/chip.c +++ b/core/chip.c @@ -38,7 +38,7 @@ uint32_t pir_to_thread_id(uint32_t pir) { if (proc_gen == proc_gen_p9) { if (this_cpu()->is_fused_core) - return P9_PIR2FUSEDTHREADID(pir); + return P9_PIRFUSED2NORMALTHREADID(pir); else return P9_PIR2THREADID(pir); } else if (proc_gen == proc_gen_p8) diff --git a/include/chip.h b/include/chip.h index 38fafcf4..2063cd29 100644 --- a/include/chip.h +++ b/include/chip.h @@ -98,6 +98,8 @@ (P9_PIR2FUSEDCOREID(pir) << 1) | \ (P9_PIR2FUSEDTHREADID(pir) & 1) +#define P9_PIRFUSED2NORMALTHREADID(pir) (((pir) >> 1) & 0x3) + /* P9 specific ones mostly used by XIVE */ #define P9_PIR2LOCALCPU(pir) ((pir) & 0xff) #define P9_PIRFROMLOCALCPU(chip, cpu) (((chip) << 8) | (cpu)) @@ -229,6 +231,11 @@ struct proc_chip { }; extern uint32_t pir_to_chip_id(uint32_t pir); + +/* + * Note: In P9 fused-core mode, these will return the "normal" + * core ID and thread ID (ie, thread ID 0..3) + */ extern uint32_t pir_to_core_id(uint32_t pir); extern uint32_t pir_to_thread_id(uint32_t pir); From patchwork Tue Aug 4 17:32:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340947 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLhjW6pVlz9sRR for ; Wed, 5 Aug 2020 03:35:27 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLhjW587LzDqcL for ; Wed, 5 Aug 2020 03:35:27 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhfL47RzzDqZS for ; Wed, 5 Aug 2020 03:32:42 +1000 (AEST) Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074H324N019684; Tue, 4 Aug 2020 13:32:39 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 32q86r0kxd-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:32:39 -0400 Received: from m0098394.ppops.net (m0098394.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HPggh118901; Tue, 4 Aug 2020 13:32:38 -0400 Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 32q86r0kwp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:32:38 -0400 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HQGOS028945; Tue, 4 Aug 2020 17:32:36 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma03ams.nl.ibm.com with ESMTP id 32n0183hks-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:36 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HWYUq27459864 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:32:34 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5C263A405C; Tue, 4 Aug 2020 17:32:34 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 4722AA405B; Tue, 4 Aug 2020 17:32:33 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:33 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:16 +0530 Message-Id: <20200804173223.36280-5-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040126 Subject: [Skiboot] [PATCH v6 04/11] cpu: Keep track of the "ec_primary" in big core more X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt The "EC" primary is the primary thread of an EC, ie, the corresponding small core "half" of the big core where the thread resides. It will be necessary for the direct controls to target the right half when doing special wakeups among others. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling Signed-off-by: Vaidyanathan Srinivasan --- core/cpu.c | 20 ++++++++++++++------ include/cpu.h | 1 + 2 files changed, 15 insertions(+), 6 deletions(-) diff --git a/core/cpu.c b/core/cpu.c index 158f73e2..9d2cd56e 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -823,9 +823,11 @@ struct cpu_thread *first_ungarded_cpu(void) struct cpu_thread *next_ungarded_primary(struct cpu_thread *cpu) { + bool is_primary; do { cpu = next_cpu(cpu); - } while(cpu && (cpu->state == cpu_state_unavailable || cpu->primary != cpu)); + is_primary = cpu == cpu->primary || cpu == cpu->ec_primary; + } while(cpu && (cpu->state == cpu_state_unavailable || !is_primary)); return cpu; } @@ -1157,7 +1159,7 @@ void init_all_cpus(void) unsigned int pir, server_no, chip_id, threads; enum cpu_thread_state state; const struct dt_property *p; - struct cpu_thread *t, *pt; + struct cpu_thread *t, *pt0, *pt1; /* Skip cache nodes */ if (strcmp(dt_prop_get(cpu, "device_type"), "cpu")) @@ -1194,14 +1196,18 @@ void init_all_cpus(void) /* Setup thread 0 */ assert(pir <= cpu_max_pir); - t = pt = &cpu_stacks[pir].cpu; + t = pt0 = &cpu_stacks[pir].cpu; if (t != boot_cpu) { init_cpu_thread(t, state, pir); /* Each cpu gets its own later in init_trace_buffers */ t->trace = boot_cpu->trace; } + if (t->is_fused_core) + pt1 = &cpu_stacks[pir + 1].cpu; + else + pt1 = pt0; t->server_no = server_no; - t->primary = t; + t->primary = t->ec_primary = t; t->node = cpu; t->chip_id = chip_id; t->icp_regs = NULL; /* Will be set later */ @@ -1239,10 +1245,12 @@ void init_all_cpus(void) t->trace = boot_cpu->trace; t->server_no = dt_property_get_cell(p, thread); t->is_secondary = true; - t->primary = pt; + t->is_fused_core = pt0->is_fused_core; + t->primary = pt0; + t->ec_primary = (thread & 1) ? pt1 : pt0; t->node = cpu; t->chip_id = chip_id; - t->core_hmi_state_ptr = &pt->core_hmi_state; + t->core_hmi_state_ptr = &pt0->core_hmi_state; } prlog(PR_INFO, "CPU: %d secondary threads\n", thread); } diff --git a/include/cpu.h b/include/cpu.h index 1863d6ad..22f83440 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -44,6 +44,7 @@ struct cpu_thread { bool is_secondary; bool is_fused_core; struct cpu_thread *primary; + struct cpu_thread *ec_primary; enum cpu_thread_state state; struct dt_node *node; struct trace_info *trace; From patchwork Tue Aug 4 17:32:17 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340955 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLhmH74QYz9sRR for ; Wed, 5 Aug 2020 03:37:51 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLhmH58spzDqZN for ; Wed, 5 Aug 2020 03:37:51 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0b-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhgd4MNhzDqXv for ; Wed, 5 Aug 2020 03:33:49 +1000 (AEST) Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074HXZN8145169; Tue, 4 Aug 2020 13:33:45 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 32qbvq8h13-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:33:44 -0400 Received: from m0098417.ppops.net (m0098417.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HXgAW145968; Tue, 4 Aug 2020 13:33:42 -0400 Received: from ppma03fra.de.ibm.com (6b.4a.5195.ip4.static.sl-reverse.com [149.81.74.107]) by mx0a-001b2d01.pphosted.com with ESMTP id 32qbvq8gb7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:33:42 -0400 Received: from pps.filterd (ppma03fra.de.ibm.com [127.0.0.1]) by ppma03fra.de.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HLQV1018156; Tue, 4 Aug 2020 17:32:38 GMT Received: from b06avi18878370.portsmouth.uk.ibm.com (b06avi18878370.portsmouth.uk.ibm.com [9.149.26.194]) by ppma03fra.de.ibm.com with ESMTP id 32nyyd1cax-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:37 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06avi18878370.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HWZuB61931806 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:32:35 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id BA9CAA4054; Tue, 4 Aug 2020 17:32:35 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A54E8A405C; Tue, 4 Aug 2020 17:32:34 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:34 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:17 +0530 Message-Id: <20200804173223.36280-6-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 phishscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 mlxlogscore=999 spamscore=0 impostorscore=0 adultscore=0 mlxscore=0 clxscore=1015 priorityscore=1501 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040130 Subject: [Skiboot] [PATCH v6 05/11] direct-ctl: Use the EC primary for special wakeups X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling Signed-off-by: Vaidyanathan Srinivasan --- core/direct-controls.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/core/direct-controls.c b/core/direct-controls.c index 793ef29c..65cf122c 100644 --- a/core/direct-controls.c +++ b/core/direct-controls.c @@ -519,7 +519,7 @@ static int p9_sreset_thread(struct cpu_thread *cpu) int dctl_set_special_wakeup(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc = OPAL_SUCCESS; if (proc_gen == proc_gen_unknown) @@ -541,7 +541,7 @@ int dctl_set_special_wakeup(struct cpu_thread *t) int dctl_clear_special_wakeup(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc = OPAL_SUCCESS; if (proc_gen == proc_gen_unknown) @@ -589,7 +589,7 @@ int dctl_core_is_gated(struct cpu_thread *t) static int dctl_stop(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc; lock(&c->dctl_lock); @@ -637,7 +637,7 @@ static int dctl_cont(struct cpu_thread *t) */ static int dctl_sreset(struct cpu_thread *t) { - struct cpu_thread *c = t->primary; + struct cpu_thread *c = t->ec_primary; int rc; lock(&c->dctl_lock); From patchwork Tue Aug 4 17:32:18 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340953 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLhlW0Yn4z9sTC for ; Wed, 5 Aug 2020 03:37:11 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLhlV6kbSzDqgq for ; Wed, 5 Aug 2020 03:37:10 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhgX34LhzDqbC for ; Wed, 5 Aug 2020 03:33:44 +1000 (AEST) Received: from pps.filterd (m0098416.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074HXR4f172570; Tue, 4 Aug 2020 13:33:40 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com with ESMTP id 32qby70aj8-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:33:40 -0400 Received: from m0098416.ppops.net (m0098416.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HXeqW173863; Tue, 4 Aug 2020 13:33:40 -0400 Received: from ppma02fra.de.ibm.com (47.49.7a9f.ip4.static.sl-reverse.com [159.122.73.71]) by mx0b-001b2d01.pphosted.com with ESMTP id 32qby70a3u-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:33:39 -0400 Received: from pps.filterd (ppma02fra.de.ibm.com [127.0.0.1]) by ppma02fra.de.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HVwDq009046; Tue, 4 Aug 2020 17:32:39 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma02fra.de.ibm.com with ESMTP id 32n018a5m1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:39 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HWbDV14287122 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:32:37 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 48BBFA405C; Tue, 4 Aug 2020 17:32:37 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0F739A4054; Tue, 4 Aug 2020 17:32:36 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:35 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:18 +0530 Message-Id: <20200804173223.36280-7-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 adultscore=0 clxscore=1015 mlxscore=0 phishscore=0 malwarescore=0 bulkscore=0 mlxlogscore=999 lowpriorityscore=0 suspectscore=0 impostorscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040126 Subject: [Skiboot] [PATCH v6 06/11] slw: Limit fused cores P9 to STOP0/1/2 X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling , Vaidyanathan Srinivasan Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt FROM: Benjamin Herrenschmidt Linux doesn't know how to properly restore state on "both halves" of a fused core, so limit ourselves to STOP states that don't require HV state restore for bare metal kernels (KVM is still broken) until we add a new representation for STOP states. The new representation will have per-state versioning so that we can control their individual enablement based on whether the OS has the necessary workarounds to make them work. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling Signed-off-by: Vaidyanathan Srinivasan --- hw/slw.c | 82 +++++++++++++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 81 insertions(+), 1 deletion(-) diff --git a/hw/slw.c b/hw/slw.c index beb129a8..625ee886 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -688,6 +688,83 @@ static struct cpu_idle_states power9_mambo_cpu_idle_states[] = { }; +/* + * cpu_idle_states for fused core configuration + * These will be a subset of power9 idle states. + */ +static struct cpu_idle_states power9_fusedcore_cpu_idle_states[] = { + { + .name = "stop0_lite", /* Enter stop0 with no state loss */ + .latency_ns = 1000, + .residency_ns = 10000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 0*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3), + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + { + .name = "stop0", + .latency_ns = 2000, + .residency_ns = 20000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(0) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + + /* stop1_lite has been removed since it adds no additional benefit over stop0_lite */ + + { + .name = "stop1", + .latency_ns = 5000, + .residency_ns = 50000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(1) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, + /* + * stop2_lite has been removed since currently it adds minimal benefit over stop2. + * However, the benefit is eclipsed by the time required to ungate the clocks + */ + + { + .name = "stop2", + .latency_ns = 10000, + .residency_ns = 100000, + .flags = 0*OPAL_PM_DEC_STOP \ + | 0*OPAL_PM_TIMEBASE_STOP \ + | 1*OPAL_PM_LOSE_USER_CONTEXT \ + | 0*OPAL_PM_LOSE_HYP_CONTEXT \ + | 0*OPAL_PM_LOSE_FULL_CONTEXT \ + | 1*OPAL_PM_STOP_INST_FAST, + .pm_ctrl_reg_val = OPAL_PM_PSSCR_RL(2) \ + | OPAL_PM_PSSCR_MTL(3) \ + | OPAL_PM_PSSCR_TR(3) \ + | OPAL_PM_PSSCR_ESL \ + | OPAL_PM_PSSCR_EC, + .pm_ctrl_reg_mask = OPAL_PM_PSSCR_MASK }, +}; + static void slw_late_init_p9(struct proc_chip *chip) { struct cpu_thread *c; @@ -772,7 +849,10 @@ void add_cpu_idle_state_properties(void) if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) { states = power9_mambo_cpu_idle_states; nr_states = ARRAY_SIZE(power9_mambo_cpu_idle_states); - } else { + } else if (this_cpu()->is_fused_core) { + states = power9_fusedcore_cpu_idle_states; + nr_states = ARRAY_SIZE(power9_fusedcore_cpu_idle_states); + } else { states = power9_cpu_idle_states; nr_states = ARRAY_SIZE(power9_cpu_idle_states); } From patchwork Tue Aug 4 17:32:19 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340949 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLhkF1nzYz9sRR for ; Wed, 5 Aug 2020 03:36:05 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLhkD6ZjlzDqcD for ; Wed, 5 Aug 2020 03:36:04 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhfQ3mzSzDqYq for ; Wed, 5 Aug 2020 03:32:46 +1000 (AEST) Received: from pps.filterd (m0098394.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074H320F019678; Tue, 4 Aug 2020 13:32:44 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 32q86r0m0b-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:32:44 -0400 Received: from m0098394.ppops.net (m0098394.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074H37M5020254; Tue, 4 Aug 2020 13:32:43 -0400 Received: from ppma04ams.nl.ibm.com (63.31.33a9.ip4.static.sl-reverse.com [169.51.49.99]) by mx0a-001b2d01.pphosted.com with ESMTP id 32q86r0kyk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:32:43 -0400 Received: from pps.filterd (ppma04ams.nl.ibm.com [127.0.0.1]) by ppma04ams.nl.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HQTuX006296; Tue, 4 Aug 2020 17:32:41 GMT Received: from b06cxnps4074.portsmouth.uk.ibm.com (d06relay11.portsmouth.uk.ibm.com [9.149.109.196]) by ppma04ams.nl.ibm.com with ESMTP id 32n0183hwe-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:40 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HWc7M31195480 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:32:38 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id A6E3AA405B; Tue, 4 Aug 2020 17:32:38 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 925A1A4054; Tue, 4 Aug 2020 17:32:37 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:37 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:19 +0530 Message-Id: <20200804173223.36280-8-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 malwarescore=0 mlxlogscore=999 phishscore=0 clxscore=1015 lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040126 Subject: [Skiboot] [PATCH v6 07/11] cpu: Make cpu_get_core_index() return the fused core number X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt cpu_get_core_index() currently uses pir_to_core_id() which returns an EC number always (ie, a normal core number) even in fused core mode. This is inconsistent with cpu_get_thread_index() which returns a thread within a fused core (0...7) on P9. So let's make things consistent and document it. Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling Signed-off-by: Vaidyanathan Srinivasan --- core/chip.c | 13 +++++++++++++ core/cpu.c | 2 +- include/chip.h | 5 +++++ include/cpu.h | 6 ++++++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/core/chip.c b/core/chip.c index c57694ab..f1269d3f 100644 --- a/core/chip.c +++ b/core/chip.c @@ -34,6 +34,19 @@ uint32_t pir_to_core_id(uint32_t pir) assert(false); } +uint32_t pir_to_fused_core_id(uint32_t pir) +{ + if (proc_gen == proc_gen_p9) { + if (this_cpu()->is_fused_core) + return P9_PIR2FUSEDCOREID(pir); + else + return P9_PIR2COREID(pir); + } else if (proc_gen == proc_gen_p8) + return P8_PIR2COREID(pir); + else + assert(false); +} + uint32_t pir_to_thread_id(uint32_t pir) { if (proc_gen == proc_gen_p9) { diff --git a/core/cpu.c b/core/cpu.c index 9d2cd56e..ff0442a8 100644 --- a/core/cpu.c +++ b/core/cpu.c @@ -866,7 +866,7 @@ struct cpu_thread *first_available_core_in_chip(u32 chip_id) uint32_t cpu_get_core_index(struct cpu_thread *cpu) { - return pir_to_core_id(cpu->pir); + return pir_to_fused_core_id(cpu->pir); } void cpu_remove_node(const struct cpu_thread *t) diff --git a/include/chip.h b/include/chip.h index 2063cd29..4deb9618 100644 --- a/include/chip.h +++ b/include/chip.h @@ -239,6 +239,11 @@ extern uint32_t pir_to_chip_id(uint32_t pir); extern uint32_t pir_to_core_id(uint32_t pir); extern uint32_t pir_to_thread_id(uint32_t pir); +/* In P9 fused core mode, this is the "fused" core ID, in + * normal core mode or P8, this is the same as pir_to_core_id + */ +extern uint32_t pir_to_fused_core_id(uint32_t pir); + extern struct proc_chip *next_chip(struct proc_chip *chip); #define for_each_chip(__c) for (__c=next_chip(NULL); __c; __c=next_chip(__c)) diff --git a/include/cpu.h b/include/cpu.h index 22f83440..b0c78ce6 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -226,6 +226,12 @@ static inline __nomcount struct cpu_thread *this_cpu(void) return __this_cpu; } +/* + * Note: On POWER9 fused core, cpu_get_thread_index() and cpu_get_core_index() + * return respectively the thread number within a fused core (0..7) and + * the fused core number. If you want the EC (small core) number, you have + * to use the low level pir_to_core_id() and pir_to_thread_id(). + */ /* Get the thread # of a cpu within the core */ static inline uint32_t cpu_get_thread_index(struct cpu_thread *cpu) { From patchwork Tue Aug 4 17:32:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLjQL56vyz9sRR for ; Wed, 5 Aug 2020 04:07:22 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLjQL3bZYzDqXG for ; Wed, 5 Aug 2020 04:07:22 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLjQF4DBszDqQL for ; Wed, 5 Aug 2020 04:07:17 +1000 (AEST) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074I2H3e118440; Tue, 4 Aug 2020 14:07:13 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com with ESMTP id 32q9gmp1py-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 14:07:13 -0400 Received: from m0098419.ppops.net (m0098419.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074I3gN1124026; Tue, 4 Aug 2020 14:07:12 -0400 Received: from ppma05fra.de.ibm.com (6c.4a.5195.ip4.static.sl-reverse.com [149.81.74.108]) by mx0b-001b2d01.pphosted.com with ESMTP id 32q9gmp1p6-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 14:07:12 -0400 Received: from pps.filterd (ppma05fra.de.ibm.com [127.0.0.1]) by ppma05fra.de.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HQDUA028099; Tue, 4 Aug 2020 17:32:42 GMT Received: from b06cxnps4075.portsmouth.uk.ibm.com (d06relay12.portsmouth.uk.ibm.com [9.149.109.197]) by ppma05fra.de.ibm.com with ESMTP id 32n017t5f2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:42 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HWe3R26083806 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:32:40 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 1271FA405B; Tue, 4 Aug 2020 17:32:40 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id F0A9CA4054; Tue, 4 Aug 2020 17:32:38 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:38 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:20 +0530 Message-Id: <20200804173223.36280-9-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 adultscore=0 bulkscore=0 lowpriorityscore=0 malwarescore=0 impostorscore=0 phishscore=0 mlxscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040130 Subject: [Skiboot] [PATCH v6 08/11] imc: Use pir_to_core_id() rather than cpu_get_core_index() X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Benjamin Herrenschmidt The IMC HW targets HW ECs, not fused cores on P9 Signed-off-by: Benjamin Herrenschmidt Signed-off-by: Michael Neuling Signed-off-by: Vaidyanathan Srinivasan --- hw/imc.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/hw/imc.c b/hw/imc.c index 927fba0b..63488b9b 100644 --- a/hw/imc.c +++ b/hw/imc.c @@ -685,7 +685,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu * pdbar in specific scom ports. port_id are in * pdbar_scom_index[] and htm_scom_index[]. */ - phys_core_id = cpu_get_core_index(c); + phys_core_id = pir_to_core_id(c->pir); port_id = phys_core_id % 4; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) @@ -762,7 +762,7 @@ static int64_t opal_imc_counters_init(uint32_t type, uint64_t addr, uint64_t cpu if (!c) return OPAL_PARAMETER; - phys_core_id = cpu_get_core_index(c); + phys_core_id = pir_to_core_id(c->pir); port_id = phys_core_id % 4; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) @@ -840,7 +840,7 @@ static int64_t opal_imc_counters_start(uint32_t type, uint64_t cpu_pir) * Core IMC hardware mandates setting of htm_mode in specific * scom ports (port_id are in htm_scom_index[]) */ - phys_core_id = cpu_get_core_index(c); + phys_core_id = pir_to_core_id(c->pir); port_id = phys_core_id % 4; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) @@ -902,7 +902,7 @@ static int64_t opal_imc_counters_stop(uint32_t type, uint64_t cpu_pir) * Core IMC hardware mandates setting of htm_mode in specific * scom ports (port_id are in htm_scom_index[]) */ - phys_core_id = cpu_get_core_index(c); + phys_core_id = pir_to_core_id(c->pir); port_id = phys_core_id % 4; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) From patchwork Tue Aug 4 17:32:21 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340950 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLhkY0pXKz9sRR for ; Wed, 5 Aug 2020 03:36:21 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLhkX6pMCzDqdP for ; Wed, 5 Aug 2020 03:36:20 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhfq2b3HzDqXP for ; Wed, 5 Aug 2020 03:33:07 +1000 (AEST) Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074HWxrT045788; Tue, 4 Aug 2020 13:33:04 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 32q87n83vu-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:33:03 -0400 Received: from m0098410.ppops.net (m0098410.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HX2bK045972; Tue, 4 Aug 2020 13:33:02 -0400 Received: from ppma06ams.nl.ibm.com (66.31.33a9.ip4.static.sl-reverse.com [169.51.49.102]) by mx0a-001b2d01.pphosted.com with ESMTP id 32q87n83ne-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:33:02 -0400 Received: from pps.filterd (ppma06ams.nl.ibm.com [127.0.0.1]) by ppma06ams.nl.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HQoMY006440; Tue, 4 Aug 2020 17:32:44 GMT Received: from b06cxnps4076.portsmouth.uk.ibm.com (d06relay13.portsmouth.uk.ibm.com [9.149.109.198]) by ppma06ams.nl.ibm.com with ESMTP id 32mynh3hvn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:43 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HWfl122348222 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:32:41 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 961B6A4064; Tue, 4 Aug 2020 17:32:41 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 5BB59A4054; Tue, 4 Aug 2020 17:32:40 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:40 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:21 +0530 Message-Id: <20200804173223.36280-10-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 mlxlogscore=999 spamscore=0 lowpriorityscore=0 bulkscore=0 suspectscore=0 clxscore=1015 malwarescore=0 impostorscore=0 priorityscore=1501 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040130 Subject: [Skiboot] [PATCH v6 09/11] Add POWER9 Cumulus processor PVR type X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling , Vaidyanathan Srinivasan Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Vaidyanathan Srinivasan Add PVR checks and feature mapping for POWER9 Cumulus chip. Signed-off-by: Vaidyanathan Srinivasan Signed-off-by: Vasant Hegde --- core/cpufeatures.c | 19 +++++++++++++++++++ include/processor.h | 15 +++++++++++++++ 2 files changed, 34 insertions(+) diff --git a/core/cpufeatures.c b/core/cpufeatures.c index f31850ab..2e33d8ad 100644 --- a/core/cpufeatures.c +++ b/core/cpufeatures.c @@ -942,6 +942,25 @@ void dt_add_cpufeatures(struct dt_node *root) default: assert(0); } + } else if (is_power9c(version) && + (PVR_VERS_MAJ(version) == 1)) { + /* P9C DD1.x */ + switch (PVR_VERS_MIN(version)) { + case 1: + /* Cumulus DD1.1 => Nimbus DD2.1 */ + cpu_feature_cpu = CPU_P9_DD2_0_1; + break; + case 2: + /* Cumulus DD1.2 */ + cpu_feature_cpu = CPU_P9_DD2_2; + break; + case 3: + /* Cumulus DD1.3 */ + cpu_feature_cpu = CPU_P9_DD2_3; + break; + default: + assert(0); + } } else { assert(0); } diff --git a/include/processor.h b/include/processor.h index ddec6c04..70e749f1 100644 --- a/include/processor.h +++ b/include/processor.h @@ -248,6 +248,21 @@ static inline bool is_fused_core(uint32_t version) } } +static inline bool is_power9c(uint32_t version) +{ + + if (PVR_TYPE(version) != PVR_TYPE_P9) + return false; + /* + * Bit 13 tells us: + * 0 = Scale out (aka Nimbus) + * 1 = Scale up (aka Cumulus) + */ + if (!((version >> 13) & 1)) + return false; + return true; +} + #ifndef __TEST__ /* POWER9 and above only */ From patchwork Tue Aug 4 17:32:22 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340951 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLhkt3CZBz9sRR for ; Wed, 5 Aug 2020 03:36:38 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLhkt262yzDqfb for ; Wed, 5 Aug 2020 03:36:38 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhgK3wbLzDqZk for ; Wed, 5 Aug 2020 03:33:33 +1000 (AEST) Received: from pps.filterd (m0098414.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074HXOjm100391; Tue, 4 Aug 2020 13:33:30 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0b-001b2d01.pphosted.com with ESMTP id 32qbmw8th7-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:33:30 -0400 Received: from m0098414.ppops.net (m0098414.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HXTQU100850; Tue, 4 Aug 2020 13:33:29 -0400 Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0b-001b2d01.pphosted.com with ESMTP id 32qbmw8tdp-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:33:28 -0400 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HQhH6029011; Tue, 4 Aug 2020 17:32:45 GMT Received: from b06avi18626390.portsmouth.uk.ibm.com (b06avi18626390.portsmouth.uk.ibm.com [9.149.26.192]) by ppma03ams.nl.ibm.com with ESMTP id 32n0183hky-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:45 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HVGvw54722976 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:31:17 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2E857A405C; Tue, 4 Aug 2020 17:32:43 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id DF404A4062; Tue, 4 Aug 2020 17:32:41 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:41 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:22 +0530 Message-Id: <20200804173223.36280-11-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 mlxlogscore=999 lowpriorityscore=0 mlxscore=0 priorityscore=1501 clxscore=1015 spamscore=0 bulkscore=0 malwarescore=0 impostorscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040126 Subject: [Skiboot] [PATCH v6 10/11] Add POWER9 Fleetwood platform support X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling , Vaidyanathan Srinivasan Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Vaidyanathan Srinivasan The system is larger than ZZ and uses P9 Cumulus chip. However the interactions with host is via FSP and FSP mailbox which are identical to a ZZ platform. Add the DT string and detect as ZZ to avoid creating a nearly identical FSP based platform. Signed-off-by: Vaidyanathan Srinivasan Signed-off-by: Vasant Hegde --- platforms/ibm-fsp/zz.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/platforms/ibm-fsp/zz.c b/platforms/ibm-fsp/zz.c index 1513b628..7c6050ab 100644 --- a/platforms/ibm-fsp/zz.c +++ b/platforms/ibm-fsp/zz.c @@ -156,6 +156,10 @@ static bool zz_probe(void) return true; } + /* Add Fleetwood FSP platform and map it to ZZ */ + if (dt_node_is_compatible(dt_root, "ibm,fleetwood-m9s")) { + return true; + } return false; } From patchwork Tue Aug 4 17:32:23 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vaidyanathan Srinivasan X-Patchwork-Id: 1340956 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4BLhmh6Y65z9sR4 for ; Wed, 5 Aug 2020 03:38:12 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 4BLhmh3G01zDqcc for ; Wed, 5 Aug 2020 03:38:12 +1000 (AEST) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0b-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=pass (p=none dis=none) header.from=linux.ibm.com Received: from mx0b-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhhp2L6DzDqS1 for ; Wed, 5 Aug 2020 03:34:50 +1000 (AEST) Received: from pps.filterd (m0127361.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id 074HYetX050160; Tue, 4 Aug 2020 13:34:46 -0400 Received: from pps.reinject (localhost [127.0.0.1]) by mx0a-001b2d01.pphosted.com with ESMTP id 32q8ygnvf0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:34:44 -0400 Received: from m0127361.ppops.net (m0127361.ppops.net [127.0.0.1]) by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HYfae050186; Tue, 4 Aug 2020 13:34:41 -0400 Received: from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com [169.51.49.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 32q8ygnug1-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 13:34:40 -0400 Received: from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1]) by ppma03ams.nl.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HQhH7029011; Tue, 4 Aug 2020 17:32:46 GMT Received: from b06cxnps3075.portsmouth.uk.ibm.com (d06relay10.portsmouth.uk.ibm.com [9.149.109.195]) by ppma03ams.nl.ibm.com with ESMTP id 32n0183hm0-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 04 Aug 2020 17:32:46 +0000 Received: from b06wcsmtp001.portsmouth.uk.ibm.com (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id 074HWiOH31326690 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Aug 2020 17:32:44 GMT Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 70C11A405C; Tue, 4 Aug 2020 17:32:44 +0000 (GMT) Received: from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 76B3AA405B; Tue, 4 Aug 2020 17:32:43 +0000 (GMT) Received: from drishya.in.ibm.com (unknown [9.102.1.52]) by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP; Tue, 4 Aug 2020 17:32:43 +0000 (GMT) From: Vaidyanathan Srinivasan To: "Oliver O'Halloran" Date: Tue, 4 Aug 2020 23:02:23 +0530 Message-Id: <20200804173223.36280-12-svaidy@linux.ibm.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200804173223.36280-1-svaidy@linux.ibm.com> References: <20200804173223.36280-1-svaidy@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687 definitions=2020-08-04_04:2020-08-03, 2020-08-04 signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxlogscore=999 impostorscore=0 adultscore=0 phishscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 malwarescore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2006250000 definitions=main-2008040130 Subject: [Skiboot] [PATCH v6 11/11] Enable fused core mode support in OPAL X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Michael Neuling Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Previous commit 482f18adf21eeb5f6ce2a93334725509a8f6f0cd added check for fused core mode and bailed out. The check can be removed since fused core mode is now supported in OPAL. Signed-off-by: Vaidyanathan Srinivasan --- core/init.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/core/init.c b/core/init.c index d82eebee..1289805f 100644 --- a/core/init.c +++ b/core/init.c @@ -1284,10 +1284,6 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) /* Install the OPAL Console handlers */ init_opal_console(); - if(is_fused_core(mfspr(SPR_PVR))) { - prerror("CPU: Detected unsupported fused core mode\n"); - abort(); - } /* * Some platforms set a flag to wait for SBE validation to be * performed by the BMC. If this occurs it leaves the SBE in a