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GET /api/patches/1340947/?format=api
{ "id": 1340947, "url": "http://patchwork.ozlabs.org/api/patches/1340947/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/20200804173223.36280-5-svaidy@linux.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200804173223.36280-5-svaidy@linux.ibm.com>", "list_archive_url": null, "date": "2020-08-04T17:32:16", "name": "[v6,04/11] cpu: Keep track of the \"ec_primary\" in big core more", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "5c706f6f334e0dd282315ffe598778d426fe951f", "submitter": { "id": 76774, "url": "http://patchwork.ozlabs.org/api/people/76774/?format=api", "name": "Vaidyanathan Srinivasan", "email": "svaidy@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/20200804173223.36280-5-svaidy@linux.ibm.com/mbox/", "series": [ { "id": 194127, "url": "http://patchwork.ozlabs.org/api/series/194127/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/list/?series=194127", "date": "2020-08-04T17:32:14", "name": "Initial fused-core support for POWER9", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/194127/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1340947/comments/", "check": "success", "checks": "http://patchwork.ozlabs.org/api/patches/1340947/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4BLhjW6pVlz9sRR\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 5 Aug 2020 03:35:27 +1000 (AEST)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4BLhjW587LzDqcL\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 5 Aug 2020 03:35:27 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n [148.163.156.1])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhfL47RzzDqZS\n for <skiboot@lists.ozlabs.org>; Wed, 5 Aug 2020 03:32:42 +1000 (AEST)", "from pps.filterd (m0098394.ppops.net [127.0.0.1])\n by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 074H324N019684; Tue, 4 Aug 2020 13:32:39 -0400", "from pps.reinject (localhost [127.0.0.1])\n by mx0a-001b2d01.pphosted.com with ESMTP id 32q86r0kxd-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 04 Aug 2020 13:32:39 -0400", "from m0098394.ppops.net (m0098394.ppops.net [127.0.0.1])\n by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HPggh118901;\n Tue, 4 Aug 2020 13:32:38 -0400", "from ppma03ams.nl.ibm.com (62.31.33a9.ip4.static.sl-reverse.com\n [169.51.49.98])\n by mx0a-001b2d01.pphosted.com with ESMTP id 32q86r0kwp-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 04 Aug 2020 13:32:38 -0400", "from pps.filterd (ppma03ams.nl.ibm.com [127.0.0.1])\n by ppma03ams.nl.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HQGOS028945;\n Tue, 4 Aug 2020 17:32:36 GMT", "from b06cxnps4076.portsmouth.uk.ibm.com\n (d06relay13.portsmouth.uk.ibm.com [9.149.109.198])\n by ppma03ams.nl.ibm.com with ESMTP id 32n0183hks-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 04 Aug 2020 17:32:36 +0000", "from b06wcsmtp001.portsmouth.uk.ibm.com\n (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160])\n by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n 074HWYUq27459864\n (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Tue, 4 Aug 2020 17:32:34 GMT", "from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 5C263A405C;\n Tue, 4 Aug 2020 17:32:34 +0000 (GMT)", "from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 4722AA405B;\n Tue, 4 Aug 2020 17:32:33 +0000 (GMT)", "from drishya.in.ibm.com (unknown [9.102.1.52])\n by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n Tue, 4 Aug 2020 17:32:33 +0000 (GMT)" ], "Authentication-Results": [ "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=linux.ibm.com", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1;\n helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com;\n receiver=<UNKNOWN>)", "lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=linux.ibm.com" ], "From": "Vaidyanathan Srinivasan <svaidy@linux.ibm.com>", "To": "\"Oliver O'Halloran\" <oohall@gmail.com>", "Date": "Tue, 4 Aug 2020 23:02:16 +0530", "Message-Id": "<20200804173223.36280-5-svaidy@linux.ibm.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20200804173223.36280-1-svaidy@linux.ibm.com>", "References": "<20200804173223.36280-1-svaidy@linux.ibm.com>", "MIME-Version": "1.0", "X-TM-AS-GCONF": "00", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-08-04_04:2020-08-03,\n 2020-08-04 signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 impostorscore=0\n malwarescore=0 mlxlogscore=999 phishscore=0 clxscore=1015\n lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0\n mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2006250000 definitions=main-2008040126", "Subject": "[Skiboot] [PATCH v6 04/11] cpu: Keep track of the \"ec_primary\" in\n big core more", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n <mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n <mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Cc": "skiboot@lists.ozlabs.org, Michael Neuling <mikey@neuling.org>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n <skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "From: Benjamin Herrenschmidt <benh@kernel.crashing.org>\n\nThe \"EC\" primary is the primary thread of an EC, ie, the corresponding\nsmall core \"half\" of the big core where the thread resides.\n\nIt will be necessary for the direct controls to target the right\nhalf when doing special wakeups among others.\n\nSigned-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>\nSigned-off-by: Michael Neuling <mikey@neuling.org>\nSigned-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>\n---\n core/cpu.c | 20 ++++++++++++++------\n include/cpu.h | 1 +\n 2 files changed, 15 insertions(+), 6 deletions(-)", "diff": "diff --git a/core/cpu.c b/core/cpu.c\nindex 158f73e2..9d2cd56e 100644\n--- a/core/cpu.c\n+++ b/core/cpu.c\n@@ -823,9 +823,11 @@ struct cpu_thread *first_ungarded_cpu(void)\n \n struct cpu_thread *next_ungarded_primary(struct cpu_thread *cpu)\n {\n+\tbool is_primary;\n \tdo {\n \t\tcpu = next_cpu(cpu);\n-\t} while(cpu && (cpu->state == cpu_state_unavailable || cpu->primary != cpu));\n+\t\tis_primary = cpu == cpu->primary || cpu == cpu->ec_primary;\n+\t} while(cpu && (cpu->state == cpu_state_unavailable || !is_primary));\n \n \treturn cpu;\n }\n@@ -1157,7 +1159,7 @@ void init_all_cpus(void)\n \t\tunsigned int pir, server_no, chip_id, threads;\n \t\tenum cpu_thread_state state;\n \t\tconst struct dt_property *p;\n-\t\tstruct cpu_thread *t, *pt;\n+\t\tstruct cpu_thread *t, *pt0, *pt1;\n \n \t\t/* Skip cache nodes */\n \t\tif (strcmp(dt_prop_get(cpu, \"device_type\"), \"cpu\"))\n@@ -1194,14 +1196,18 @@ void init_all_cpus(void)\n \n \t\t/* Setup thread 0 */\n \t\tassert(pir <= cpu_max_pir);\n-\t\tt = pt = &cpu_stacks[pir].cpu;\n+\t\tt = pt0 = &cpu_stacks[pir].cpu;\n \t\tif (t != boot_cpu) {\n \t\t\tinit_cpu_thread(t, state, pir);\n \t\t\t/* Each cpu gets its own later in init_trace_buffers */\n \t\t\tt->trace = boot_cpu->trace;\n \t\t}\n+\t\tif (t->is_fused_core)\n+\t\t\tpt1 = &cpu_stacks[pir + 1].cpu;\n+\t\telse\n+\t\t\tpt1 = pt0;\n \t\tt->server_no = server_no;\n-\t\tt->primary = t;\n+\t\tt->primary = t->ec_primary = t;\n \t\tt->node = cpu;\n \t\tt->chip_id = chip_id;\n \t\tt->icp_regs = NULL; /* Will be set later */\n@@ -1239,10 +1245,12 @@ void init_all_cpus(void)\n \t\t\tt->trace = boot_cpu->trace;\n \t\t\tt->server_no = dt_property_get_cell(p, thread);\n \t\t\tt->is_secondary = true;\n-\t\t\tt->primary = pt;\n+\t\t\tt->is_fused_core = pt0->is_fused_core;\n+\t\t\tt->primary = pt0;\n+\t\t\tt->ec_primary = (thread & 1) ? pt1 : pt0;\n \t\t\tt->node = cpu;\n \t\t\tt->chip_id = chip_id;\n-\t\t\tt->core_hmi_state_ptr = &pt->core_hmi_state;\n+\t\t\tt->core_hmi_state_ptr = &pt0->core_hmi_state;\n \t\t}\n \t\tprlog(PR_INFO, \"CPU: %d secondary threads\\n\", thread);\n \t}\ndiff --git a/include/cpu.h b/include/cpu.h\nindex 1863d6ad..22f83440 100644\n--- a/include/cpu.h\n+++ b/include/cpu.h\n@@ -44,6 +44,7 @@ struct cpu_thread {\n \tbool\t\t\t\tis_secondary;\n \tbool\t\t\t\tis_fused_core;\n \tstruct cpu_thread\t\t*primary;\n+\tstruct cpu_thread\t\t*ec_primary;\n \tenum cpu_thread_state\t\tstate;\n \tstruct dt_node\t\t\t*node;\n \tstruct trace_info\t\t*trace;\n", "prefixes": [ "v6", "04/11" ] }