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GET /api/patches/1340945/?format=api
{ "id": 1340945, "url": "http://patchwork.ozlabs.org/api/patches/1340945/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/20200804173223.36280-3-svaidy@linux.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20200804173223.36280-3-svaidy@linux.ibm.com>", "list_archive_url": null, "date": "2020-08-04T17:32:14", "name": "[v6,02/11] xive: Set the fused core mode properly", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "3f17bb19dc72d642f1794b16be5d8b3e49ece3be", "submitter": { "id": 76774, "url": "http://patchwork.ozlabs.org/api/people/76774/?format=api", "name": "Vaidyanathan Srinivasan", "email": "svaidy@linux.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/20200804173223.36280-3-svaidy@linux.ibm.com/mbox/", "series": [ { "id": 194127, "url": "http://patchwork.ozlabs.org/api/series/194127/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/list/?series=194127", "date": "2020-08-04T17:32:14", "name": "Initial fused-core support for POWER9", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/194127/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1340945/comments/", "check": "success", "checks": "http://patchwork.ozlabs.org/api/patches/1340945/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest\n SHA256)\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 4BLhj927CSz9sTC\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 5 Aug 2020 03:35:09 +1000 (AEST)", "from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 4BLhj85Hf6zDqQC\n\tfor <incoming@patchwork.ozlabs.org>; Wed, 5 Aug 2020 03:35:08 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n [148.163.156.1])\n (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n (No client certificate requested)\n by lists.ozlabs.org (Postfix) with ESMTPS id 4BLhfJ3YFVzDqYq\n for <skiboot@lists.ozlabs.org>; Wed, 5 Aug 2020 03:32:40 +1000 (AEST)", "from pps.filterd (m0098394.ppops.net [127.0.0.1])\n by mx0a-001b2d01.pphosted.com (8.16.0.42/8.16.0.42) with SMTP id\n 074H334S019761; Tue, 4 Aug 2020 13:32:37 -0400", "from pps.reinject (localhost [127.0.0.1])\n by mx0a-001b2d01.pphosted.com with ESMTP id 32q86r0kwj-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 04 Aug 2020 13:32:37 -0400", "from m0098394.ppops.net (m0098394.ppops.net [127.0.0.1])\n by pps.reinject (8.16.0.36/8.16.0.36) with SMTP id 074HNUkc108123;\n Tue, 4 Aug 2020 13:32:36 -0400", "from ppma04fra.de.ibm.com (6a.4a.5195.ip4.static.sl-reverse.com\n [149.81.74.106])\n by mx0a-001b2d01.pphosted.com with ESMTP id 32q86r0kvf-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 04 Aug 2020 13:32:36 -0400", "from pps.filterd (ppma04fra.de.ibm.com [127.0.0.1])\n by ppma04fra.de.ibm.com (8.16.0.42/8.16.0.42) with SMTP id 074HPkEM032357;\n Tue, 4 Aug 2020 17:32:34 GMT", "from b06cxnps4074.portsmouth.uk.ibm.com\n (d06relay11.portsmouth.uk.ibm.com [9.149.109.196])\n by ppma04fra.de.ibm.com with ESMTP id 32n018a57f-1\n (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT);\n Tue, 04 Aug 2020 17:32:33 +0000", "from b06wcsmtp001.portsmouth.uk.ibm.com\n (b06wcsmtp001.portsmouth.uk.ibm.com [9.149.105.160])\n by b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n 074HWVQP29032928\n (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK);\n Tue, 4 Aug 2020 17:32:31 GMT", "from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 93BB3A405B;\n Tue, 4 Aug 2020 17:32:31 +0000 (GMT)", "from b06wcsmtp001.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n by IMSVA (Postfix) with ESMTP id 7E93DA405C;\n Tue, 4 Aug 2020 17:32:30 +0000 (GMT)", "from drishya.in.ibm.com (unknown [9.102.1.52])\n by b06wcsmtp001.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n Tue, 4 Aug 2020 17:32:30 +0000 (GMT)" ], "Authentication-Results": [ "ozlabs.org;\n dmarc=fail (p=none dis=none) header.from=linux.ibm.com", "lists.ozlabs.org; spf=pass (sender SPF authorized)\n smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1;\n helo=mx0a-001b2d01.pphosted.com; envelope-from=svaidy@linux.ibm.com;\n receiver=<UNKNOWN>)", "lists.ozlabs.org;\n dmarc=pass (p=none dis=none) header.from=linux.ibm.com" ], "From": "Vaidyanathan Srinivasan <svaidy@linux.ibm.com>", "To": "\"Oliver O'Halloran\" <oohall@gmail.com>", "Date": "Tue, 4 Aug 2020 23:02:14 +0530", "Message-Id": "<20200804173223.36280-3-svaidy@linux.ibm.com>", "X-Mailer": "git-send-email 2.26.2", "In-Reply-To": "<20200804173223.36280-1-svaidy@linux.ibm.com>", "References": "<20200804173223.36280-1-svaidy@linux.ibm.com>", "MIME-Version": "1.0", "X-TM-AS-GCONF": "00", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10434:6.0.235, 18.0.687\n definitions=2020-08-04_04:2020-08-03,\n 2020-08-04 signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n spamscore=0 impostorscore=0\n malwarescore=0 mlxlogscore=999 phishscore=0 clxscore=1011\n lowpriorityscore=0 bulkscore=0 priorityscore=1501 suspectscore=0\n mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1\n engine=8.12.0-2006250000 definitions=main-2008040126", "Subject": "[Skiboot] [PATCH v6 02/11] xive: Set the fused core mode properly", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n <mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n <mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "Cc": "skiboot@lists.ozlabs.org, Michael Neuling <mikey@neuling.org>", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n <skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "From: Benjamin Herrenschmidt <benh@kernel.crashing.org>\n\nSet or clear the fused core mode bit in the XIVE inits\nproperly. While HostBoot is supposed to do it, I prefer\nnot depending on it doing the right thing, since we already\nconfigure that register ourselves anyway.\n\nSigned-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>\nSigned-off-by: Michael Neuling <mikey@neuling.org>\nSigned-off-by: Vaidyanathan Srinivasan <svaidy@linux.ibm.com>\n---\n hw/xive.c | 4 ++++\n include/xive-p9-regs.h | 1 +\n 2 files changed, 5 insertions(+)", "diff": "diff --git a/hw/xive.c b/hw/xive.c\nindex 626ec182..9d09500e 100644\n--- a/hw/xive.c\n+++ b/hw/xive.c\n@@ -1531,6 +1531,10 @@ static bool xive_config_init(struct xive *x)\n \tval |= PC_TCTXT_CFG_LGS_EN;\n \t/* Disable pressure relief as we hijack the field in the VPs */\n \tval &= ~PC_TCTXT_CFG_STORE_ACK;\n+\tif (this_cpu()->is_fused_core)\n+\t\tval |= PC_TCTXT_CFG_FUSE_CORE_EN;\n+\telse\n+\t\tval &= ~PC_TCTXT_CFG_FUSE_CORE_EN;\n \txive_regw(x, PC_TCTXT_CFG, val);\n \txive_dbg(x, \"PC_TCTXT_CFG=%016llx\\n\", val);\n \ndiff --git a/include/xive-p9-regs.h b/include/xive-p9-regs.h\nindex 7d18a6bf..fff341cc 100644\n--- a/include/xive-p9-regs.h\n+++ b/include/xive-p9-regs.h\n@@ -80,6 +80,7 @@\n #define PC_TCTXT_CFG_TARGET_EN\t\tPPC_BIT(1)\n #define PC_TCTXT_CFG_LGS_EN\t\tPPC_BIT(2)\n #define PC_TCTXT_CFG_STORE_ACK\t\tPPC_BIT(3)\n+#define PC_TCTXT_CFG_FUSE_CORE_EN PPC_BIT(4)\n #define PC_TCTXT_CFG_HARD_CHIPID_BLK\tPPC_BIT(8)\n #define PC_TCTXT_CHIPID_OVERRIDE\tPPC_BIT(9)\n #define PC_TCTXT_CHIPID\t\tPPC_BITMASK(12,15)\n", "prefixes": [ "v6", "02/11" ] }