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GET /api/patches/1139009/?format=api
{ "id": 1139009, "url": "http://patchwork.ozlabs.org/api/patches/1139009/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190730142959.8467-5-laurentiu.tudor@nxp.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190730142959.8467-5-laurentiu.tudor@nxp.com>", "list_archive_url": null, "date": "2019-07-30T14:29:59", "name": "[U-Boot,5/5] armv8: ls1028a: add icid setup for platform devices", "commit_ref": null, "pull_url": null, "state": "accepted", "archived": false, "hash": "cbc97658b90c3b20e029a37ceeedfd56ae2fc55e", "submitter": { "id": 71003, "url": "http://patchwork.ozlabs.org/api/people/71003/?format=api", "name": "Laurentiu Tudor", "email": "laurentiu.tudor@nxp.com" }, "delegate": { "id": 2467, "url": "http://patchwork.ozlabs.org/api/users/2467/?format=api", "username": "prabhu_kush", "first_name": "Prabhakar", "last_name": "Kushwaha", "email": "prabhakar@freescale.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190730142959.8467-5-laurentiu.tudor@nxp.com/mbox/", "series": [ { "id": 122243, "url": "http://patchwork.ozlabs.org/api/series/122243/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=122243", "date": "2019-07-30T14:29:55", "name": "[U-Boot,1/5] armv8: fsl-layerscape: add missing sec jr base address defines", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/122243/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1139009/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1139009/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdmarc=fail (p=none dis=none) header.from=nxp.com" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45yfCd3SWwz9s8m\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 31 Jul 2019 00:32:29 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid E786CC21EA8; Tue, 30 Jul 2019 14:30:56 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id C9C9CC21EA1;\n\tTue, 30 Jul 2019 14:30:08 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid EE6D9C21DEC; Tue, 30 Jul 2019 14:30:05 +0000 (UTC)", "from inva020.nxp.com (inva020.nxp.com [92.121.34.13])\n\tby lists.denx.de (Postfix) with ESMTPS id A8B42C21DD7\n\tfor <u-boot@lists.denx.de>; Tue, 30 Jul 2019 14:30:05 +0000 (UTC)", "from inva020.nxp.com (localhost [127.0.0.1])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 7C5181A070B;\n\tTue, 30 Jul 2019 16:30:05 +0200 (CEST)", "from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com\n\t[134.27.226.22])\n\tby inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6FABD1A01CB;\n\tTue, 30 Jul 2019 16:30:05 +0200 (CEST)", "from fsr-ub1864-101.ea.freescale.net\n\t(fsr-ub1864-101.ea.freescale.net [10.171.82.13])\n\tby inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 11DAF205F3;\n\tTue, 30 Jul 2019 16:30:05 +0200 (CEST)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=none autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "From": "laurentiu.tudor@nxp.com", "To": "u-boot@lists.denx.de,\n\tprabhakar.kushwaha@nxp.com", "Date": "Tue, 30 Jul 2019 17:29:59 +0300", "Message-Id": "<20190730142959.8467-5-laurentiu.tudor@nxp.com>", "X-Mailer": "git-send-email 2.17.1", "In-Reply-To": "<20190730142959.8467-1-laurentiu.tudor@nxp.com>", "References": "<20190730142959.8467-1-laurentiu.tudor@nxp.com>", "X-Virus-Scanned": "ClamAV using ClamSMTP", "Subject": "[U-Boot] [PATCH 5/5] armv8: ls1028a: add icid setup for platform\n\tdevices", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Laurentiu Tudor <laurentiu.tudor@nxp.com>\n\nAdd ICID setup for the platform devices contained on this chip: usb,\nsata, sdhc, edma, qdma, gpu, display and sec.\n\nSigned-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>\n---\n arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +\n .../arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 33 ++++++++++++++++\n .../arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 +-\n arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-\n .../asm/arch-fsl-layerscape/fsl_icid.h | 38 +++++++++++++------\n .../asm/arch-fsl-layerscape/immap_lsch3.h | 6 ++-\n .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 7 +++-\n board/freescale/ls1028a/ls1028a.c | 3 ++\n 8 files changed, 76 insertions(+), 16 deletions(-)\n create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c", "diff": "diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile\nindex aa88b93175..efecbc07e7 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile\n@@ -52,4 +52,5 @@ endif\n \n ifneq ($(CONFIG_ARCH_LS1028A),)\n obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o\n+obj-y += icid.o ls1028_ids.o\n endif\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c\nnew file mode 100644\nindex 0000000000..d9d125e8ba\n--- /dev/null\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c\n@@ -0,0 +1,33 @@\n+// SPDX-License-Identifier: GPL-2.0+\n+/*\n+ * Copyright 2019 NXP\n+ */\n+\n+#include <common.h>\n+#include <asm/arch-fsl-layerscape/immap_lsch3.h>\n+#include <asm/arch-fsl-layerscape/fsl_icid.h>\n+#include <asm/arch-fsl-layerscape/fsl_portals.h>\n+\n+struct icid_id_table icid_tbl[] = {\n+\tSET_USB_ICID(1, \"snps,dwc3\", FSL_USB1_STREAM_ID),\n+\tSET_USB_ICID(2, \"snps,dwc3\", FSL_USB2_STREAM_ID),\n+\tSET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),\n+\tSET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID),\n+\tSET_SATA_ICID(1, \"fsl,ls1028a-ahci\", FSL_SATA1_STREAM_ID),\n+\tSET_EDMA_ICID(FSL_EDMA_STREAM_ID),\n+\tSET_QDMA_ICID(\"fsl,ls1028a-qdma\", FSL_DMA_STREAM_ID),\n+\tSET_GPU_ICID(\"fsl,ls1028a-gpu\", FSL_GPU_STREAM_ID),\n+\tSET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID),\n+\tSET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID),\n+\tSET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID),\n+\tSET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID),\n+\tSET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID),\n+\tSET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID),\n+\tSET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID),\n+\tSET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID),\n+\tSET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID),\n+\tSET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID),\n+\tSET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID),\n+};\n+\n+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c\nindex 956d6e78c8..49e27553b1 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c\n@@ -9,7 +9,7 @@\n #include <asm/arch-fsl-layerscape/fsl_portals.h>\n \n struct icid_id_table icid_tbl[] = {\n-\tSET_SDHC_ICID(FSL_SDMMC_STREAM_ID),\n+\tSET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),\n \tSET_USB_ICID(1, \"snps,dwc3\", FSL_USB1_STREAM_ID),\n \tSET_USB_ICID(2, \"snps,dwc3\", FSL_USB2_STREAM_ID),\n \tSET_SATA_ICID(1, \"fsl,ls1088a-ahci\", FSL_SATA1_STREAM_ID),\ndiff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\nindex 467c34649f..eca21db289 100644\n--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c\n@@ -340,7 +340,7 @@ void fsl_lsch3_early_init_f(void)\n \t\tbypass_smmu();\n #endif\n \n-#ifdef CONFIG_ARCH_LS1088A\n+#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)\n \tset_icids();\n #endif\n }\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h\nindex feb3304364..37e2fe4e66 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h\n@@ -54,6 +54,8 @@ void fdt_fixup_icid(void *blob);\n #define SCFG_IS_LE false\n #endif\n \n+#define QDMA_IS_LE false\n+\n #define SET_SCFG_ICID(compat, streamid, name, compataddr) \\\n \tSET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \\\n \t\toffsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \\\n@@ -71,14 +73,6 @@ void fdt_fixup_icid(void *blob);\n \tSET_SCFG_ICID(\"fsl,esdhc\", streamid, sdhc_icid,\\\n \t\tCONFIG_SYS_FSL_ESDHC_ADDR)\n \n-#define SET_QDMA_ICID(compat, streamid) \\\n-\tSET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \\\n-\t\tQDMA_BASE_ADDR + QMAN_CQSIDR_REG, \\\n-\t\tQDMA_BASE_ADDR, false), \\\n-\tSET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \\\n-\t\tQDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \\\n-\t\tQDMA_BASE_ADDR, false)\n-\n #define SET_EDMA_ICID(streamid) \\\n \tSET_SCFG_ICID(\"fsl,vf610-edma\", streamid, edma_icid,\\\n \t\tEDMA_BASE_ADDR)\n@@ -127,6 +121,8 @@ extern int fman_icid_tbl_sz;\n #define GUR_IS_LE false\n #endif\n \n+#define QDMA_IS_LE true\n+\n #define SET_GUR_ICID(compat, streamid, name, compataddr) \\\n \tSET_ICID_ENTRY(compat, streamid, streamid, \\\n \t\toffsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \\\n@@ -140,14 +136,34 @@ extern int fman_icid_tbl_sz;\n \tSET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \\\n \t\tAHCI_BASE_ADDR##sata_num)\n \n-#define SET_SDHC_ICID(streamid) \\\n-\tSET_GUR_ICID(\"fsl,esdhc\", streamid, sdmm1_amqr,\\\n-\t\tCONFIG_SYS_FSL_ESDHC_ADDR)\n+#define SET_SDHC_ICID(sdhc_num, streamid) \\\n+\tSET_GUR_ICID(\"fsl,esdhc\", streamid, sdmm##sdhc_num##_amqr,\\\n+\t\tFSL_ESDHC##sdhc_num##_BASE_ADDR)\n+\n+#define SET_EDMA_ICID(streamid) \\\n+\tSET_GUR_ICID(\"fsl,vf610-edma\", streamid, spare3_amqr,\\\n+\t\tEDMA_BASE_ADDR)\n+\n+#define SET_GPU_ICID(compat, streamid) \\\n+\tSET_GUR_ICID(compat, streamid, misc1_amqr,\\\n+\t\tGPU_BASE_ADDR)\n+\n+#define SET_DISPLAY_ICID(streamid) \\\n+\tSET_GUR_ICID(\"arm,mali-dp500\", streamid, spare2_amqr,\\\n+\t\tDISPLAY_BASE_ADDR)\n \n #define SEC_ICID_REG_VAL(streamid) (streamid)\n \n #endif /* CONFIG_FSL_LSCH2 */\n \n+#define SET_QDMA_ICID(compat, streamid) \\\n+\tSET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \\\n+\t\tQDMA_BASE_ADDR + QMAN_CQSIDR_REG, \\\n+\t\tQDMA_BASE_ADDR, QDMA_IS_LE), \\\n+\tSET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \\\n+\t\tQDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \\\n+\t\tQDMA_BASE_ADDR, QDMA_IS_LE)\n+\n #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \\\n \tSET_ICID_ENTRY( \\\n \t\t(CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \\\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\nindex 84bed8d423..8a5446df1a 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h\n@@ -440,7 +440,8 @@ struct ccsr_gur {\n \tu32\tusb2_amqr;\n \tu8\tres_528[0x530-0x528];\t/* add more registers when needed */\n \tu32\tsdmm1_amqr;\n-\tu8\tres_534[0x550-0x534];\t/* add more registers when needed */\n+\tu32\tsdmm2_amqr;\n+\tu8\tres_538[0x550 - 0x538];\t/* add more registers when needed */\n \tu32\tsata1_amqr;\n \tu32\tsata2_amqr;\n \tu8\tres_558[0x570-0x558];\t/* add more registers when needed */\n@@ -448,7 +449,8 @@ struct ccsr_gur {\n \tu8\tres_574[0x590-0x574];\t/* add more registers when needed */\n \tu32\tspare1_amqr;\n \tu32\tspare2_amqr;\n-\tu8\tres_598[0x620-0x598];\t/* add more registers when needed */\n+\tu32\tspare3_amqr;\n+\tu8\tres_59c[0x620 - 0x59c];\t/* add more registers when needed */\n \tu32\tgencr[7];\t/* General Control Registers */\n \tu8\tres_63c[0x640-0x63c];\t/* add more registers when needed */\n \tu32\tcgensr1;\t/* Core General Status Register */\ndiff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\nindex 383eb259bd..93bdcc4caa 100644\n--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\n+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h\n@@ -76,7 +76,7 @@\n \n #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A)\n #define FSL_DMA_STREAM_ID\t\t6\n-#elif defined(CONFIG_ARCH_LS1088A)\n+#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A)\n #define FSL_DMA_STREAM_ID\t\t5\n #endif\n \n@@ -104,4 +104,9 @@\n #define FSL_SEC_JR3_STREAM_ID\t\t67\n #define FSL_SEC_JR4_STREAM_ID\t\t68\n \n+#define FSL_SDMMC2_STREAM_ID\t\t69\n+#define FSL_EDMA_STREAM_ID\t\t70\n+#define FSL_GPU_STREAM_ID\t\t71\n+#define FSL_DISPLAY_STREAM_ID\t\t72\n+\n #endif\ndiff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c\nindex e5de4eb70c..d64481d27e 100644\n--- a/board/freescale/ls1028a/ls1028a.c\n+++ b/board/freescale/ls1028a/ls1028a.c\n@@ -13,6 +13,7 @@\n #include <linux/libfdt.h>\n #include <environment.h>\n #include <asm/arch-fsl-layerscape/soc.h>\n+#include <asm/arch-fsl-layerscape/fsl_icid.h>\n #include <i2c.h>\n #include <asm/arch/soc.h>\n #ifdef CONFIG_FSL_LS_PPA\n@@ -135,6 +136,8 @@ int ft_board_setup(void *blob, bd_t *bd)\n \n \tfdt_fixup_memory_banks(blob, base, size, 2);\n \n+\tfdt_fixup_icid(blob);\n+\n \treturn 0;\n }\n #endif\n", "prefixes": [ "U-Boot", "5/5" ] }