From patchwork Tue Jul 30 14:29:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Laurentiu Tudor X-Patchwork-Id: 1139009 X-Patchwork-Delegate: prabhakar@freescale.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=nxp.com Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45yfCd3SWwz9s8m for ; Wed, 31 Jul 2019 00:32:29 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id E786CC21EA8; Tue, 30 Jul 2019 14:30:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C9C9CC21EA1; Tue, 30 Jul 2019 14:30:08 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EE6D9C21DEC; Tue, 30 Jul 2019 14:30:05 +0000 (UTC) Received: from inva020.nxp.com (inva020.nxp.com [92.121.34.13]) by lists.denx.de (Postfix) with ESMTPS id A8B42C21DD7 for ; Tue, 30 Jul 2019 14:30:05 +0000 (UTC) Received: from inva020.nxp.com (localhost [127.0.0.1]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 7C5181A070B; Tue, 30 Jul 2019 16:30:05 +0200 (CEST) Received: from inva024.eu-rdc02.nxp.com (inva024.eu-rdc02.nxp.com [134.27.226.22]) by inva020.eu-rdc02.nxp.com (Postfix) with ESMTP id 6FABD1A01CB; Tue, 30 Jul 2019 16:30:05 +0200 (CEST) Received: from fsr-ub1864-101.ea.freescale.net (fsr-ub1864-101.ea.freescale.net [10.171.82.13]) by inva024.eu-rdc02.nxp.com (Postfix) with ESMTP id 11DAF205F3; Tue, 30 Jul 2019 16:30:05 +0200 (CEST) From: laurentiu.tudor@nxp.com To: u-boot@lists.denx.de, prabhakar.kushwaha@nxp.com Date: Tue, 30 Jul 2019 17:29:59 +0300 Message-Id: <20190730142959.8467-5-laurentiu.tudor@nxp.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190730142959.8467-1-laurentiu.tudor@nxp.com> References: <20190730142959.8467-1-laurentiu.tudor@nxp.com> X-Virus-Scanned: ClamAV using ClamSMTP Subject: [U-Boot] [PATCH 5/5] armv8: ls1028a: add icid setup for platform devices X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Laurentiu Tudor Add ICID setup for the platform devices contained on this chip: usb, sata, sdhc, edma, qdma, gpu, display and sec. Signed-off-by: Laurentiu Tudor Reviewed-by: Horia Geantă --- arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 + .../arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 33 ++++++++++++++++ .../arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +- .../asm/arch-fsl-layerscape/fsl_icid.h | 38 +++++++++++++------ .../asm/arch-fsl-layerscape/immap_lsch3.h | 6 ++- .../asm/arch-fsl-layerscape/stream_id_lsch3.h | 7 +++- board/freescale/ls1028a/ls1028a.c | 3 ++ 8 files changed, 76 insertions(+), 16 deletions(-) create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index aa88b93175..efecbc07e7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -52,4 +52,5 @@ endif ifneq ($(CONFIG_ARCH_LS1028A),) obj-$(CONFIG_SYS_HAS_SERDES) += ls1028a_serdes.o +obj-y += icid.o ls1028_ids.o endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c new file mode 100644 index 0000000000..d9d125e8ba --- /dev/null +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include +#include +#include +#include + +struct icid_id_table icid_tbl[] = { + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), + SET_SDHC_ICID(2, FSL_SDMMC2_STREAM_ID), + SET_SATA_ICID(1, "fsl,ls1028a-ahci", FSL_SATA1_STREAM_ID), + SET_EDMA_ICID(FSL_EDMA_STREAM_ID), + SET_QDMA_ICID("fsl,ls1028a-qdma", FSL_DMA_STREAM_ID), + SET_GPU_ICID("fsl,ls1028a-gpu", FSL_GPU_STREAM_ID), + SET_DISPLAY_ICID(FSL_DISPLAY_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(0, FSL_SEC_JR1_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(1, FSL_SEC_JR2_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(2, FSL_SEC_JR3_STREAM_ID), + SET_SEC_JR_ICID_ENTRY(3, FSL_SEC_JR4_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(1, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(2, FSL_SEC_STREAM_ID), + SET_SEC_RTIC_ICID_ENTRY(3, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(0, FSL_SEC_STREAM_ID), + SET_SEC_DECO_ICID_ENTRY(1, FSL_SEC_STREAM_ID), +}; + +int icid_tbl_sz = ARRAY_SIZE(icid_tbl); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c index 956d6e78c8..49e27553b1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c @@ -9,7 +9,7 @@ #include struct icid_id_table icid_tbl[] = { - SET_SDHC_ICID(FSL_SDMMC_STREAM_ID), + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID), SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID), SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID), SET_SATA_ICID(1, "fsl,ls1088a-ahci", FSL_SATA1_STREAM_ID), diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 467c34649f..eca21db289 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -340,7 +340,7 @@ void fsl_lsch3_early_init_f(void) bypass_smmu(); #endif -#ifdef CONFIG_ARCH_LS1088A +#if defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) set_icids(); #endif } diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index feb3304364..37e2fe4e66 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -54,6 +54,8 @@ void fdt_fixup_icid(void *blob); #define SCFG_IS_LE false #endif +#define QDMA_IS_LE false + #define SET_SCFG_ICID(compat, streamid, name, compataddr) \ SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \ offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \ @@ -71,14 +73,6 @@ void fdt_fixup_icid(void *blob); SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\ CONFIG_SYS_FSL_ESDHC_ADDR) -#define SET_QDMA_ICID(compat, streamid) \ - SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ - QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ - QDMA_BASE_ADDR, false), \ - SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ - QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ - QDMA_BASE_ADDR, false) - #define SET_EDMA_ICID(streamid) \ SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\ EDMA_BASE_ADDR) @@ -127,6 +121,8 @@ extern int fman_icid_tbl_sz; #define GUR_IS_LE false #endif +#define QDMA_IS_LE true + #define SET_GUR_ICID(compat, streamid, name, compataddr) \ SET_ICID_ENTRY(compat, streamid, streamid, \ offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \ @@ -140,14 +136,34 @@ extern int fman_icid_tbl_sz; SET_GUR_ICID(compat, streamid, sata##sata_num##_amqr, \ AHCI_BASE_ADDR##sata_num) -#define SET_SDHC_ICID(streamid) \ - SET_GUR_ICID("fsl,esdhc", streamid, sdmm1_amqr,\ - CONFIG_SYS_FSL_ESDHC_ADDR) +#define SET_SDHC_ICID(sdhc_num, streamid) \ + SET_GUR_ICID("fsl,esdhc", streamid, sdmm##sdhc_num##_amqr,\ + FSL_ESDHC##sdhc_num##_BASE_ADDR) + +#define SET_EDMA_ICID(streamid) \ + SET_GUR_ICID("fsl,vf610-edma", streamid, spare3_amqr,\ + EDMA_BASE_ADDR) + +#define SET_GPU_ICID(compat, streamid) \ + SET_GUR_ICID(compat, streamid, misc1_amqr,\ + GPU_BASE_ADDR) + +#define SET_DISPLAY_ICID(streamid) \ + SET_GUR_ICID("arm,mali-dp500", streamid, spare2_amqr,\ + DISPLAY_BASE_ADDR) #define SEC_ICID_REG_VAL(streamid) (streamid) #endif /* CONFIG_FSL_LSCH2 */ +#define SET_QDMA_ICID(compat, streamid) \ + SET_ICID_ENTRY(compat, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG, \ + QDMA_BASE_ADDR, QDMA_IS_LE), \ + SET_ICID_ENTRY(NULL, streamid, (1 << 31) | (streamid), \ + QDMA_BASE_ADDR + QMAN_CQSIDR_REG + 4, \ + QDMA_BASE_ADDR, QDMA_IS_LE) + #define SET_SEC_JR_ICID_ENTRY(jr_num, streamid) \ SET_ICID_ENTRY( \ (CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT && \ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 84bed8d423..8a5446df1a 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -440,7 +440,8 @@ struct ccsr_gur { u32 usb2_amqr; u8 res_528[0x530-0x528]; /* add more registers when needed */ u32 sdmm1_amqr; - u8 res_534[0x550-0x534]; /* add more registers when needed */ + u32 sdmm2_amqr; + u8 res_538[0x550 - 0x538]; /* add more registers when needed */ u32 sata1_amqr; u32 sata2_amqr; u8 res_558[0x570-0x558]; /* add more registers when needed */ @@ -448,7 +449,8 @@ struct ccsr_gur { u8 res_574[0x590-0x574]; /* add more registers when needed */ u32 spare1_amqr; u32 spare2_amqr; - u8 res_598[0x620-0x598]; /* add more registers when needed */ + u32 spare3_amqr; + u8 res_59c[0x620 - 0x59c]; /* add more registers when needed */ u32 gencr[7]; /* General Control Registers */ u8 res_63c[0x640-0x63c]; /* add more registers when needed */ u32 cgensr1; /* Core General Status Register */ diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h index 383eb259bd..93bdcc4caa 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch3.h @@ -76,7 +76,7 @@ #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LX2160A) #define FSL_DMA_STREAM_ID 6 -#elif defined(CONFIG_ARCH_LS1088A) +#elif defined(CONFIG_ARCH_LS1088A) || defined(CONFIG_ARCH_LS1028A) #define FSL_DMA_STREAM_ID 5 #endif @@ -104,4 +104,9 @@ #define FSL_SEC_JR3_STREAM_ID 67 #define FSL_SEC_JR4_STREAM_ID 68 +#define FSL_SDMMC2_STREAM_ID 69 +#define FSL_EDMA_STREAM_ID 70 +#define FSL_GPU_STREAM_ID 71 +#define FSL_DISPLAY_STREAM_ID 72 + #endif diff --git a/board/freescale/ls1028a/ls1028a.c b/board/freescale/ls1028a/ls1028a.c index e5de4eb70c..d64481d27e 100644 --- a/board/freescale/ls1028a/ls1028a.c +++ b/board/freescale/ls1028a/ls1028a.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #ifdef CONFIG_FSL_LS_PPA @@ -135,6 +136,8 @@ int ft_board_setup(void *blob, bd_t *bd) fdt_fixup_memory_banks(blob, base, size, 2); + fdt_fixup_icid(blob); + return 0; } #endif