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GET /api/patches/1132698/?format=api
{ "id": 1132698, "url": "http://patchwork.ozlabs.org/api/patches/1132698/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-37-jagan@amarulasolutions.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20190716115745.12585-37-jagan@amarulasolutions.com>", "list_archive_url": null, "date": "2019-07-16T11:57:24", "name": "[U-Boot,v3,36/57] ram: rk3399: Configure soc odt support", "commit_ref": "f288d54936d7360e934132a128d7e92d3b1c95a0", "pull_url": null, "state": "accepted", "archived": false, "hash": "defcd77220893ad0e93e7c3352f62c3826454f4e", "submitter": { "id": 69820, "url": "http://patchwork.ozlabs.org/api/people/69820/?format=api", "name": "Jagan Teki", "email": "jagan@amarulasolutions.com" }, "delegate": { "id": 93623, "url": "http://patchwork.ozlabs.org/api/users/93623/?format=api", "username": "kevery", "first_name": "Kever", "last_name": "Yang", "email": "ykai007@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20190716115745.12585-37-jagan@amarulasolutions.com/mbox/", "series": [ { "id": 119754, "url": "http://patchwork.ozlabs.org/api/series/119754/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=119754", "date": "2019-07-16T11:56:48", "name": "ram: rk3399: Add LPDDR4 support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/119754/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/1132698/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/1132698/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dmarc=none (p=none dis=none)\n\theader.from=amarulasolutions.com", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=amarulasolutions.com\n\theader.i=@amarulasolutions.com header.b=\"fxMyMKHQ\"; \n\tdkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 45nzp60B17z9sDB\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 16 Jul 2019 22:13:49 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 7CC0EC21E47; Tue, 16 Jul 2019 12:10:48 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 0BB31C21E52;\n\tTue, 16 Jul 2019 12:08:39 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid A8395C21C6A; Tue, 16 Jul 2019 12:00:12 +0000 (UTC)", "from mail-pf1-f195.google.com (mail-pf1-f195.google.com\n\t[209.85.210.195])\n\tby lists.denx.de (Postfix) with ESMTPS id 1C06DC21E60\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 12:00:06 +0000 (UTC)", "by mail-pf1-f195.google.com with SMTP id g2so9022410pfq.0\n\tfor <u-boot@lists.denx.de>; Tue, 16 Jul 2019 05:00:06 -0700 (PDT)", "from localhost.localdomain ([49.206.201.107])\n\tby smtp.gmail.com with ESMTPSA id\n\tz24sm36269566pfr.51.2019.07.16.05.00.01\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tTue, 16 Jul 2019 05:00:04 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3,\n\tRCVD_IN_MSPIKE_WL,\n\tT_DKIM_INVALID autolearn=unavailable autolearn_force=no\n\tversion=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=amarulasolutions.com; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=uJaha5qbi/fzESpsHy2ICJEbRyPTEVDRBKY1OAzcEjI=;\n\tb=fxMyMKHQlRZcQdid2Y4MfQYIItmUQw8UEYIzR5TQs4ZdPevDHIdOCiVeWh2hi0pOls\n\txHUMqQvrTVJosSGXplBFPfmdcBfWoRXjWm2R2O9Dpm1uHoM5IyRoi48OqMxt4yNcXI3z\n\t8050xeCjvQrZbwC58qR7KoQIme3srUQ7KoMjI=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references:mime-version:content-transfer-encoding;\n\tbh=uJaha5qbi/fzESpsHy2ICJEbRyPTEVDRBKY1OAzcEjI=;\n\tb=pfeY7xotoKw6Fz3YnLU7e8Ymz9K5Dhdv6Y1uX5lJ/YYCc0FL46RjP2kAMNaSdOwudy\n\t/0Jhb/kLGgsziIEEe8nsrKUISMGFp4hMkjHZBeQojALbVAksHS1tpX0HnCysBBUBHM88\n\tezrbk+KKtsFV0nH/lZBurqMDe2wi433AOkK+jiEJXOOSlJFAy0c4M8C/ZIk8yPrvjguD\n\tDF5rxsuaNnEK+/sYOBaUvfM0HBLLL17/xcR1fStbh+DGqNqYoX/SJPFr0sZ8X3gj6ixy\n\tanxzIXzCgEOpbOpXjdz61sLv28LaR2KgEUKrYRipW8Hs5+xTr3p5FwsVMb5avy5q1YTW\n\tbP2Q==", "X-Gm-Message-State": "APjAAAX61Bd0OWXN/Dvmlt50OTKvKoKXB3KwyQqCajEAs0zwk/T4syjq\n\tPl3aV2OMhqRPPaTSQzpprzbTQAvjUZf1KQ==", "X-Google-Smtp-Source": "APXvYqz0hU5nUJh5VO5fSaJ+ceWkrhncjbPHuPEH0UyXZ2qISFsN2yPLiWIX7q9EmkMz43+qlxlSYQ==", "X-Received": "by 2002:a63:2606:: with SMTP id\n\tm6mr32927678pgm.436.1563278404676; \n\tTue, 16 Jul 2019 05:00:04 -0700 (PDT)", "From": "Jagan Teki <jagan@amarulasolutions.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tPhilipp Tomsich <philipp.tomsich@theobroma-systems.com>,\n\tKever Yang <kever.yang@rock-chips.com>,\n\tYouMin Chen <cym@rock-chips.com>, u-boot@lists.denx.de", "Date": "Tue, 16 Jul 2019 17:27:24 +0530", "Message-Id": "<20190716115745.12585-37-jagan@amarulasolutions.com>", "X-Mailer": "git-send-email 2.18.0.321.gffc6fa0e3", "In-Reply-To": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "References": "<20190716115745.12585-1-jagan@amarulasolutions.com>", "MIME-Version": "1.0", "Cc": "linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com,\n\tlinux-amarula@amarulasolutions.com,\n\tManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>", "Subject": "[U-Boot] [PATCH v3 36/57] ram: rk3399: Configure soc odt support", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "CTL 145, 146, 159, 160 registers are used to configure\nsoc odt on rk3399.\n\nThese soc odt values are updated from CS0_MR22_VAL and\nCS1_MR22_VAL and for lpddr4 these values ORed with\ntsel_rd_select_n.\n\nSigned-off-by: Jagan Teki <jagan@amarulasolutions.com>\nSigned-off-by: YouMin Chen <cym@rock-chips.com>\n---\n drivers/ram/rockchip/sdram_rk3399.c | 49 ++++++++++++++++++++++++++++-\n 1 file changed, 48 insertions(+), 1 deletion(-)", "diff": "diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c\nindex c38ea1d284..e0be9d2485 100644\n--- a/drivers/ram/rockchip/sdram_rk3399.c\n+++ b/drivers/ram/rockchip/sdram_rk3399.c\n@@ -40,6 +40,8 @@\n #define PHY_SLEWP_EN\t\t0x1\n #define PHY_SLEWN_EN\t\t0x1\n #define PHY_RX_CM_INPUT\t\t0x1\n+#define CS0_MR22_VAL\t\t0\n+#define CS1_MR22_VAL\t\t3\n \n #define CRU_SFTRST_DDR_CTRL(ch, n)\t((0x1 << (8 + 16 + (ch) * 4)) | \\\n \t\t\t\t\t((n) << (8 + (ch) * 4)))\n@@ -554,7 +556,7 @@ static void set_ds_odt(const struct chan_info *chan,\n \t\t const struct rk3399_sdram_params *params, u32 mr5)\n {\n \tu32 *denali_phy = chan->publ->denali_phy;\n-\n+\tu32 *denali_ctl = chan->pctl->denali_ctl;\n \tu32 tsel_idle_en, tsel_wr_en, tsel_rd_en;\n \tu32 tsel_idle_select_p, tsel_rd_select_p;\n \tu32 tsel_idle_select_n, tsel_rd_select_n;\n@@ -562,6 +564,7 @@ static void set_ds_odt(const struct chan_info *chan,\n \tu32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;\n \tu32 tsel_ckcs_select_p, tsel_ckcs_select_n;\n \tstruct io_setting *io = NULL;\n+\tu32 soc_odt = 0;\n \tu32 reg_value;\n \n \tif (params->base.dramtype == LPDDR4) {\n@@ -581,6 +584,35 @@ static void set_ds_odt(const struct chan_info *chan,\n \n \t\ttsel_ckcs_select_p = io->wr_ckcs_drv;\n \t\ttsel_ckcs_select_n = PHY_DRV_ODT_34_3;\n+\t\tswitch (tsel_rd_select_n) {\n+\t\tcase PHY_DRV_ODT_240:\n+\t\t\tsoc_odt = 1;\n+\t\t\tbreak;\n+\t\tcase PHY_DRV_ODT_120:\n+\t\t\tsoc_odt = 2;\n+\t\t\tbreak;\n+\t\tcase PHY_DRV_ODT_80:\n+\t\t\tsoc_odt = 3;\n+\t\t\tbreak;\n+\t\tcase PHY_DRV_ODT_60:\n+\t\t\tsoc_odt = 4;\n+\t\t\tbreak;\n+\t\tcase PHY_DRV_ODT_48:\n+\t\t\tsoc_odt = 5;\n+\t\t\tbreak;\n+\t\tcase PHY_DRV_ODT_40:\n+\t\t\tsoc_odt = 6;\n+\t\t\tbreak;\n+\t\tcase PHY_DRV_ODT_34_3:\n+\t\t\tsoc_odt = 6;\n+\t\t\tprintf(\"%s: Unable to support LPDDR4 MR22 Soc ODT\\n\",\n+\t\t\t __func__);\n+\t\t\tbreak;\n+\t\tcase PHY_DRV_ODT_HI_Z:\n+\t\tdefault:\n+\t\t\tsoc_odt = 0;\n+\t\t\tbreak;\n+\t\t}\n \t} else if (params->base.dramtype == LPDDR3) {\n \t\ttsel_rd_select_p = PHY_DRV_ODT_240;\n \t\ttsel_rd_select_n = PHY_DRV_ODT_HI_Z;\n@@ -621,6 +653,21 @@ static void set_ds_odt(const struct chan_info *chan,\n \ttsel_wr_en = 0;\n \ttsel_idle_en = 0;\n \n+\t/* F0_0 */\n+\tclrsetbits_le32(&denali_ctl[145], 0xFF << 16,\n+\t\t\t(soc_odt | (CS0_MR22_VAL << 3)) << 16);\n+\t/* F2_0, F1_0 */\n+\tclrsetbits_le32(&denali_ctl[146], 0xFF00FF,\n+\t\t\t((soc_odt | (CS0_MR22_VAL << 3)) << 16) |\n+\t\t\t(soc_odt | (CS0_MR22_VAL << 3)));\n+\t/* F0_1 */\n+\tclrsetbits_le32(&denali_ctl[159], 0xFF << 16,\n+\t\t\t(soc_odt | (CS1_MR22_VAL << 3)) << 16);\n+\t/* F2_1, F1_1 */\n+\tclrsetbits_le32(&denali_ctl[160], 0xFF00FF,\n+\t\t\t((soc_odt | (CS1_MR22_VAL << 3)) << 16) |\n+\t\t\t(soc_odt | (CS1_MR22_VAL << 3)));\n+\n \t/*\n \t * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0\n \t * sets termination values for read/idle cycles and drive strength\n", "prefixes": [ "U-Boot", "v3", "36/57" ] }