From patchwork Tue Jul 16 11:57:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 1132698 X-Patchwork-Delegate: ykai007@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amarulasolutions.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=amarulasolutions.com header.i=@amarulasolutions.com header.b="fxMyMKHQ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 45nzp60B17z9sDB for ; Tue, 16 Jul 2019 22:13:49 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 7CC0EC21E47; Tue, 16 Jul 2019 12:10:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0BB31C21E52; Tue, 16 Jul 2019 12:08:39 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A8395C21C6A; Tue, 16 Jul 2019 12:00:12 +0000 (UTC) Received: from mail-pf1-f195.google.com (mail-pf1-f195.google.com [209.85.210.195]) by lists.denx.de (Postfix) with ESMTPS id 1C06DC21E60 for ; Tue, 16 Jul 2019 12:00:06 +0000 (UTC) Received: by mail-pf1-f195.google.com with SMTP id g2so9022410pfq.0 for ; Tue, 16 Jul 2019 05:00:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=uJaha5qbi/fzESpsHy2ICJEbRyPTEVDRBKY1OAzcEjI=; b=fxMyMKHQlRZcQdid2Y4MfQYIItmUQw8UEYIzR5TQs4ZdPevDHIdOCiVeWh2hi0pOls xHUMqQvrTVJosSGXplBFPfmdcBfWoRXjWm2R2O9Dpm1uHoM5IyRoi48OqMxt4yNcXI3z 8050xeCjvQrZbwC58qR7KoQIme3srUQ7KoMjI= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uJaha5qbi/fzESpsHy2ICJEbRyPTEVDRBKY1OAzcEjI=; b=pfeY7xotoKw6Fz3YnLU7e8Ymz9K5Dhdv6Y1uX5lJ/YYCc0FL46RjP2kAMNaSdOwudy /0Jhb/kLGgsziIEEe8nsrKUISMGFp4hMkjHZBeQojALbVAksHS1tpX0HnCysBBUBHM88 ezrbk+KKtsFV0nH/lZBurqMDe2wi433AOkK+jiEJXOOSlJFAy0c4M8C/ZIk8yPrvjguD DF5rxsuaNnEK+/sYOBaUvfM0HBLLL17/xcR1fStbh+DGqNqYoX/SJPFr0sZ8X3gj6ixy anxzIXzCgEOpbOpXjdz61sLv28LaR2KgEUKrYRipW8Hs5+xTr3p5FwsVMb5avy5q1YTW bP2Q== X-Gm-Message-State: APjAAAX61Bd0OWXN/Dvmlt50OTKvKoKXB3KwyQqCajEAs0zwk/T4syjq Pl3aV2OMhqRPPaTSQzpprzbTQAvjUZf1KQ== X-Google-Smtp-Source: APXvYqz0hU5nUJh5VO5fSaJ+ceWkrhncjbPHuPEH0UyXZ2qISFsN2yPLiWIX7q9EmkMz43+qlxlSYQ== X-Received: by 2002:a63:2606:: with SMTP id m6mr32927678pgm.436.1563278404676; Tue, 16 Jul 2019 05:00:04 -0700 (PDT) Received: from localhost.localdomain ([49.206.201.107]) by smtp.gmail.com with ESMTPSA id z24sm36269566pfr.51.2019.07.16.05.00.01 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 16 Jul 2019 05:00:04 -0700 (PDT) From: Jagan Teki To: Simon Glass , Philipp Tomsich , Kever Yang , YouMin Chen , u-boot@lists.denx.de Date: Tue, 16 Jul 2019 17:27:24 +0530 Message-Id: <20190716115745.12585-37-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.18.0.321.gffc6fa0e3 In-Reply-To: <20190716115745.12585-1-jagan@amarulasolutions.com> References: <20190716115745.12585-1-jagan@amarulasolutions.com> MIME-Version: 1.0 Cc: linux-rockchip@lists.infradead.org, gajjar04akash@gmail.com, linux-amarula@amarulasolutions.com, Manivannan Sadhasivam Subject: [U-Boot] [PATCH v3 36/57] ram: rk3399: Configure soc odt support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" CTL 145, 146, 159, 160 registers are used to configure soc odt on rk3399. These soc odt values are updated from CS0_MR22_VAL and CS1_MR22_VAL and for lpddr4 these values ORed with tsel_rd_select_n. Signed-off-by: Jagan Teki Signed-off-by: YouMin Chen Reviewed-by: Kever Yang --- drivers/ram/rockchip/sdram_rk3399.c | 49 ++++++++++++++++++++++++++++- 1 file changed, 48 insertions(+), 1 deletion(-) diff --git a/drivers/ram/rockchip/sdram_rk3399.c b/drivers/ram/rockchip/sdram_rk3399.c index c38ea1d284..e0be9d2485 100644 --- a/drivers/ram/rockchip/sdram_rk3399.c +++ b/drivers/ram/rockchip/sdram_rk3399.c @@ -40,6 +40,8 @@ #define PHY_SLEWP_EN 0x1 #define PHY_SLEWN_EN 0x1 #define PHY_RX_CM_INPUT 0x1 +#define CS0_MR22_VAL 0 +#define CS1_MR22_VAL 3 #define CRU_SFTRST_DDR_CTRL(ch, n) ((0x1 << (8 + 16 + (ch) * 4)) | \ ((n) << (8 + (ch) * 4))) @@ -554,7 +556,7 @@ static void set_ds_odt(const struct chan_info *chan, const struct rk3399_sdram_params *params, u32 mr5) { u32 *denali_phy = chan->publ->denali_phy; - + u32 *denali_ctl = chan->pctl->denali_ctl; u32 tsel_idle_en, tsel_wr_en, tsel_rd_en; u32 tsel_idle_select_p, tsel_rd_select_p; u32 tsel_idle_select_n, tsel_rd_select_n; @@ -562,6 +564,7 @@ static void set_ds_odt(const struct chan_info *chan, u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n; u32 tsel_ckcs_select_p, tsel_ckcs_select_n; struct io_setting *io = NULL; + u32 soc_odt = 0; u32 reg_value; if (params->base.dramtype == LPDDR4) { @@ -581,6 +584,35 @@ static void set_ds_odt(const struct chan_info *chan, tsel_ckcs_select_p = io->wr_ckcs_drv; tsel_ckcs_select_n = PHY_DRV_ODT_34_3; + switch (tsel_rd_select_n) { + case PHY_DRV_ODT_240: + soc_odt = 1; + break; + case PHY_DRV_ODT_120: + soc_odt = 2; + break; + case PHY_DRV_ODT_80: + soc_odt = 3; + break; + case PHY_DRV_ODT_60: + soc_odt = 4; + break; + case PHY_DRV_ODT_48: + soc_odt = 5; + break; + case PHY_DRV_ODT_40: + soc_odt = 6; + break; + case PHY_DRV_ODT_34_3: + soc_odt = 6; + printf("%s: Unable to support LPDDR4 MR22 Soc ODT\n", + __func__); + break; + case PHY_DRV_ODT_HI_Z: + default: + soc_odt = 0; + break; + } } else if (params->base.dramtype == LPDDR3) { tsel_rd_select_p = PHY_DRV_ODT_240; tsel_rd_select_n = PHY_DRV_ODT_HI_Z; @@ -621,6 +653,21 @@ static void set_ds_odt(const struct chan_info *chan, tsel_wr_en = 0; tsel_idle_en = 0; + /* F0_0 */ + clrsetbits_le32(&denali_ctl[145], 0xFF << 16, + (soc_odt | (CS0_MR22_VAL << 3)) << 16); + /* F2_0, F1_0 */ + clrsetbits_le32(&denali_ctl[146], 0xFF00FF, + ((soc_odt | (CS0_MR22_VAL << 3)) << 16) | + (soc_odt | (CS0_MR22_VAL << 3))); + /* F0_1 */ + clrsetbits_le32(&denali_ctl[159], 0xFF << 16, + (soc_odt | (CS1_MR22_VAL << 3)) << 16); + /* F2_1, F1_1 */ + clrsetbits_le32(&denali_ctl[160], 0xFF00FF, + ((soc_odt | (CS1_MR22_VAL << 3)) << 16) | + (soc_odt | (CS1_MR22_VAL << 3))); + /* * phy_dq_tsel_select_X 24bits DENALI_PHY_6/134/262/390 offset_0 * sets termination values for read/idle cycles and drive strength