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{ "id": 818623, "url": "http://patchwork.ozlabs.org/api/covers/818623/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/1506428644-2996-1-git-send-email-absahu@codeaurora.org/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1506428644-2996-1-git-send-email-absahu@codeaurora.org>", "list_archive_url": null, "date": "2017-09-26T12:23:53", "name": "[00/11] Add remaining clocks for QCOM IPQ8074", "submitter": { "id": 68957, "url": "http://patchwork.ozlabs.org/api/people/68957/?format=api", "name": "Abhishek Sahu", "email": "absahu@codeaurora.org" }, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/1506428644-2996-1-git-send-email-absahu@codeaurora.org/mbox/", "series": [ { "id": 5127, "url": "http://patchwork.ozlabs.org/api/series/5127/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=5127", "date": "2017-09-26T12:23:53", "name": "Add remaining clocks for QCOM IPQ8074", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/5127/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/818623/comments/", "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org header.i=@codeaurora.org\n\theader.b=\"lUGAnlH+\"; \n\tdkim=fail reason=\"signature verification failed\" (1024-bit key)\n\theader.d=codeaurora.org header.i=@codeaurora.org header.b=\"fBn+XP8F\"; \n\tdkim-atps=neutral", "pdx-caf-mail.web.codeaurora.org;\n\tdmarc=none (p=none dis=none) header.from=codeaurora.org", "pdx-caf-mail.web.codeaurora.org;\n\tspf=none smtp.mailfrom=absahu@codeaurora.org" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1gFN0ffjz9ryk\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tTue, 26 Sep 2017 22:27:20 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S936200AbdIZMYS (ORCPT <rfc822; incoming-dt@patchwork.ozlabs.org>);\n\tTue, 26 Sep 2017 08:24:18 -0400", "from smtp.codeaurora.org ([198.145.29.96]:53456 \"EHLO\n\tsmtp.codeaurora.org\" rhost-flags-OK-OK-OK-OK) by vger.kernel.org\n\twith ESMTP id S935503AbdIZMYQ (ORCPT\n\t<rfc822; devicetree@vger.kernel.org>); Tue, 26 Sep 2017 08:24:16 -0400", "by smtp.codeaurora.org (Postfix, from userid 1000)\n\tid A072860A36; Tue, 26 Sep 2017 12:24:14 +0000 (UTC)", "from absahu-linux.qualcomm.com\n\t(blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com\n\t[103.229.19.19])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits))\n\t(No client certificate requested)\n\t(Authenticated sender: absahu@smtp.codeaurora.org)\n\tby smtp.codeaurora.org (Postfix) with ESMTPSA id 3FFEB60246;\n\tTue, 26 Sep 2017 12:24:09 +0000 (UTC)" ], "DKIM-Signature": [ "v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506428656;\n\tbh=Ams0wiM2TA5mx+KFNrtoCSs44lPDvRaAVNOm+AOVWRA=;\n\th=From:To:Cc:Subject:Date:From;\n\tb=lUGAnlH+DPPZSVlPcOEhIoWk/XQ1+0xZUkmMvZaNbTtwRp2NaxVtJ0K56RgQGUd2U\n\t3lbSd0zj4DVBpRVq2XmDtf40fAAbqBNKYt8gneVbxzG7kHcNXaPSoWIqZXSxJ+u3OG\n\tnfGgDYtAka3LEVfwCJgRtYGMrTMlrLum2vs/tXGw=", "v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org;\n\ts=default; t=1506428653;\n\tbh=Ams0wiM2TA5mx+KFNrtoCSs44lPDvRaAVNOm+AOVWRA=;\n\th=From:To:Cc:Subject:Date:From;\n\tb=fBn+XP8FHBC91zBtxiHwLFRXSkW048I5VFgv1J0OrUOkii5a8sNigP3MzR6pWuEXD\n\tXCaX0b3W92UdVAg588kchDma26CUPTx2gs7rXyXHF9IUzbhG1X6pEu+ZDf+LJ5VSFq\n\t96ii1ookGBEbplz46hEZRHBmRzf64vX7D0y7KAPA=" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on\n\tpdx-caf-mail.web.codeaurora.org", "X-Spam-Level": "", "X-Spam-Status": "No, score=-2.8 required=2.0 tests=ALL_TRUSTED,BAYES_00,\n\tDKIM_SIGNED,\n\tT_DKIM_INVALID autolearn=no autolearn_force=no version=3.4.0", "DMARC-Filter": "OpenDMARC Filter v1.3.2 smtp.codeaurora.org 3FFEB60246", "From": "Abhishek Sahu <absahu@codeaurora.org>", "To": "Stephen Boyd <sboyd@codeaurora.org>,\n\tMichael Turquette <mturquette@baylibre.com>,\n\tRob Herring <robh+dt@kernel.org>", "Cc": "Andy Gross <andy.gross@linaro.org>, David Brown <david.brown@linaro.org>,\n\tlinux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tAbhishek Sahu <absahu@codeaurora.org>,\n\tMark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org", "Subject": "[PATCH 00/11] Add remaining clocks for QCOM IPQ8074", "Date": "Tue, 26 Sep 2017 17:53:53 +0530", "Message-Id": "<1506428644-2996-1-git-send-email-absahu@codeaurora.org>", "X-Mailer": "git-send-email 1.9.1", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=UTF-8", "Content-Transfer-Encoding": "8bit", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "This patch series adds following IPQ8074 clocks\n\n- Remaining General PLL’s, NSS UBI PLL and NSS Crypto PLL.\n- 2 instances of PCIE, USB, SDCC.\n- 2 NSS UBI core and common NSS clocks. NSS is network.\n switching subsystem which accelerates the ethernet traffic.\n IPQ8074 has two UBI cores and each core uses some separate\n core clocks and remaining common clocks.\n- NSS Crypto Engine clocks\n- NSS ethernet port clocks. IPQ8074 has 6 Ethernet ports and each\n port uses different clocks\n- Crypto engine clocks\n- PCIE and NSS MISC resets.\n\nAbhishek Sahu (11):\n clk: qcom: add read-only divider operations\n clk: qcom: add parent map for regmap mux\n clk: qcom: ipq8074: fix missing GPLL0 divider width\n dt-bindings: clock: qcom: add remaining clocks for IPQ8074\n clk: qcom: ipq8074: add remaining PLL’s\n clk: qcom: ipq8074: add PCIE, USB and SDCC clocks\n clk: qcom: ipq8074: add NSS clocks\n clk: qcom: ipq8074: add NSS ethernet port clocks\n clk: qcom: ipq8074: add GP and Crypto clocks\n dt-bindings: clock: qcom: add misc resets for PCIE and NSS\n clk: qcom: ipq8074: add misc resets for PCIE and NSS\n\n drivers/clk/qcom/clk-rcg.h | 10 -\n drivers/clk/qcom/clk-regmap-divider.c | 29 +\n drivers/clk/qcom/clk-regmap-divider.h | 1 +\n drivers/clk/qcom/clk-regmap-mux.c | 6 +\n drivers/clk/qcom/clk-regmap-mux.h | 2 +\n drivers/clk/qcom/common.h | 11 +-\n drivers/clk/qcom/gcc-ipq8074.c | 3736 ++++++++++++++++++++++++++\n include/dt-bindings/clock/qcom,gcc-ipq8074.h | 222 ++\n 8 files changed, 4006 insertions(+), 11 deletions(-)" }