[{"id":1811509,"web_url":"http://patchwork.ozlabs.org/comment/1811509/","msgid":"<8db28dda018f43ac3038d33f1020eb57@codeaurora.org>","list_archive_url":null,"date":"2017-11-28T15:24:33","subject":"Re: [PATCH 04/11] dt-bindings: clock: qcom: add remaining clocks for\n\tIPQ8074","submitter":{"id":68957,"url":"http://patchwork.ozlabs.org/api/people/68957/","name":"Abhishek Sahu","email":"absahu@codeaurora.org"},"content":"On 2017-09-26 17:53, Abhishek Sahu wrote:\n> This patch adds the DT bindings for following IPQ8074 clocks\n> \n> - General PLL’s, NSS UBI PLL and NSS Crypto PLL.\n> - 2 instances of PCIE, USB, SDCC.\n> - 2 NSS UBI core and common NSS clocks. NSS is network switching\n> system which accelerates the ethernet traffic. IPQ8074\n> NSS has two UBI cores. Some clocks are separate for each UBI core\n> and remaining NSS clocks are common.\n> - NSS ethernet port clocks. IPQ8074 has 6 ethernet ports and\n> each port uses different TX and RX clocks.\n> - Crypto engine clocks.\n> - General purpose clocks which comes over GPIO.\n> \n\nHi Rob,\n\nCould you please review this DT bindings change and give\nyour Acked-by if its OK.\n\nThanks,\nAbhishek\n\n> Signed-off-by: Abhishek Sahu \n> ---\n> include/dt-bindings/clock/qcom,gcc-ipq8074.h | 180 \n> +++++++++++++++++++++++++++\n> 1 file changed, 180 insertions(+)\n> \n> diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h\n> b/include/dt-bindings/clock/qcom,gcc-ipq8074.h\n> index 370c83c..ff0b4ac 100644\n> --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h\n> +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h\n> @@ -58,6 +58,186 @@\n> #define GCC_QPIC_AHB_CLK\t\t\t41\n> #define GCC_QPIC_CLK\t\t\t\t42\n> #define PCNOC_BFDCD_CLK_SRC\t\t\t43\n> +#define GPLL2_MAIN\t\t\t\t44\n> +#define GPLL2\t\t\t\t\t45\n> +#define GPLL4_MAIN\t\t\t\t46\n> +#define GPLL4\t\t\t\t\t47\n> +#define GPLL6_MAIN\t\t\t\t48\n> +#define GPLL6\t\t\t\t\t49\n> +#define UBI32_PLL_MAIN\t\t\t\t50\n> +#define UBI32_PLL\t\t\t\t51\n> +#define NSS_CRYPTO_PLL_MAIN\t\t\t52\n> +#define NSS_CRYPTO_PLL\t\t\t\t53\n> +#define PCIE0_AXI_CLK_SRC\t\t\t54\n> +#define PCIE0_AUX_CLK_SRC\t\t\t55\n> +#define PCIE0_PIPE_CLK_SRC\t\t\t56\n> +#define PCIE1_AXI_CLK_SRC\t\t\t57\n> +#define PCIE1_AUX_CLK_SRC\t\t\t58\n> +#define PCIE1_PIPE_CLK_SRC\t\t\t59\n> +#define SDCC1_APPS_CLK_SRC\t\t\t60\n> +#define SDCC1_ICE_CORE_CLK_SRC\t\t\t61\n> +#define SDCC2_APPS_CLK_SRC\t\t\t62\n> +#define USB0_MASTER_CLK_SRC\t\t\t63\n> +#define USB0_AUX_CLK_SRC\t\t\t64\n> +#define USB0_MOCK_UTMI_CLK_SRC\t\t\t65\n> +#define USB0_PIPE_CLK_SRC\t\t\t66\n> +#define USB1_MASTER_CLK_SRC\t\t\t67\n> +#define USB1_AUX_CLK_SRC\t\t\t68\n> +#define USB1_MOCK_UTMI_CLK_SRC\t\t\t69\n> +#define USB1_PIPE_CLK_SRC\t\t\t70\n> +#define GCC_XO_CLK_SRC\t\t\t\t71\n> +#define SYSTEM_NOC_BFDCD_CLK_SRC\t\t72\n> +#define NSS_CE_CLK_SRC\t\t\t\t73\n> +#define NSS_NOC_BFDCD_CLK_SRC\t\t\t74\n> +#define NSS_CRYPTO_CLK_SRC\t\t\t75\n> +#define NSS_UBI0_CLK_SRC\t\t\t76\n> +#define NSS_UBI0_DIV_CLK_SRC\t\t\t77\n> +#define NSS_UBI1_CLK_SRC\t\t\t78\n> +#define NSS_UBI1_DIV_CLK_SRC\t\t\t79\n> +#define UBI_MPT_CLK_SRC\t\t\t\t80\n> +#define NSS_IMEM_CLK_SRC\t\t\t81\n> +#define NSS_PPE_CLK_SRC\t\t\t\t82\n> +#define NSS_PORT1_RX_CLK_SRC\t\t\t83\n> +#define NSS_PORT1_RX_DIV_CLK_SRC\t\t84\n> +#define NSS_PORT1_TX_CLK_SRC\t\t\t85\n> +#define NSS_PORT1_TX_DIV_CLK_SRC\t\t86\n> +#define NSS_PORT2_RX_CLK_SRC\t\t\t87\n> +#define NSS_PORT2_RX_DIV_CLK_SRC\t\t88\n> +#define NSS_PORT2_TX_CLK_SRC\t\t\t89\n> +#define NSS_PORT2_TX_DIV_CLK_SRC\t\t90\n> +#define NSS_PORT3_RX_CLK_SRC\t\t\t91\n> +#define NSS_PORT3_RX_DIV_CLK_SRC\t\t92\n> +#define NSS_PORT3_TX_CLK_SRC\t\t\t93\n> +#define NSS_PORT3_TX_DIV_CLK_SRC\t\t94\n> +#define NSS_PORT4_RX_CLK_SRC\t\t\t95\n> +#define NSS_PORT4_RX_DIV_CLK_SRC\t\t96\n> +#define NSS_PORT4_TX_CLK_SRC\t\t\t97\n> +#define NSS_PORT4_TX_DIV_CLK_SRC\t\t98\n> +#define NSS_PORT5_RX_CLK_SRC\t\t\t99\n> +#define NSS_PORT5_RX_DIV_CLK_SRC\t\t100\n> +#define NSS_PORT5_TX_CLK_SRC\t\t\t101\n> +#define NSS_PORT5_TX_DIV_CLK_SRC\t\t102\n> +#define NSS_PORT6_RX_CLK_SRC\t\t\t103\n> +#define NSS_PORT6_RX_DIV_CLK_SRC\t\t104\n> +#define NSS_PORT6_TX_CLK_SRC\t\t\t105\n> +#define NSS_PORT6_TX_DIV_CLK_SRC\t\t106\n> +#define CRYPTO_CLK_SRC\t\t\t\t107\n> +#define GP1_CLK_SRC\t\t\t\t108\n> +#define GP2_CLK_SRC\t\t\t\t109\n> +#define GP3_CLK_SRC\t\t\t\t110\n> +#define GCC_PCIE0_AHB_CLK\t\t\t111\n> +#define GCC_PCIE0_AUX_CLK\t\t\t112\n> +#define GCC_PCIE0_AXI_M_CLK\t\t\t113\n> +#define GCC_PCIE0_AXI_S_CLK\t\t\t114\n> +#define GCC_PCIE0_PIPE_CLK\t\t\t115\n> +#define GCC_SYS_NOC_PCIE0_AXI_CLK\t\t116\n> +#define GCC_PCIE1_AHB_CLK\t\t\t117\n> +#define GCC_PCIE1_AUX_CLK\t\t\t118\n> +#define GCC_PCIE1_AXI_M_CLK\t\t\t119\n> +#define GCC_PCIE1_AXI_S_CLK\t\t\t120\n> +#define GCC_PCIE1_PIPE_CLK\t\t\t121\n> +#define GCC_SYS_NOC_PCIE1_AXI_CLK\t\t122\n> +#define GCC_USB0_AUX_CLK\t\t\t123\n> +#define GCC_SYS_NOC_USB0_AXI_CLK\t\t124\n> +#define GCC_USB0_MASTER_CLK\t\t\t125\n> +#define GCC_USB0_MOCK_UTMI_CLK\t\t\t126\n> +#define GCC_USB0_PHY_CFG_AHB_CLK\t\t127\n> +#define GCC_USB0_PIPE_CLK\t\t\t128\n> +#define GCC_USB0_SLEEP_CLK\t\t\t129\n> +#define GCC_USB1_AUX_CLK\t\t\t130\n> +#define GCC_SYS_NOC_USB1_AXI_CLK\t\t131\n> +#define GCC_USB1_MASTER_CLK\t\t\t132\n> +#define GCC_USB1_MOCK_UTMI_CLK\t\t\t133\n> +#define GCC_USB1_PHY_CFG_AHB_CLK\t\t134\n> +#define GCC_USB1_PIPE_CLK\t\t\t135\n> +#define GCC_USB1_SLEEP_CLK\t\t\t136\n> +#define GCC_SDCC1_AHB_CLK\t\t\t137\n> +#define GCC_SDCC1_APPS_CLK\t\t\t138\n> +#define GCC_SDCC1_ICE_CORE_CLK\t\t\t139\n> +#define GCC_SDCC2_AHB_CLK\t\t\t140\n> +#define GCC_SDCC2_APPS_CLK\t\t\t141\n> +#define GCC_MEM_NOC_NSS_AXI_CLK\t\t\t142\n> +#define GCC_NSS_CE_APB_CLK\t\t\t143\n> +#define GCC_NSS_CE_AXI_CLK\t\t\t144\n> +#define GCC_NSS_CFG_CLK\t\t\t\t145\n> +#define GCC_NSS_CRYPTO_CLK\t\t\t146\n> +#define GCC_NSS_CSR_CLK\t\t\t\t147\n> +#define GCC_NSS_EDMA_CFG_CLK\t\t\t148\n> +#define GCC_NSS_EDMA_CLK\t\t\t149\n> +#define GCC_NSS_IMEM_CLK\t\t\t150\n> +#define GCC_NSS_NOC_CLK\t\t\t\t151\n> +#define GCC_NSS_PPE_BTQ_CLK\t\t\t152\n> +#define GCC_NSS_PPE_CFG_CLK\t\t\t153\n> +#define GCC_NSS_PPE_CLK\t\t\t\t154\n> +#define GCC_NSS_PPE_IPE_CLK\t\t\t155\n> +#define GCC_NSS_PTP_REF_CLK\t\t\t156\n> +#define GCC_NSSNOC_CE_APB_CLK\t\t\t157\n> +#define GCC_NSSNOC_CE_AXI_CLK\t\t\t158\n> +#define GCC_NSSNOC_CRYPTO_CLK\t\t\t159\n> +#define GCC_NSSNOC_PPE_CFG_CLK\t\t\t160\n> +#define GCC_NSSNOC_PPE_CLK\t\t\t161\n> +#define GCC_NSSNOC_QOSGEN_REF_CLK\t\t162\n> +#define GCC_NSSNOC_SNOC_CLK\t\t\t163\n> +#define GCC_NSSNOC_TIMEOUT_REF_CLK\t\t164\n> +#define GCC_NSSNOC_UBI0_AHB_CLK\t\t\t165\n> +#define GCC_NSSNOC_UBI1_AHB_CLK\t\t\t166\n> +#define GCC_UBI0_AHB_CLK\t\t\t167\n> +#define GCC_UBI0_AXI_CLK\t\t\t168\n> +#define GCC_UBI0_NC_AXI_CLK\t\t\t169\n> +#define GCC_UBI0_CORE_CLK\t\t\t170\n> +#define GCC_UBI0_MPT_CLK\t\t\t171\n> +#define GCC_UBI1_AHB_CLK\t\t\t172\n> +#define GCC_UBI1_AXI_CLK\t\t\t173\n> +#define GCC_UBI1_NC_AXI_CLK\t\t\t174\n> +#define GCC_UBI1_CORE_CLK\t\t\t175\n> +#define GCC_UBI1_MPT_CLK\t\t\t176\n> +#define GCC_CMN_12GPLL_AHB_CLK\t\t\t177\n> +#define GCC_CMN_12GPLL_SYS_CLK\t\t\t178\n> +#define GCC_MDIO_AHB_CLK\t\t\t179\n> +#define GCC_UNIPHY0_AHB_CLK\t\t\t180\n> +#define GCC_UNIPHY0_SYS_CLK\t\t\t181\n> +#define GCC_UNIPHY1_AHB_CLK\t\t\t182\n> +#define GCC_UNIPHY1_SYS_CLK\t\t\t183\n> +#define GCC_UNIPHY2_AHB_CLK\t\t\t184\n> +#define GCC_UNIPHY2_SYS_CLK\t\t\t185\n> +#define GCC_NSS_PORT1_RX_CLK\t\t\t186\n> +#define GCC_NSS_PORT1_TX_CLK\t\t\t187\n> +#define GCC_NSS_PORT2_RX_CLK\t\t\t188\n> +#define GCC_NSS_PORT2_TX_CLK\t\t\t189\n> +#define GCC_NSS_PORT3_RX_CLK\t\t\t190\n> +#define GCC_NSS_PORT3_TX_CLK\t\t\t191\n> +#define GCC_NSS_PORT4_RX_CLK\t\t\t192\n> +#define GCC_NSS_PORT4_TX_CLK\t\t\t193\n> +#define GCC_NSS_PORT5_RX_CLK\t\t\t194\n> +#define GCC_NSS_PORT5_TX_CLK\t\t\t195\n> +#define GCC_NSS_PORT6_RX_CLK\t\t\t196\n> +#define GCC_NSS_PORT6_TX_CLK\t\t\t197\n> +#define GCC_PORT1_MAC_CLK\t\t\t198\n> +#define GCC_PORT2_MAC_CLK\t\t\t199\n> +#define GCC_PORT3_MAC_CLK\t\t\t200\n> +#define GCC_PORT4_MAC_CLK\t\t\t201\n> +#define GCC_PORT5_MAC_CLK\t\t\t202\n> +#define GCC_PORT6_MAC_CLK\t\t\t203\n> +#define GCC_UNIPHY0_PORT1_RX_CLK\t\t204\n> +#define GCC_UNIPHY0_PORT1_TX_CLK\t\t205\n> +#define GCC_UNIPHY0_PORT2_RX_CLK\t\t206\n> +#define GCC_UNIPHY0_PORT2_TX_CLK\t\t207\n> +#define GCC_UNIPHY0_PORT3_RX_CLK\t\t208\n> +#define GCC_UNIPHY0_PORT3_TX_CLK\t\t209\n> +#define GCC_UNIPHY0_PORT4_RX_CLK\t\t210\n> +#define GCC_UNIPHY0_PORT4_TX_CLK\t\t211\n> +#define GCC_UNIPHY0_PORT5_RX_CLK\t\t212\n> +#define GCC_UNIPHY0_PORT5_TX_CLK\t\t213\n> +#define GCC_UNIPHY1_PORT5_RX_CLK\t\t214\n> +#define GCC_UNIPHY1_PORT5_TX_CLK\t\t215\n> +#define GCC_UNIPHY2_PORT6_RX_CLK\t\t216\n> +#define GCC_UNIPHY2_PORT6_TX_CLK\t\t217\n> +#define GCC_CRYPTO_AHB_CLK\t\t\t218\n> +#define GCC_CRYPTO_AXI_CLK\t\t\t219\n> +#define GCC_CRYPTO_CLK\t\t\t\t220\n> +#define GCC_GP1_CLK\t\t\t\t221\n> +#define GCC_GP2_CLK\t\t\t\t222\n> +#define GCC_GP3_CLK\t\t\t\t223\n> \n> #define GCC_BLSP1_BCR\t\t\t\t0\n> #define GCC_BLSP1_QUP1_BCR\t\t\t1\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=codeaurora.org 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T_DKIM_INVALID,\n\tUPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8;\n format=flowed","Content-Transfer-Encoding":"8bit","Date":"Tue, 28 Nov 2017 20:54:33 +0530","From":"Abhishek Sahu ","To":"Stephen Boyd ,\n\tMichael Turquette ,\n\tRob Herring ","Cc":"Andy Gross , David Brown ,\n\tlinux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tMark Rutland , devicetree@vger.kernel.org","Subject":"Re: [PATCH 04/11] dt-bindings: clock: qcom: add remaining clocks for\n\tIPQ8074","In-Reply-To":"<1506428644-2996-5-git-send-email-absahu@codeaurora.org>","References":"<1506428644-2996-1-git-send-email-absahu@codeaurora.org>\n\t<1506428644-2996-5-git-send-email-absahu@codeaurora.org>","Message-ID":"<8db28dda018f43ac3038d33f1020eb57@codeaurora.org>","X-Sender":"absahu@codeaurora.org","User-Agent":"Roundcube Webmail/1.2.5","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1811511,"web_url":"http://patchwork.ozlabs.org/comment/1811511/","msgid":"","list_archive_url":null,"date":"2017-11-28T15:25:29","subject":"Re: [PATCH 10/11] dt-bindings: clock: qcom: add misc resets for PCIE\n\tand NSS","submitter":{"id":68957,"url":"http://patchwork.ozlabs.org/api/people/68957/","name":"Abhishek Sahu","email":"absahu@codeaurora.org"},"content":"On 2017-09-26 17:54, Abhishek Sahu wrote:\n> PCIE and NSS has MISC reset register in which single register has\n> multiple reset bit. The patch adds the DT bindings for these MISC\n> resets.\n> \n> Signed-off-by: Abhishek Sahu \n\nHi Rob,\n\nCould you please review this DT bindings change and give\nyour Acked-by if its OK.\n\nThanks,\nAbhishek\n\n> ---\n> include/dt-bindings/clock/qcom,gcc-ipq8074.h | 42 \n> ++++++++++++++++++++++++++++\n> 1 file changed, 42 insertions(+)\n> \n> diff --git a/include/dt-bindings/clock/qcom,gcc-ipq8074.h\n> b/include/dt-bindings/clock/qcom,gcc-ipq8074.h\n> index ff0b4ac..238f872 100644\n> --- a/include/dt-bindings/clock/qcom,gcc-ipq8074.h\n> +++ b/include/dt-bindings/clock/qcom,gcc-ipq8074.h\n> @@ -328,5 +328,47 @@\n> #define GCC_APC0_VOLTAGE_DROOP_DETECTOR_BCR\t86\n> #define GCC_APC1_VOLTAGE_DROOP_DETECTOR_BCR\t87\n> #define GCC_SMMU_CATS_BCR\t\t\t88\n> +#define GCC_UBI0_AXI_ARES\t\t\t89\n> +#define GCC_UBI0_AHB_ARES\t\t\t90\n> +#define GCC_UBI0_NC_AXI_ARES\t\t\t91\n> +#define GCC_UBI0_DBG_ARES\t\t\t92\n> +#define GCC_UBI0_CORE_CLAMP_ENABLE\t\t93\n> +#define GCC_UBI0_CLKRST_CLAMP_ENABLE\t\t94\n> +#define GCC_UBI1_AXI_ARES\t\t\t95\n> +#define GCC_UBI1_AHB_ARES\t\t\t96\n> +#define GCC_UBI1_NC_AXI_ARES\t\t\t97\n> +#define GCC_UBI1_DBG_ARES\t\t\t98\n> +#define GCC_UBI1_CORE_CLAMP_ENABLE\t\t99\n> +#define GCC_UBI1_CLKRST_CLAMP_ENABLE\t\t100\n> +#define GCC_NSS_CFG_ARES\t\t\t101\n> +#define GCC_NSS_IMEM_ARES\t\t\t102\n> +#define GCC_NSS_NOC_ARES\t\t\t103\n> +#define GCC_NSS_CRYPTO_ARES\t\t\t104\n> +#define GCC_NSS_CSR_ARES\t\t\t105\n> +#define GCC_NSS_CE_APB_ARES\t\t\t106\n> +#define GCC_NSS_CE_AXI_ARES\t\t\t107\n> +#define GCC_NSSNOC_CE_APB_ARES\t\t\t108\n> +#define GCC_NSSNOC_CE_AXI_ARES\t\t\t109\n> +#define GCC_NSSNOC_UBI0_AHB_ARES\t\t110\n> +#define GCC_NSSNOC_UBI1_AHB_ARES\t\t111\n> +#define GCC_NSSNOC_SNOC_ARES\t\t\t112\n> +#define GCC_NSSNOC_CRYPTO_ARES\t\t\t113\n> +#define GCC_NSSNOC_ATB_ARES\t\t\t114\n> +#define GCC_NSSNOC_QOSGEN_REF_ARES\t\t115\n> +#define GCC_NSSNOC_TIMEOUT_REF_ARES\t\t116\n> +#define GCC_PCIE0_PIPE_ARES\t\t\t117\n> +#define GCC_PCIE0_SLEEP_ARES\t\t\t118\n> +#define GCC_PCIE0_CORE_STICKY_ARES\t\t119\n> +#define GCC_PCIE0_AXI_MASTER_ARES\t\t120\n> +#define GCC_PCIE0_AXI_SLAVE_ARES\t\t121\n> +#define GCC_PCIE0_AHB_ARES\t\t\t122\n> +#define GCC_PCIE0_AXI_MASTER_STICKY_ARES\t123\n> +#define GCC_PCIE1_PIPE_ARES\t\t\t124\n> +#define GCC_PCIE1_SLEEP_ARES\t\t\t125\n> +#define GCC_PCIE1_CORE_STICKY_ARES\t\t126\n> +#define GCC_PCIE1_AXI_MASTER_ARES\t\t127\n> +#define GCC_PCIE1_AXI_SLAVE_ARES\t\t128\n> +#define GCC_PCIE1_AHB_ARES\t\t\t129\n> +#define GCC_PCIE1_AXI_MASTER_STICKY_ARES\t130\n> \n> #endif\n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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charset=US-ASCII;\n format=flowed","Content-Transfer-Encoding":"7bit","Date":"Tue, 28 Nov 2017 20:55:29 +0530","From":"Abhishek Sahu ","To":"Stephen Boyd ,\n\tMichael Turquette ,\n\tRob Herring ","Cc":"Andy Gross , David Brown ,\n\tlinux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org,\n\tlinux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tMark Rutland , devicetree@vger.kernel.org","Subject":"Re: [PATCH 10/11] dt-bindings: clock: qcom: add misc resets for PCIE\n\tand NSS","In-Reply-To":"<1506428644-2996-11-git-send-email-absahu@codeaurora.org>","References":"<1506428644-2996-1-git-send-email-absahu@codeaurora.org>\n\t<1506428644-2996-11-git-send-email-absahu@codeaurora.org>","Message-ID":"","X-Sender":"absahu@codeaurora.org","User-Agent":"Roundcube Webmail/1.2.5","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]