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{ "id": 813815, "url": "http://patchwork.ozlabs.org/api/covers/813815/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/cover/20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com/", "project": { "id": 19, "url": "http://patchwork.ozlabs.org/api/projects/19/?format=api", "name": "Linux IMX development", "link_name": "linux-imx", "list_id": "linux-imx-kernel.lists.patchwork.ozlabs.org", "list_email": "linux-imx-kernel@lists.patchwork.ozlabs.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com>", "list_archive_url": null, "date": "2017-09-14T12:57:51", "name": "[v7,0/5] iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI)", "submitter": { "id": 70507, "url": "http://patchwork.ozlabs.org/api/people/70507/?format=api", "name": "Shameerali Kolothum Thodi", "email": "shameerali.kolothum.thodi@huawei.com" }, "mbox": "http://patchwork.ozlabs.org/project/linux-imx/cover/20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com/mbox/", "series": [ { "id": 3094, "url": "http://patchwork.ozlabs.org/api/series/3094/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-imx/list/?series=3094", "date": "2017-09-14T12:57:51", "name": "iommu/smmu-v3: Workaround for hisilicon 161010801 erratum(reserve HW MSI)", "version": 7, "mbox": "http://patchwork.ozlabs.org/series/3094/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/813815/comments/", "headers": { "Return-Path": "<linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org>", "X-Original-To": "incoming-imx@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-imx@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"Ct64cwP/\"; dkim-atps=neutral" ], "Received": [ "from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xtJbz4MJnz9sPt\n\tfor <incoming-imx@patchwork.ozlabs.org>;\n\tThu, 14 Sep 2017 23:02:55 +1000 (AEST)", "from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dsTn8-0002J9-DA; Thu, 14 Sep 2017 13:02:50 +0000", "from szxga05-in.huawei.com ([45.249.212.191])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dsTlh-0000sg-E3 for linux-arm-kernel@lists.infradead.org;\n\tThu, 14 Sep 2017 13:01:37 +0000", "from 172.30.72.58 (EHLO DGGEMS413-HUB.china.huawei.com)\n\t([172.30.72.58])\n\tby dggrg05-dlp.huawei.com (MOS 4.4.6-GA FastPath queued)\n\twith ESMTP id DHH33779; Thu, 14 Sep 2017 21:00:40 +0800 (CST)", "from S00345302A-PC.china.huawei.com (10.212.247.163) by\n\tDGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP\n\tServer id 14.3.301.0; Thu, 14 Sep 2017 21:00:30 +0800" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:To\n\t:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From:\n\tResent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:\n\tList-Owner; bh=mGu1f0VohcjMAoyD3Wfu26t7IT0mzL6DxEoBqK31dIg=;\n\tb=Ct64cwP/k4qtRz\n\t9gpxPC78XxIfMjnWVLlObEunLxw/3TWY2QYc5aitNUtlxSynGnFpq6ZSCxb/3N89V1h66kF97q6PZ\n\tdHdaTHhodmyHpNVkBvvog/ksisNuPBUozyxHTGKMv9cmkUR5uhWxvFRmqhXLrS2CgYLL1m7OGQH+a\n\tO4xP3OZN9f8aioLleFZaph64hCVkwzTdcrf5R2BgtEK1DSMILqJCxihJpovX1sDwgOW/RReQGlW44\n\tZYWHxWpQFkQXBKUKtoF48EXeDXvPmZwFBcuRGUmVqpBTGU7OmA1x+S2FKvIShzpKHgPBfCRP4R8pK\n\tmkuDwdRNnHhqzFEeXaeQ==;", "From": "Shameer Kolothum <shameerali.kolothum.thodi@huawei.com>", "To": "<lorenzo.pieralisi@arm.com>, <marc.zyngier@arm.com>,\n\t<sudeep.holla@arm.com>, <will.deacon@arm.com>, <robin.murphy@arm.com>,\n\t<joro@8bytes.org>, <mark.rutland@arm.com>, <hanjun.guo@linaro.org>", "Subject": "[PATCH v7 0/5] iommu/smmu-v3: Workaround for hisilicon 161010801\n\terratum(reserve HW MSI)", "Date": "Thu, 14 Sep 2017 13:57:51 +0100", "Message-ID": "<20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com>", "X-Mailer": "git-send-email 2.12.0.windows.1", "MIME-Version": "1.0", "X-Originating-IP": "[10.212.247.163]", "X-CFilter-Loop": "Reflected", "X-Mirapoint-Virus-RAPID-Raw": "score=unknown(0),\n\trefid=str=0001.0A090203.59BA7D79.003A, ss=1, re=0.000, recu=0.000,\n\treip=0.000, cl=1, cld=1, fgs=0, ip=0.0.0.0,\n\tso=2014-11-16 11:51:01, dmn=2013-03-21 17:37:32", "X-Mirapoint-Loop-Id": "b9f2301d5d55a745764a794f01ffd5e1", "X-CRM114-Version": "20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ", "X-CRM114-CacheID": "sfid-20170914_060122_265591_F5E1A30B ", "X-CRM114-Status": "GOOD ( 12.58 )", "X-Spam-Score": "-1.9 (-)", "X-Spam-Report": "SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-1.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]", "X-BeenThere": "linux-arm-kernel@lists.infradead.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Unsubscribe": "<http://lists.infradead.org/mailman/options/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=unsubscribe>", "List-Archive": "<http://lists.infradead.org/pipermail/linux-arm-kernel/>", "List-Post": "<mailto:linux-arm-kernel@lists.infradead.org>", "List-Help": "<mailto:linux-arm-kernel-request@lists.infradead.org?subject=help>", "List-Subscribe": "<http://lists.infradead.org/mailman/listinfo/linux-arm-kernel>,\n\t<mailto:linux-arm-kernel-request@lists.infradead.org?subject=subscribe>", "Cc": "devicetree@vger.kernel.org, gabriele.paoloni@huawei.com,\n\tjohn.garry@huawei.com, linuxarm@huawei.com,\n\tShameer Kolothum <shameerali.kolothum.thodi@huawei.com>,\n\tlinux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org,\n\twangzhou1@hisilicon.com, guohanjun@huawei.com,\n\tlinux-arm-kernel@lists.infradead.org, devel@acpica.org", "Content-Type": "text/plain; charset=\"us-ascii\"", "Content-Transfer-Encoding": "7bit", "Sender": "\"linux-arm-kernel\" <linux-arm-kernel-bounces@lists.infradead.org>", "Errors-To": "linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org", "List-Id": "linux-imx-kernel.lists.patchwork.ozlabs.org" }, "content": "On certain HiSilicon platforms (hip06/hip07) the GIC ITS and PCIe RC\ndeviates from the standard implementation and this breaks PCIe MSI\nfunctionality when SMMU is enabled.\n\nThe HiSilicon erratum 161010801 describes this limitation of certain\nHiSilicon platforms to support the SMMU mappings for MSI transactions.\nOn these platforms GICv3 ITS translator is presented with the deviceID\nby extending the MSI payload data to 64 bits to include the deviceID.\nHence, the PCIe controller on this platforms has to differentiate the MSI\npayload against other DMA payload and has to modify the MSI payload.\nThis basically makes it difficult for this platforms to have a SMMU\ntranslation for MSI.\n\nThis patch implements an ACPI and DT based quirk to reserve the hw msi\nregions in the smmu-v3 driver which means these address regions will\nnot be translated and will be excluded from iova allocations.\n\nTo implement this quirk, the following changes are incorporated:\n1. Added a generic helper function to IORT code to retrieve the\n associated ITS base address from a device IORT node.\n2. Added a generic helper function to of iommu code to retrieve the\n associated msi controller base address from for a PCI RC\n msi-mapping and also platform device msi-parent.\n3. Added quirk to SMMUv3 to retrieve the HW ITS address and replace\n the default SW MSI reserve address based on the IORT SMMU model\n or DT bindings.\n\nChangelog:\n\nv6 --> v7\nAddressed request from Will to add DT support for the erratum:\n - added bt binding\n - add of_iommu_msi_get_resv_regions()\nNew arm64 silicon errata entry\nRename iort_iommu_{its->msi}_get_resv_regions\n\nv5 --> v6\nAddressed comments from Robin and Lorenzo:\n-No change to patch#1 .\n-Reverted v5 patch#2 as this might break the platforms where this quirk\n is not applicable. Provided a generic function in iommu code and added\n back the quirk implementation in SMMU v3 driver(patch#3)\n \nv4 --> v5\nAddressed comments from Robin and Lorenzo:\n-Added a comment to make it clear that, for now, only straightforward \n HW topologies are handled while reserving ITS regions(patch #1).\n\nv3 --> v4\nRebased on 4.13-rc1.\nAddressed comments from Robin, Will and Lorenzo:\n-As suggested by Robin, moved the ITS msi reservation into \n iommu_dma_get_resv_regions().\n-Added its_count != resv region failure case(patch #1).\n\nv2 --> v3\nAddressed comments from Lorenzo and Robin:\n-Removed dev_is_pci() check in smmuV3 driver.\n-Don't treat device not having an ITS mapping as an error in\n iort helper function.\n\nv1 --> v2\n-patch 2/2: Invoke iort helper fn based on fwnode type(acpi).\n\nRFCv2 -->PATCH\n-Incorporated Lorenzo's review comments.\n\nRFC v1 --> RFC v2\nBased on Robin's review comments,\n-Removed the generic erratum framework.\n-Using IORT/MADT tables to retrieve the ITS base addr instead of vendor specific CSRT table.\n\nJohn Garry (2):\n Doc: iommu/arm-smmu-v3: Add workaround for HiSilicon erratum 161010801\n iommu/of: Add msi address regions reservation helper\n\nShameer Kolothum (3):\n ACPI/IORT: Add msi address regions reservation helper\n iommu/dma: Add a helper function to reserve HW MSI address regions for\n IOMMU drivers\n iommu/arm-smmu-v3:Enable ACPI based HiSilicon erratum 161010801\n\n Documentation/arm64/silicon-errata.txt | 1 +\n .../devicetree/bindings/iommu/arm,smmu-v3.txt | 3 +\n drivers/acpi/arm64/iort.c | 96 ++++++++++++++++-\n drivers/iommu/arm-smmu-v3.c | 28 ++++-\n drivers/iommu/dma-iommu.c | 19 ++++\n drivers/iommu/of_iommu.c | 117 +++++++++++++++++++++\n drivers/irqchip/irq-gic-v3-its.c | 3 +-\n include/linux/acpi_iort.h | 7 +-\n include/linux/dma-iommu.h | 7 ++\n include/linux/of_iommu.h | 10 ++\n 10 files changed, 281 insertions(+), 10 deletions(-)" }