[{"id":1771115,"web_url":"http://patchwork.ozlabs.org/comment/1771115/","msgid":"<20170919145314.2irmqpsfneeydupo@rob-hp-laptop>","list_archive_url":null,"date":"2017-09-19T14:53:14","subject":"Re: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n\tHiSilicon erratum 161010801","submitter":{"id":62529,"url":"http://patchwork.ozlabs.org/api/people/62529/","name":"Rob Herring (Arm)","email":"robh@kernel.org"},"content":"On Thu, Sep 14, 2017 at 01:57:52PM +0100, Shameer Kolothum wrote:\n> From: John Garry \n> \n> The HiSilicon erratum 161010801 describes the limitation of HiSilicon platforms\n> hip06/hip07 to support the SMMU mappings for MSI transactions.\n> \n> On these platforms, GICv3 ITS translator is presented with the deviceID\n> by extending the MSI payload data to 64 bits to include the deviceID.\n> Hence, the PCIe controller on this platforms has to differentiate the MSI\n> payload against other DMA payload and has to modify the MSI payload.\n> This basically makes it difficult for this platforms to have a SMMU\n> translation for MSI.\n> \n> This patch adds a SMMUv3 binding to flag that the SMMU breaks msi\n> translation at ITS.\n> \n> Also, the arm64 silicon errata is updated with this same erratum.\n> \n> Signed-off-by: John Garry \n> Signed-off-by: Shameer Kolothum \n> ---\n> Documentation/arm64/silicon-errata.txt | 1 +\n> Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt | 3 +++\n> 2 files changed, 4 insertions(+)\n> \n> diff --git a/Documentation/arm64/silicon-errata.txt b/Documentation/arm64/silicon-errata.txt\n> index 66e8ce1..02816b1 100644\n> --- a/Documentation/arm64/silicon-errata.txt\n> +++ b/Documentation/arm64/silicon-errata.txt\n> @@ -70,6 +70,7 @@ stable kernels.\n> | | | | |\n> | Hisilicon | Hip0{5,6,7} | #161010101 | HISILICON_ERRATUM_161010101 |\n> | Hisilicon | Hip0{6,7} | #161010701 | N/A |\n> +| Hisilicon | Hip0{6,7} | #161010801 | N/A |\n> | | | | |\n> | Qualcomm Tech. | Falkor v1 | E1003 | QCOM_FALKOR_ERRATUM_1003 |\n> | Qualcomm Tech. | Falkor v1 | E1009 | QCOM_FALKOR_ERRATUM_1009 |\n> diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n> index c9abbf3..1f5f7f9 100644\n> --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n> +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n> @@ -55,6 +55,9 @@ the PCIe specification.\n> - hisilicon,broken-prefetch-cmd\n> : Avoid sending CMD_PREFETCH_* commands to the SMMU.\n> \n> +- hisilicon,broken-untranslated-msi\n> + : Reserve ITS HW region to avoid translating msi.\n> +\n\nThis should be determined from the compatible string. Continuing to add \nproperties for each errata doesn't scale.\n\n> - cavium,cn9900-broken-page1-regspace\n> : Replaces all page 1 offsets used for EVTQ_PROD/CONS,\n> \t\t PRIQ_PROD/CONS register access with page 0 offsets.\n> -- \n> 1.9.1\n> \n> \n> --\n> To unsubscribe from this list: send the line \"unsubscribe devicetree\" in\n> the body of a message to majordomo@vger.kernel.org\n> More majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"EikZa3Qy\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxQqy703dz9sBZ\n\tfor ;\n\tWed, 20 Sep 2017 00:54:06 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duJuU-0005mJ-DO; Tue, 19 Sep 2017 14:54:02 +0000","from mail-it0-f68.google.com ([209.85.214.68])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duJu4-0005dN-Is for linux-arm-kernel@lists.infradead.org;\n\tTue, 19 Sep 2017 14:53:39 +0000","by mail-it0-f68.google.com with SMTP id g18so2547397itg.0\n\tfor ;\n\tTue, 19 Sep 2017 07:53:16 -0700 (PDT)","from localhost (rrcs-67-78-118-34.sw.biz.rr.com. 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charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1771183,"web_url":"http://patchwork.ozlabs.org/comment/1771183/","msgid":"<5FC3163CFD30C246ABAA99954A238FA838411AD3@FRAEML521-MBX.china.huawei.com>","list_archive_url":null,"date":"2017-09-19T16:09:33","subject":"RE: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n\tHiSilicon erratum 161010801","submitter":{"id":70507,"url":"http://patchwork.ozlabs.org/api/people/70507/","name":"Shameerali Kolothum Thodi","email":"shameerali.kolothum.thodi@huawei.com"},"content":"> -----Original Message-----\n> From: Rob Herring [mailto:robh@kernel.org]\n> Sent: Tuesday, September 19, 2017 3:53 PM\n> To: Shameerali Kolothum Thodi \n> Cc: lorenzo.pieralisi@arm.com; marc.zyngier@arm.com;\n> sudeep.holla@arm.com; will.deacon@arm.com; robin.murphy@arm.com;\n> joro@8bytes.org; mark.rutland@arm.com; hanjun.guo@linaro.org; Gabriele\n> Paoloni ; John Garry\n> ; iommu@lists.linux-foundation.org; linux-arm-\n> kernel@lists.infradead.org; linux-acpi@vger.kernel.org;\n> devicetree@vger.kernel.org; devel@acpica.org; Linuxarm\n> ; Wangzhou (B) ;\n> Guohanjun (Hanjun Guo) \n> Subject: Re: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n> HiSilicon erratum 161010801\n> \n> On Thu, Sep 14, 2017 at 01:57:52PM +0100, Shameer Kolothum wrote:\n> > From: John Garry \n> >\n> > The HiSilicon erratum 161010801 describes the limitation of HiSilicon\n> platforms\n> > hip06/hip07 to support the SMMU mappings for MSI transactions.\n> >\n> > On these platforms, GICv3 ITS translator is presented with the deviceID\n> > by extending the MSI payload data to 64 bits to include the deviceID.\n> > Hence, the PCIe controller on this platforms has to differentiate the MSI\n> > payload against other DMA payload and has to modify the MSI payload.\n> > This basically makes it difficult for this platforms to have a SMMU\n> > translation for MSI.\n> >\n> > This patch adds a SMMUv3 binding to flag that the SMMU breaks msi\n> > translation at ITS.\n> >\n> > Also, the arm64 silicon errata is updated with this same erratum.\n> >\n> > Signed-off-by: John Garry \n> > Signed-off-by: Shameer Kolothum\n> \n[...]\n> > --- a/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n> > +++ b/Documentation/devicetree/bindings/iommu/arm,smmu-v3.txt\n> > @@ -55,6 +55,9 @@ the PCIe specification.\n> > - hisilicon,broken-prefetch-cmd\n> > : Avoid sending CMD_PREFETCH_* commands to the SMMU.\n> >\n> > +- hisilicon,broken-untranslated-msi\n> > + : Reserve ITS HW region to avoid translating msi.\n> > +\n> \n> This should be determined from the compatible string. Continuing to add\n> properties for each errata doesn't scale.\n\nOk. I think the suggestion here is to follow the arm-smmu.c (SMMUv1/v2) \ndriver way of implementing the errata. As you might have noticed, the \nSMMUv3 driver dt errata framework depends on properties and this will\nchange the way errata is implemented in the driver now.\n\nHi Will/Robin,\nCould you please take a look and let us know your thoughts on changing\nthe SMMUv3 dt errata implementation to version/model/compatible string\nframework for this quirk.\n\nThanks,\nShameer","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"K4Hiii2w\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xxSXF4XGFz9sPk\n\tfor ;\n\tWed, 20 Sep 2017 02:10:37 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duL6W-0004FT-8K; Tue, 19 Sep 2017 16:10:32 +0000","from lhrrgout.huawei.com ([194.213.3.17])\n\tby bombadil.infradead.org with esmtps (Exim 4.87 #1 (Red Hat Linux))\n\tid 1duL6M-0002hp-Va for linux-arm-kernel@lists.infradead.org;\n\tTue, 19 Sep 2017 16:10:30 +0000","from 172.18.7.190 (EHLO lhreml704-cah.china.huawei.com)\n\t([172.18.7.190])\n\tby lhrrg01-dlp.huawei.com (MOS 4.3.7-GA FastPath queued)\n\twith ESMTP id DVU64325; Tue, 19 Sep 2017 16:09:49 +0000 (GMT)","from FRAEML702-CAH.china.huawei.com (10.206.14.33) by\n\tlhreml704-cah.china.huawei.com (10.201.108.45) with Microsoft SMTP\n\tServer (TLS) id 14.3.301.0; Tue, 19 Sep 2017 17:09:42 +0100","from FRAEML521-MBX.china.huawei.com ([169.254.1.161]) by\n\tfraeml702-cah.china.huawei.com ([10.206.14.33]) with mapi id\n\t14.03.0301.000; Tue, 19 Sep 2017 18:09:34 +0200"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:MIME-Version:In-Reply-To:References:\n\tMessage-ID:Date:Subject:To:From:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=AR6ntCwvpmSTVYSut1JI/ojr/uLealyIARFvzx3C8BM=;\n\tb=K4Hiii2wcSADK6\n\tAknzZZywbn7ZBXzJ2ddOSHeEoO2rHVPeXihHiIMVyGxtpPP/MFvSV2TRL3WEAMfG96w0niB/QCKKx\n\t2olQpKds+QbP/3CTs19QT4aXoUtKNhxfwi+xfyxy2ubbETStnkcIwB9aqdqse87imrFKyTahtTRd0\n\tnD4VLc49G7deiX4tjd9WMe/hFhkbbYHPA6bVRtBT6DRMsX90LXHwu+w+Hmw86YxbdB4Mu80/yYlHK\n\t7dyN6w/XkybZ1L5tjFmvYgFHRlCHAfIj+80cEQwhe0sf5S8xK1AV3BcCYwnyZP7HwC/nOt4jx1aHC\n\t1XMnVJ4lFx2r/2JopPiA==;","From":"Shameerali Kolothum Thodi ","To":"Rob Herring ","Subject":"RE: [PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n\tHiSilicon erratum 161010801","Thread-Topic":"[PATCH v7 1/5] Doc: iommu/arm-smmu-v3: Add workaround for\n\tHiSilicon erratum 161010801","Thread-Index":"AQHTLVl7i0VgSrSDgkWVkk8hYI0WSKK8MdAAgAAvcLA=","Date":"Tue, 19 Sep 2017 16:09:33 +0000","Message-ID":"<5FC3163CFD30C246ABAA99954A238FA838411AD3@FRAEML521-MBX.china.huawei.com>","References":"<20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com>\n\t<20170914125756.14836-2-shameerali.kolothum.thodi@huawei.com>\n\t<20170919145314.2irmqpsfneeydupo@rob-hp-laptop>","In-Reply-To":"<20170919145314.2irmqpsfneeydupo@rob-hp-laptop>","Accept-Language":"en-GB, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.203.177.212]","MIME-Version":"1.0","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020202.59C1414F.0053, ss=1, re=0.000, recu=0.000,\n\treip=0.000, \n\tcl=1, cld=1, fgs=0, ip=169.254.1.161,\n\tso=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"696153915bf86c269f6cf8efa13f28b4","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170919_091023_900687_0D05AD4C ","X-CRM114-Status":"GOOD ( 19.58 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [194.213.3.17 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[194.213.3.17 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"mark.rutland@arm.com\" ,\n\t\"devicetree@vger.kernel.org\" , \"Guohanjun\n\t\\(Hanjun Guo\\)\" ,\n\t\"lorenzo.pieralisi@arm.com\" ,\n\tGabriele Paoloni ,\n\t\"marc.zyngier@arm.com\" ,\n\t\"joro@8bytes.org\" , John Garry , \n\t\"will.deacon@arm.com\" ,\n\tLinuxarm , \n\t\"linux-acpi@vger.kernel.org\" ,\n\t\"iommu@lists.linux-foundation.org\" ,\n\t\"hanjun.guo@linaro.org\" ,\n\t\"Wangzhou \\(B\\)\" ,\n\t\"sudeep.holla@arm.com\" ,\n\t\"robin.murphy@arm.com\" ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t, \n\t\"devel@acpica.org\" ","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1773647,"web_url":"http://patchwork.ozlabs.org/comment/1773647/","msgid":"<20170922142758.GE3475@red-moon>","list_archive_url":null,"date":"2017-09-22T14:27:58","subject":"Re: [PATCH v7 3/5] iommu/of: Add msi address regions reservation\n\thelper","submitter":{"id":5388,"url":"http://patchwork.ozlabs.org/api/people/5388/","name":"Lorenzo Pieralisi","email":"Lorenzo.Pieralisi@arm.com"},"content":"John, Shameer,\n\nOn Thu, Sep 14, 2017 at 01:57:54PM +0100, Shameer Kolothum wrote:\n> From: John Garry \n> \n> On some platforms msi-controller address regions have to be excluded\n> from normal IOVA allocation in that they are detected and decoded in\n> a HW specific way by system components and so they cannot be considered\n> normal IOVA address space.\n> \n> Add a helper function that retrieves msi address regions through device\n> tree msi mapping, so that these regions will not be translated by IOMMU\n> and will be excluded from IOVA allocations.\n> \n> Signed-off-by: John Garry \n> Signed-off-by: Shameer Kolothum \n> ---\n> drivers/iommu/of_iommu.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++\n> include/linux/of_iommu.h | 10 ++++\n> 2 files changed, 127 insertions(+)\n> \n> diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c\n> index 8cb6082..f2d1a76 100644\n> --- a/drivers/iommu/of_iommu.c\n> +++ b/drivers/iommu/of_iommu.c\n> @@ -21,6 +21,7 @@\n> #include \n> #include \n> #include \n> +#include \n> #include \n> #include \n> #include \n> @@ -246,6 +247,122 @@ const struct iommu_ops *of_iommu_configure(struct device *dev,\n> \treturn ops;\n> }\n> \n> +/**\n> + * of_iommu_msi_get_resv_regions - Reserved region driver helper\n> + * @dev: Device from iommu_get_resv_regions()\n> + * @list: Reserved region list from iommu_get_resv_regions()\n> + *\n> + * Returns: Number of reserved regions on success (0 if no associated\n> + * msi parent), appropriate error value otherwise.\n> + */\n> +int of_iommu_msi_get_resv_regions(struct device *dev, struct list_head *head)\n> +{\n> +\tint prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;\n> +\tstruct iommu_resv_region *region;\n> +\tstruct device_node *np;\n> +\tstruct resource res;\n> +\tint i, resv = 0, mappings = 0;\n> +\n> +\tif (dev_is_pci(dev)) {\n> +\t\tstruct device *dma_dev, *bridge;\n> +\t\tstruct of_phandle_args iommu_spec;\n> +\t\tstruct pci_dev *pdev = to_pci_dev(dev);\n> +\t\tint err, count;\n> +\t\tu32 rid, map_mask;\n> +\t\tconst __be32 *msi_map;\n> +\n> +\t\tbridge = pci_get_host_bridge_device(pdev);\n> +\t\tdma_dev = bridge->parent;\n> +\t\tpci_put_host_bridge_device(bridge);\n> +\n> +\t\tif (!dma_dev->of_node)\n> +\t\t\treturn -ENODEV;\n> +\n> +\t\tiommu_spec.args_count = 1;\n> +\t\tnp = iommu_spec.np = dma_dev->of_node;\n> +\t\tpci_for_each_dma_alias(pdev, __get_pci_rid, &iommu_spec);\n> +\n> +\t\trid = iommu_spec.args[0];\n> +\t\tif (!of_property_read_u32(np, \"msi-map-mask\", &map_mask))\n> +\t\t\trid &= map_mask;\n> +\n> +\t\tmsi_map = of_get_property(np, \"msi-map\", NULL);\n> +\t\tif (!msi_map)\n> +\t\t\treturn -ENODEV;\n> +\n> +\t\tmappings = of_count_phandle_with_args(np, \"msi-map\", NULL) / 4;\n> +\n> +\t\tfor (i = 0, count = mappings; i < count; i++, msi_map += 4) {\n> +\t\t\tstruct device_node *msi_node;\n> +\t\t\tu32 rid_base, rid_len, phandle;\n> +\n> +\t\t\trid_base = be32_to_cpup(msi_map + 0);\n> +\t\t\tphandle = be32_to_cpup(msi_map + 1);\n> +\t\t\trid_len = be32_to_cpup(msi_map + 3);\n> +\n> +\t\t\t/* check rid is within range */\n> +\t\t\tif (rid < rid_base || rid >= rid_base + rid_len) {\n> +\t\t\t\tmappings--;\n> +\t\t\t\tcontinue;\n> +\t\t\t}\n> +\n> +\t\t\tmsi_node = of_find_node_by_phandle(phandle);\n> +\t\t\tif (!msi_node)\n> +\t\t\t\treturn -ENODEV;\n\nThis is basically of_pci_map_rid(), I wonder whether there is not\na way to consolidate some code here - duplicating certainly does not\nhelp. To make MSI reservations generic this is probably the only way\nto do it but it would be nice to reuse some OF MSI code.\n\nWith the current kernel API there is a way but it is a bit whacky.\n\nJust loop over \"msi-controller\" nodes and try to map the device to\nthem through of_pci_map_rid, if mapping succeeds reserve region for\nthe target node.\n\nNot a big fan of what I am proposing but it certainly helps reuse\nsome existing code that makes no sense to duplicate.\n\n> +\t\t\terr = of_address_to_resource(msi_node, 0, &res);\n> +\t\t\tof_node_put(msi_node);\n> +\t\t\tif (err)\n> +\t\t\t\treturn err;\n> +\n> +\t\t\tregion = iommu_alloc_resv_region(res.start,\n> +\t\t\t\t\t\t\t resource_size(&res),\n> +\t\t\t\t\t\t\t prot, IOMMU_RESV_MSI);\n> +\t\t\tif (region) {\n> +\t\t\t\tlist_add_tail(®ion->list, head);\n> +\t\t\t\tresv++;\n> +\t\t\t}\n> +\t\t}\n> +\t} else if (dev->of_node) {\n> +\t\tstruct device_node *msi_np;\n> +\t\tint index = 0;\n> +\t\tint tuples;\n> +\n> +\t\tnp = dev->of_node;\n> +\n> +\t\ttuples = of_count_phandle_with_args(np, \"msi-parent\", NULL);\n> +\n> +\t\twhile (index < tuples) {\n\nWould not be easier to have an of_parse_phandle_with_args() loop here ?\n\nLorenzo\n\n> +\t\t\tint msi_cells = 0;\n> +\t\t\tint err;\n> +\n> +\t\t\tmsi_np = of_parse_phandle(np, \"msi-parent\", index);\n> +\t\t\tif (!msi_np)\n> +\t\t\t\treturn -ENODEV;\n> +\n> +\t\t\tof_property_read_u32(msi_np, \"#msi-cells\", &msi_cells);\n> +\n> +\t\t\terr = of_address_to_resource(msi_np, 0, &res);\n> +\t\t\tof_node_put(msi_np);\n> +\t\t\tif (err)\n> +\t\t\t\treturn err;\n> +\n> +\t\t\tmappings++;\n> +\n> +\t\t\tregion = iommu_alloc_resv_region(res.start,\n> +\t\t\t\t\t\t\t resource_size(&res),\n> +\t\t\t\t\t\t\t prot, IOMMU_RESV_MSI);\n> +\t\t\tif (region) {\n> +\t\t\t\tlist_add_tail(®ion->list, head);\n> +\t\t\t\tresv++;\n> +\t\t\t}\n> +\t\t\tindex += 1 + msi_cells;\n> +\t\t}\n> +\t}\n> +\n> +\treturn (resv == mappings) ? resv : -ENODEV;\n> +}\n> +\n> static int __init of_iommu_init(void)\n> {\n> \tstruct device_node *np;\n> diff --git a/include/linux/of_iommu.h b/include/linux/of_iommu.h\n> index 13394ac..9267772 100644\n> --- a/include/linux/of_iommu.h\n> +++ b/include/linux/of_iommu.h\n> @@ -14,6 +14,9 @@ extern int of_get_dma_window(struct device_node *dn, const char *prefix,\n> extern const struct iommu_ops *of_iommu_configure(struct device *dev,\n> \t\t\t\t\tstruct device_node *master_np);\n> \n> +extern int of_iommu_msi_get_resv_regions(struct device *dev,\n> +\t\t\t\t\tstruct list_head *head);\n> +\n> #else\n> \n> static inline int of_get_dma_window(struct device_node *dn, const char *prefix,\n> @@ -29,6 +32,13 @@ static inline const struct iommu_ops *of_iommu_configure(struct device *dev,\n> \treturn NULL;\n> }\n> \n> +static int of_iommu_msi_get_resv_regions(struct device *dev,\n> +\t\t\t\t\tstruct list_head *head)\n> +{\n> +\treturn -ENODEV;\n> +}\n> +\n> +\n> #endif\t/* CONFIG_OF_IOMMU */\n> \n> extern struct of_device_id __iommu_of_table;\n> -- \n> 1.9.1\n> \n> \n> --\n> To unsubscribe from this list: send the line \"unsubscribe linux-acpi\" in\n> the body of a message to majordomo@vger.kernel.org\n> More majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; 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Fri, 22 Sep 2017 07:25:25 -0700 (PDT)"],"DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed;\n\td=lists.infradead.org; s=bombadil.20170209; h=Sender:\n\tContent-Transfer-Encoding:Content-Type:Cc:List-Subscribe:List-Help:List-Post:\n\tList-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:\n\tMessage-ID:Subject:To:From:Date:Reply-To:Content-ID:Content-Description:\n\tResent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:\n\tList-Owner; bh=mXjS/oBtbdzHEqJBnc7OYIIcwzUsXi9S05/4CqCETIk=;\n\tb=gW93hnWOgzbuA2\n\tZMSKDBga6/brUwRiHTFiN9iPnuX775n3grWMyEY6Yq6Oef9ng3WzDE1J8f1aWyRCY9orVXRiJcGcj\n\t5LHfGFlQaHrT3IBRk9il8jpU0npOJQzzV4QDt+y32BGLkW9OcCX1Y0yNiFuEwC+IdRNpR0pJHWONa\n\tLW0Tk1ua5ISnvLWWdA8DIN29FNaX9i27DGgqLScfEenIEGJe6+GqDKTNFjuGED4Wy9W7GCQOX44TR\n\th0vioTcccOkWq0rHRmdxDPkLgY0aAEhA1QvC0OiVco+Px5mLsMOdLdgYK6W+TxraLGUQKIIhCok8n\n\t5gpbTvT/4Nz0EMuF9XZg==;","Date":"Fri, 22 Sep 2017 15:27:58 +0100","From":"Lorenzo Pieralisi ","To":"Shameer Kolothum ","Subject":"Re: [PATCH v7 3/5] iommu/of: Add msi address regions reservation\n\thelper","Message-ID":"<20170922142758.GE3475@red-moon>","References":"<20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com>\n\t<20170914125756.14836-4-shameerali.kolothum.thodi@huawei.com>","MIME-Version":"1.0","Content-Disposition":"inline","In-Reply-To":"<20170914125756.14836-4-shameerali.kolothum.thodi@huawei.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170922_072549_626110_6F503053 ","X-CRM114-Status":"GOOD ( 25.98 )","X-Spam-Score":"-6.9 (------)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-6.9 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-5.0 RCVD_IN_DNSWL_HI RBL: Sender listed at http://www.dnswl.org/,\n\thigh trust [217.140.101.70 listed in list.dnswl.org]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"mark.rutland@arm.com, devicetree@vger.kernel.org, guohanjun@huawei.com, \n\tgabriele.paoloni@huawei.com, marc.zyngier@arm.com, joro@8bytes.org,\n\tjohn.garry@huawei.com, will.deacon@arm.com, linuxarm@huawei.com,\n\tlinux-acpi@vger.kernel.org, iommu@lists.linux-foundation.org,\n\thanjun.guo@linaro.org, wangzhou1@hisilicon.com, sudeep.holla@arm.com, \n\trobin.murphy@arm.com, linux-arm-kernel@lists.infradead.org,\n\tdevel@acpica.org","Content-Type":"text/plain; charset=\"us-ascii\"","Content-Transfer-Encoding":"7bit","Sender":"\"linux-arm-kernel\" ","Errors-To":"linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org","List-Id":"linux-imx-kernel.lists.patchwork.ozlabs.org"}},{"id":1773702,"web_url":"http://patchwork.ozlabs.org/comment/1773702/","msgid":"<5FC3163CFD30C246ABAA99954A238FA8384142E1@FRAEML521-MBX.china.huawei.com>","list_archive_url":null,"date":"2017-09-22T15:37:52","subject":"RE: [PATCH v7 3/5] iommu/of: Add msi address regions reservation\n\thelper","submitter":{"id":70507,"url":"http://patchwork.ozlabs.org/api/people/70507/","name":"Shameerali Kolothum Thodi","email":"shameerali.kolothum.thodi@huawei.com"},"content":"> -----Original Message-----\n> From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi@arm.com]\n> Sent: Friday, September 22, 2017 3:28 PM\n> To: Shameerali Kolothum Thodi \n> Cc: marc.zyngier@arm.com; sudeep.holla@arm.com; will.deacon@arm.com;\n> robin.murphy@arm.com; joro@8bytes.org; mark.rutland@arm.com;\n> hanjun.guo@linaro.org; Gabriele Paoloni ;\n> John Garry ; iommu@lists.linux-foundation.org;\n> linux-arm-kernel@lists.infradead.org; linux-acpi@vger.kernel.org;\n> devicetree@vger.kernel.org; devel@acpica.org; Linuxarm\n> ; Wangzhou (B) ;\n> Guohanjun (Hanjun Guo) \n> Subject: Re: [PATCH v7 3/5] iommu/of: Add msi address regions reservation\n> helper\n> \n> John, Shameer,\n> \n> On Thu, Sep 14, 2017 at 01:57:54PM +0100, Shameer Kolothum wrote:\n> > From: John Garry \n> >\n> > On some platforms msi-controller address regions have to be excluded\n> > from normal IOVA allocation in that they are detected and decoded in\n> > a HW specific way by system components and so they cannot be\n> considered\n> > normal IOVA address space.\n> >\n> > Add a helper function that retrieves msi address regions through device\n> > tree msi mapping, so that these regions will not be translated by IOMMU\n> > and will be excluded from IOVA allocations.\n> >\n> > Signed-off-by: John Garry \n> > Signed-off-by: Shameer Kolothum\n> \n> > ---\n> > drivers/iommu/of_iommu.c | 117\n> +++++++++++++++++++++++++++++++++++++++++++++++\n> > include/linux/of_iommu.h | 10 ++++\n> > 2 files changed, 127 insertions(+)\n> >\n> > diff --git a/drivers/iommu/of_iommu.c b/drivers/iommu/of_iommu.c\n> > index 8cb6082..f2d1a76 100644\n> > --- a/drivers/iommu/of_iommu.c\n> > +++ b/drivers/iommu/of_iommu.c\n> > @@ -21,6 +21,7 @@\n> > #include \n> > #include \n> > #include \n> > +#include \n> > #include \n> > #include \n> > #include \n> > @@ -246,6 +247,122 @@ const struct iommu_ops\n> *of_iommu_configure(struct device *dev,\n> > \treturn ops;\n> > }\n> >\n> > +/**\n> > + * of_iommu_msi_get_resv_regions - Reserved region driver helper\n> > + * @dev: Device from iommu_get_resv_regions()\n> > + * @list: Reserved region list from iommu_get_resv_regions()\n> > + *\n> > + * Returns: Number of reserved regions on success (0 if no associated\n> > + * msi parent), appropriate error value otherwise.\n> > + */\n> > +int of_iommu_msi_get_resv_regions(struct device *dev, struct list_head\n> *head)\n> > +{\n> > +\tint prot = IOMMU_WRITE | IOMMU_NOEXEC | IOMMU_MMIO;\n> > +\tstruct iommu_resv_region *region;\n> > +\tstruct device_node *np;\n> > +\tstruct resource res;\n> > +\tint i, resv = 0, mappings = 0;\n> > +\n> > +\tif (dev_is_pci(dev)) {\n> > +\t\tstruct device *dma_dev, *bridge;\n> > +\t\tstruct of_phandle_args iommu_spec;\n> > +\t\tstruct pci_dev *pdev = to_pci_dev(dev);\n> > +\t\tint err, count;\n> > +\t\tu32 rid, map_mask;\n> > +\t\tconst __be32 *msi_map;\n> > +\n> > +\t\tbridge = pci_get_host_bridge_device(pdev);\n> > +\t\tdma_dev = bridge->parent;\n> > +\t\tpci_put_host_bridge_device(bridge);\n> > +\n> > +\t\tif (!dma_dev->of_node)\n> > +\t\t\treturn -ENODEV;\n> > +\n> > +\t\tiommu_spec.args_count = 1;\n> > +\t\tnp = iommu_spec.np = dma_dev->of_node;\n> > +\t\tpci_for_each_dma_alias(pdev, __get_pci_rid,\n> &iommu_spec);\n> > +\n> > +\t\trid = iommu_spec.args[0];\n> > +\t\tif (!of_property_read_u32(np, \"msi-map-mask\",\n> &map_mask))\n> > +\t\t\trid &= map_mask;\n> > +\n> > +\t\tmsi_map = of_get_property(np, \"msi-map\", NULL);\n> > +\t\tif (!msi_map)\n> > +\t\t\treturn -ENODEV;\n> > +\n> > +\t\tmappings = of_count_phandle_with_args(np, \"msi-map\",\n> NULL) / 4;\n> > +\n> > +\t\tfor (i = 0, count = mappings; i < count; i++, msi_map += 4) {\n> > +\t\t\tstruct device_node *msi_node;\n> > +\t\t\tu32 rid_base, rid_len, phandle;\n> > +\n> > +\t\t\trid_base = be32_to_cpup(msi_map + 0);\n> > +\t\t\tphandle = be32_to_cpup(msi_map + 1);\n> > +\t\t\trid_len = be32_to_cpup(msi_map + 3);\n> > +\n> > +\t\t\t/* check rid is within range */\n> > +\t\t\tif (rid < rid_base || rid >= rid_base + rid_len) {\n> > +\t\t\t\tmappings--;\n> > +\t\t\t\tcontinue;\n> > +\t\t\t}\n> > +\n> > +\t\t\tmsi_node = of_find_node_by_phandle(phandle);\n> > +\t\t\tif (!msi_node)\n> > +\t\t\t\treturn -ENODEV;\n> \n> This is basically of_pci_map_rid(), I wonder whether there is not\n> a way to consolidate some code here - duplicating certainly does not\n> help. To make MSI reservations generic this is probably the only way\n> to do it but it would be nice to reuse some OF MSI code.\n> \n> With the current kernel API there is a way but it is a bit whacky.\n> \n> Just loop over \"msi-controller\" nodes and try to map the device to\n> them through of_pci_map_rid, if mapping succeeds reserve region for\n> the target node.\n> \n> Not a big fan of what I am proposing but it certainly helps reuse\n> some existing code that makes no sense to duplicate.\n\nRight, lot of this is of_pci_map_rid() code. And just to confirm, \nI think the proposal is to make use of the @target node param in \nof_pci_map_rid() for a matching \"msi-controller\".\n\n> > +\t\t\terr = of_address_to_resource(msi_node, 0, &res);\n> > +\t\t\tof_node_put(msi_node);\n> > +\t\t\tif (err)\n> > +\t\t\t\treturn err;\n> > +\n> > +\t\t\tregion = iommu_alloc_resv_region(res.start,\n> > +\t\t\t\t\t\t\t resource_size(&res),\n> > +\t\t\t\t\t\t\t prot,\n> IOMMU_RESV_MSI);\n> > +\t\t\tif (region) {\n> > +\t\t\t\tlist_add_tail(®ion->list, head);\n> > +\t\t\t\tresv++;\n> > +\t\t\t}\n> > +\t\t}\n> > +\t} else if (dev->of_node) {\n> > +\t\tstruct device_node *msi_np;\n> > +\t\tint index = 0;\n> > +\t\tint tuples;\n> > +\n> > +\t\tnp = dev->of_node;\n> > +\n> > +\t\ttuples = of_count_phandle_with_args(np, \"msi-parent\",\n> NULL);\n> > +\n> > +\t\twhile (index < tuples) {\n> \n> Would not be easier to have an of_parse_phandle_with_args() loop here ?\n\nOk. Many thanks for going through this. We will rework this based on your\nsuggestions and send out the next revision (rebased on -rc1).\n\nThanks,\nShameer","headers":{"Return-Path":"","X-Original-To":"incoming-imx@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-imx@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.infradead.org\n\t(client-ip=65.50.211.133; helo=bombadil.infradead.org;\n\tenvelope-from=linux-arm-kernel-bounces+incoming-imx=patchwork.ozlabs.org@lists.infradead.org;\n\treceiver=)","ozlabs.org; dkim=pass (2048-bit key;\n\tunprotected) header.d=lists.infradead.org\n\theader.i=@lists.infradead.org\n\theader.b=\"TmYwM8Na\"; dkim-atps=neutral"],"Received":["from bombadil.infradead.org (bombadil.infradead.org\n\t[65.50.211.133])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xzHhC0nV1z9s7h\n\tfor ;\n\tSat, 23 Sep 2017 01:38:51 +1000 (AEST)","from localhost ([127.0.0.1] helo=bombadil.infradead.org)\n\tby bombadil.infradead.org with esmtp (Exim 4.87 #1 (Red Hat Linux))\n\tid 1dvQ2S-0001rB-1i; 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bh=WQ8LkpUucjmJP+jbiWGB7R9ynRWIhCKwxig7tWxDPxQ=;\n\tb=TmYwM8Nad/1/Is\n\tSpwoLISfiAPMvEhH4r6XgqApe0Lkva7ZYRoKukpGlALHrR/gQW7PdUoq37zO2RpcZqa2MkCqqKXJp\n\tkG98fLibPLkqmER9nY4RfsfqxREAFP6tVuYZdC5Q9FtbSbBhYZ+/Ag6CfPcwGz57+RYHJqE/PaOhW\n\tXOvDuvYVyd28iSsX0nPsN0iGu6tFt1UwL8a9SGPrnN4ii6neJLZVy4uzUh/d3LRZmibLteYs6acD9\n\tWZoMHrhz7CFjhfDTsY13C0fIHwf1nfevuE3n8iIpbrPTDdQ8bX+56oxSZgU11txrmothPUC6GmVS+\n\tf/znixPW9YLbz68QFfcg==;","From":"Shameerali Kolothum Thodi ","To":"Lorenzo Pieralisi ","Subject":"RE: [PATCH v7 3/5] iommu/of: Add msi address regions reservation\n\thelper","Thread-Topic":"[PATCH v7 3/5] iommu/of: Add msi address regions reservation\n\thelper","Thread-Index":"AQHTLVmCIBTeBhfEukWKEYWoEWcA6aLA4b8AgAAoI6A=","Date":"Fri, 22 Sep 2017 15:37:52 +0000","Message-ID":"<5FC3163CFD30C246ABAA99954A238FA8384142E1@FRAEML521-MBX.china.huawei.com>","References":"<20170914125756.14836-1-shameerali.kolothum.thodi@huawei.com>\n\t<20170914125756.14836-4-shameerali.kolothum.thodi@huawei.com>\n\t<20170922142758.GE3475@red-moon>","In-Reply-To":"<20170922142758.GE3475@red-moon>","Accept-Language":"en-GB, en-US","Content-Language":"en-US","X-MS-Has-Attach":"","X-MS-TNEF-Correlator":"","x-originating-ip":"[10.203.177.212]","MIME-Version":"1.0","X-CFilter-Loop":"Reflected","X-Mirapoint-Virus-RAPID-Raw":"score=unknown(0),\n\trefid=str=0001.0A020206.59C52E63.019D, ss=1, re=0.000, recu=0.000,\n\treip=0.000, \n\tcl=1, cld=1, fgs=0, ip=169.254.1.161,\n\tso=2013-06-18 04:22:30, dmn=2013-03-21 17:37:32","X-Mirapoint-Loop-Id":"64483f65fff88bb94d4f3484273f1fa1","X-CRM114-Version":"20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 ","X-CRM114-CacheID":"sfid-20170922_083842_618824_EE2C4DC1 ","X-CRM114-Status":"GOOD ( 24.49 )","X-Spam-Score":"-4.2 (----)","X-Spam-Report":"SpamAssassin version 3.4.1 on bombadil.infradead.org summary:\n\tContent analysis details: (-4.2 points)\n\tpts rule name description\n\t---- ----------------------\n\t--------------------------------------------------\n\t-2.3 RCVD_IN_DNSWL_MED RBL: Sender listed at http://www.dnswl.org/,\n\tmedium trust [194.213.3.17 listed in list.dnswl.org]\n\t-0.0 RCVD_IN_MSPIKE_H3 RBL: Good reputation (+3)\n\t[194.213.3.17 listed in wl.mailspike.net]\n\t-0.0 SPF_PASS SPF: sender matches SPF record\n\t-0.0 RP_MATCHES_RCVD Envelope sender domain matches handover relay\n\tdomain\n\t-1.9 BAYES_00 BODY: Bayes spam probability is 0 to 1%\n\t[score: 0.0000]\n\t-0.0 RCVD_IN_MSPIKE_WL Mailspike good senders","X-BeenThere":"linux-arm-kernel@lists.infradead.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"\"mark.rutland@arm.com\" ,\n\t\"devicetree@vger.kernel.org\" , \"Guohanjun\n\t\\(Hanjun Guo\\)\" ,\n\tGabriele Paoloni ,\n\t\"marc.zyngier@arm.com\" ,\n\t\"joro@8bytes.org\" , John Garry , \n\t\"will.deacon@arm.com\" ,\n\tLinuxarm , \n\t\"linux-acpi@vger.kernel.org\" ,\n\t\"iommu@lists.linux-foundation.org\" ,\n\t\"hanjun.guo@linaro.org\" ,\n\t\"Wangzhou \\(B\\)\" ,\n\t\"sudeep.holla@arm.com\" ,\n\t\"robin.murphy@arm.com\" ,\n\t\"linux-arm-kernel@lists.infradead.org\"\n\t, \n\t\"devel@acpica.org\" ","Content-Type":"text/plain; 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