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{ "id": 811557, "url": "http://patchwork.ozlabs.org/api/covers/811557/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/1504873388-29195-1-git-send-email-vjonnal@xilinx.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>", "list_archive_url": null, "date": "2017-09-08T12:23:02", "name": "[v2,0/5] dmaengine: ZynqMP PS PCIe DMA driver", "submitter": { "id": 72127, "url": "http://patchwork.ozlabs.org/api/people/72127/?format=api", "name": "Ravi Shankar Jonnalagadda", "email": "venkata.ravi.jonnalagadda@xilinx.com" }, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/1504873388-29195-1-git-send-email-vjonnal@xilinx.com/mbox/", "series": [ { "id": 2192, "url": "http://patchwork.ozlabs.org/api/series/2192/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=2192", "date": "2017-09-08T12:23:02", "name": "dmaengine: ZynqMP PS PCIe DMA driver", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/2192/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/811557/comments/", "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=xilinx.onmicrosoft.com\n\theader.i=@xilinx.onmicrosoft.com\n\theader.b=\"t3/vujUI\"; dkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xpc654bZDz9sRW\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tFri, 8 Sep 2017 22:27:39 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1754946AbdIHMXr (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tFri, 8 Sep 2017 08:23:47 -0400", "from mail-bn3nam01on0047.outbound.protection.outlook.com\n\t([104.47.33.47]:63986\n\t\"EHLO NAM01-BN3-obe.outbound.protection.outlook.com\"\n\trhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP\n\tid S1754914AbdIHMXb (ORCPT <rfc822;devicetree@vger.kernel.org>);\n\tFri, 8 Sep 2017 08:23:31 -0400", "from BLUPR0201CA0018.namprd02.prod.outlook.com (10.163.116.28) by\n\tBLUPR0201MB1923.namprd02.prod.outlook.com (10.162.239.157) with\n\tMicrosoft SMTP Server (version=TLS1_2,\n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.35.12;\n\tFri, 8 Sep 2017 12:23:27 +0000", "from SN1NAM02FT064.eop-nam02.prod.protection.outlook.com\n\t(2a01:111:f400:7e44::203) by BLUPR0201CA0018.outlook.office365.com\n\t(2a01:111:e400:52e7::28) with Microsoft SMTP Server (version=TLS1_2, \n\tcipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.35.12 via\n\tFrontend Transport; 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Fri, 08 Sep 2017 05:23:12 -0700", "by xhd-paegbuild40.xilinx.com (Postfix, from userid 12633)\n\tid 7C4EDB20857; Fri, 8 Sep 2017 17:53:11 +0530 (IST)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=xilinx.onmicrosoft.com; s=selector1-xilinx-com;\n\th=From:Date:Subject:Message-ID:Content-Type:MIME-Version;\n\tbh=UP7COu89fTkQK/OHbHPI9XrdJZh0+8I/OagEJq11Baw=;\n\tb=t3/vujUIydb2hnLloVHiGYCJ4Q5cw+qiljjZmornVN3DamxFRlk1vsiDSuS5t8PP8GPCNi25XrjQgwzChh5pgvXsSUgJtd/jAb9/8OKN9Jt4JDy/ngE0LRuykB+ZjHKL1DrUVGpmPBV40+4rAVFjZ9WkX4/DhQY42xXlkO+/Wdc=", "Received-SPF": "Pass (protection.outlook.com: domain of xilinx.com designates\n\t149.199.60.100 as permitted sender)\n\treceiver=protection.outlook.com; \n\tclient-ip=149.199.60.100; helo=xsj-pvapsmtpgw02;", "From": "Ravi Shankar Jonnalagadda <venkata.ravi.jonnalagadda@xilinx.com>", "To": "<vinod.koul@intel.com>, <robh+dt@kernel.org>,\n\t<mark.rutland@arm.com>, <michal.simek@xilinx.com>,\n\t<soren.brinkmann@xilinx.com>, <dan.j.williams@intel.com>,\n\t<bhelgaas@google.com>, <vjonnal@xilinx.com>,\n\t<lorenzo.pieralisi@arm.com>, <bharat.kumar.gogada@xilinx.com>,\n\t<dmaengine@vger.kernel.org>, <devicetree@vger.kernel.org>,\n\t<linux-arm-kernel@lists.infradead.org>,\n\t<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<rgummal@xilinx.com>", "Subject": "[PATCH v2 0/5] dmaengine: ZynqMP PS PCIe DMA driver", "Date": "Fri, 8 Sep 2017 17:53:02 +0530", "Message-ID": "<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>", "X-Mailer": "git-send-email 2.1.1", "X-RCIS-Action": "ALLOW", "X-TM-AS-Product-Ver": "IMSS-7.1.0.1224-8.1.0.1062-23314.003", "X-TM-AS-User-Approved-Sender": "Yes;Yes", "X-EOPAttributedMessage": "0", "X-MS-Office365-Filtering-HT": "Tenant", "X-Forefront-Antispam-Report": "CIP:149.199.60.100; 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BCL:0; PCL:0;\n\tRULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095);\n\tSRVR:BLUPR0201MB1923; ", "X-Forefront-PRVS": "04244E0DC5", "SpamDiagnosticOutput": "1:99", "SpamDiagnosticMetadata": "NSPM", "X-OriginatorOrg": "xilinx.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "08 Sep 2017 12:23:23.1938\n\t(UTC)", "X-MS-Exchange-CrossTenant-Id": "657af505-d5df-48d0-8300-c31994686c5c", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "TenantId=657af505-d5df-48d0-8300-c31994686c5c;\n\tIp=[149.199.60.100]; \n\tHelo=[xsj-pvapsmtpgw02]", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "BLUPR0201MB1923", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "ZynqMP devices have PCIe Bridge along with DMA in PS.\nThese devices can be configured as either PCIe Endpoints\nor as PCIe Root Complex.\nThis patch series shall provide a driver to initiate\ntransactions using this DMA.\nSingle platform driver shall handle both EndPoint and\nRoot DMA transfers.\nPatch 1 enables Root DMA register translation and\n\tinterrupts\nPatch 2 corrects styling errors seen with checkpatch\nPatch 3 adds PCIe driver for end points\nPatch 4 adds Platform driver which handles DMA transactions\n\tfor both PCI end points and Root DMA\nPatch 5 describes device tree bindings for Root DMA\n\n\nRavi Shankar Jonnalagadda (5):\n PCI:xilinx-nwl: Enable Root DMA\n PCI:xilinx-nwl: Correcting Styling checks\n dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA driver\n dmaengine: zynqmp_ps_pcie: Adding PS PCIe platform DMA driver\n devicetree: zynqmp_ps_pcie: Devicetree binding for Root DMA\n\n .../devicetree/bindings/dma/xilinx/ps-pcie-dma.txt | 67 +\n drivers/dma/Kconfig | 12 +\n drivers/dma/xilinx/Makefile | 2 +\n drivers/dma/xilinx/ps_pcie.h | 44 +\n drivers/dma/xilinx/ps_pcie_main.c | 200 ++\n drivers/dma/xilinx/ps_pcie_platform.c | 3055 ++++++++++++++++++++\n drivers/pci/host/pcie-xilinx-nwl.c | 23 +-\n include/linux/dma/ps_pcie_dma.h | 69 +\n 8 files changed, 3468 insertions(+), 4 deletions(-)\n create mode 100644 Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n create mode 100644 drivers/dma/xilinx/ps_pcie.h\n create mode 100644 drivers/dma/xilinx/ps_pcie_main.c\n create mode 100644 drivers/dma/xilinx/ps_pcie_platform.c\n create mode 100644 include/linux/dma/ps_pcie_dma.h" }