[{"id":1771318,"web_url":"http://patchwork.ozlabs.org/comment/1771318/","msgid":"<20170919193635.GE22312@bhelgaas-glaptop.roam.corp.google.com>","list_archive_url":null,"date":"2017-09-19T19:36:35","subject":"Re: [PATCH v2 1/5] PCI:xilinx-nwl: Enable Root DMA","submitter":{"id":67298,"url":"http://patchwork.ozlabs.org/api/people/67298/","name":"Bjorn Helgaas","email":"helgaas@kernel.org"},"content":"Hi Ravi,\n\nPlease make the subject line follow the existing convention, i.e., run\n\n $ git log --oneline drivers/pci/host/pcie-xilinx-nwl.c\n\nand make yours match spacing, capitalization, and style (imperative\nsentence).\n\nAlso waiting for ack from Michal.\n\nOn Fri, Sep 08, 2017 at 05:53:03PM +0530, Ravi Shankar Jonnalagadda wrote:\n> Enabling Root DMA interrupts\n> \n> Adding Root DMA translations to bridge for Register Access\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> drivers/pci/host/pcie-xilinx-nwl.c | 15 +++++++++++++++\n> 1 file changed, 15 insertions(+)\n> \n> diff --git a/drivers/pci/host/pcie-xilinx-nwl.c b/drivers/pci/host/pcie-xilinx-nwl.c\n> index eec641a..5766582 100644\n> --- a/drivers/pci/host/pcie-xilinx-nwl.c\n> +++ b/drivers/pci/host/pcie-xilinx-nwl.c\n> @@ -39,6 +39,11 @@\n> #define E_ECAM_CONTROL\t\t\t0x00000228\n> #define E_ECAM_BASE_LO\t\t\t0x00000230\n> #define E_ECAM_BASE_HI\t\t\t0x00000234\n> +#define E_DREG_CTRL\t\t\t0x00000288\n> +#define E_DREG_BASE_LO\t\t\t0x00000290\n> +\n> +#define DREG_DMA_EN\t\t\tBIT(0)\n> +#define DREG_DMA_BASE_LO\t\t0xFD0F0000\n> \n> /* Ingress - address translations */\n> #define I_MSII_CAPABILITIES\t\t0x00000300\n> @@ -57,6 +62,10 @@\n> #define MSGF_MSI_STATUS_HI\t\t0x00000444\n> #define MSGF_MSI_MASK_LO\t\t0x00000448\n> #define MSGF_MSI_MASK_HI\t\t0x0000044C\n> +/* Root DMA Interrupt register */\n> +#define MSGF_DMA_MASK\t\t\t0x00000464\n> +\n> +#define MSGF_INTR_EN\t\t\tBIT(0)\n> \n> /* Msg filter mask bits */\n> #define CFG_ENABLE_PM_MSG_FWD\t\tBIT(1)\n> @@ -766,6 +775,12 @@ static int nwl_pcie_bridge_init(struct nwl_pcie *pcie)\n> \tnwl_bridge_writel(pcie, nwl_bridge_readl(pcie, MSGF_LEG_STATUS) &\n> \t\t\t MSGF_LEG_SR_MASKALL, MSGF_LEG_STATUS);\n> \n> +\t/* Enabling DREG translations */\n> +\tnwl_bridge_writel(pcie, DREG_DMA_EN, E_DREG_CTRL);\n> +\tnwl_bridge_writel(pcie, DREG_DMA_BASE_LO, E_DREG_BASE_LO);\n> +\t/* Enabling Root DMA interrupts */\n> +\tnwl_bridge_writel(pcie, MSGF_INTR_EN, MSGF_DMA_MASK);\n> +\n> \t/* Enable all legacy interrupts */\n> \tnwl_bridge_writel(pcie, MSGF_LEG_SR_MASKALL, MSGF_LEG_MASK);\n> \n> -- \n> 2.7.4\n> \n--\nTo unsubscribe from this list: send the line \"unsubscribe devicetree\" in\nthe body of a message to majordomo@vger.kernel.org\nMore majordomo info at http://vger.kernel.org/majordomo-info.html","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","mail.kernel.org;\n\tdmarc=none (p=none dis=none) header.from=kernel.org","mail.kernel.org;\n\tspf=none smtp.mailfrom=helgaas@kernel.org"],"Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xxY5z4jB8z9s81\n\tfor ;\n\tWed, 20 Sep 2017 05:36:39 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1750872AbdISTgi (ORCPT\n\t);\n\tTue, 19 Sep 2017 15:36:38 -0400","from mail.kernel.org ([198.145.29.99]:46666 \"EHLO mail.kernel.org\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750733AbdISTgh (ORCPT );\n\tTue, 19 Sep 2017 15:36:37 -0400","from localhost (unknown [69.55.156.165])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby mail.kernel.org (Postfix) with ESMTPSA id 4A5B3218F8;\n\tTue, 19 Sep 2017 19:36:36 +0000 (UTC)"],"DMARC-Filter":"OpenDMARC Filter v1.3.2 mail.kernel.org 4A5B3218F8","Date":"Tue, 19 Sep 2017 14:36:35 -0500","From":"Bjorn Helgaas ","To":"Ravi Shankar Jonnalagadda ","Cc":"vinod.koul@intel.com, robh+dt@kernel.org, mark.rutland@arm.com,\n\tmichal.simek@xilinx.com, soren.brinkmann@xilinx.com,\n\tdan.j.williams@intel.com, bhelgaas@google.com, vjonnal@xilinx.com,\n\tlorenzo.pieralisi@arm.com, bharat.kumar.gogada@xilinx.com,\n\tdmaengine@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, rgummal@xilinx.com","Subject":"Re: [PATCH v2 1/5] PCI:xilinx-nwl: Enable Root DMA","Message-ID":"<20170919193635.GE22312@bhelgaas-glaptop.roam.corp.google.com>","References":"<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>\n\t<1504873388-29195-2-git-send-email-vjonnal@xilinx.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504873388-29195-2-git-send-email-vjonnal@xilinx.com>","User-Agent":"Mutt/1.5.21 (2010-09-15)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1771584,"web_url":"http://patchwork.ozlabs.org/comment/1771584/","msgid":"<1e17381d-0e60-e563-4f74-96245fe00aaf@monstr.eu>","list_archive_url":null,"date":"2017-09-20T05:49:19","subject":"Re: [PATCH v2 3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA\n\tdriver","submitter":{"id":2237,"url":"http://patchwork.ozlabs.org/api/people/2237/","name":"Michal Simek","email":"monstr@monstr.eu"},"content":"On 8.9.2017 14:23, Ravi Shankar Jonnalagadda wrote:\n> Adding support for ZynqmMP PS PCIe EP driver.\n> Adding support for ZynqmMP PS PCIe Root DMA driver.\n> Modifying Kconfig and Makefile to add the support.\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> drivers/dma/Kconfig | 12 +++\n> drivers/dma/xilinx/Makefile | 2 +\n> drivers/dma/xilinx/ps_pcie.h | 44 +++++++++\n> drivers/dma/xilinx/ps_pcie_main.c | 200 ++++++++++++++++++++++++++++++++++++++\n> include/linux/dma/ps_pcie_dma.h | 69 +++++++++++++\n> 5 files changed, 327 insertions(+)\n> create mode 100644 drivers/dma/xilinx/ps_pcie.h\n> create mode 100644 drivers/dma/xilinx/ps_pcie_main.c\n> create mode 100644 include/linux/dma/ps_pcie_dma.h\n> \n> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig\n> index fa8f9c0..e2fe4e5 100644\n> --- a/drivers/dma/Kconfig\n> +++ b/drivers/dma/Kconfig\n> @@ -586,6 +586,18 @@ config XILINX_ZYNQMP_DMA\n> \thelp\n> \t Enable support for Xilinx ZynqMP DMA controller.\n> \n> +config XILINX_PS_PCIE_DMA\n> +\ttristate \"Xilinx PS PCIe DMA support\"\n> +\tdepends on (PCI && X86_64 || ARM64)\n> +\tselect DMA_ENGINE\n> +\thelp\n> +\t Enable support for the Xilinx PS PCIe DMA engine present\n> +\t in recent Xilinx ZynqMP chipsets.\n> +\n> +\t Say Y here if you have such a chipset.\n> +\n> +\t If unsure, say N.\n> +\n> config ZX_DMA\n> \ttristate \"ZTE ZX DMA support\"\n> \tdepends on ARCH_ZX || COMPILE_TEST\n> diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile\n> index 9e91f8f..04f6f99 100644\n> --- a/drivers/dma/xilinx/Makefile\n> +++ b/drivers/dma/xilinx/Makefile\n> @@ -1,2 +1,4 @@\n> obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o\n> obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o\n> +ps_pcie_dma-objs := ps_pcie_main.o ps_pcie_platform.o\n> +obj-$(CONFIG_XILINX_PS_PCIE_DMA) += ps_pcie_dma.o\n> diff --git a/drivers/dma/xilinx/ps_pcie.h b/drivers/dma/xilinx/ps_pcie.h\n> new file mode 100644\n> index 0000000..351f051\n> --- /dev/null\n> +++ b/drivers/dma/xilinx/ps_pcie.h\n> @@ -0,0 +1,44 @@\n> +/*\n> + * Xilinx PS PCIe DMA Engine platform header file\n> + *\n> + * Copyright (C) 2010-2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#ifndef __XILINX_PS_PCIE_H\n> +#define __XILINX_PS_PCIE_H\n> +\n> +#include \n> +#include \n\nthis is included via dma-mapping.h below.\n\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n\nthis is already include via of.h\n\n> +#include \n> +#include \n> +#include \n\nDon't we have any script for checking this?\n\n> +\n> +/**\n> + * dma_platform_driver_register - This will be invoked by module init\n> + *\n> + * Return: returns status of platform_driver_register\n> + */\n> +int dma_platform_driver_register(void);\n\n\nput empty line here.\n\n> +/**\n> + * dma_platform_driver_unregister - This will be invoked by module exit\n> + *\n> + * Return: returns void after unregustering platform driver\n> + */\n> +void dma_platform_driver_unregister(void);\n> +\n> +#endif\n> diff --git a/drivers/dma/xilinx/ps_pcie_main.c b/drivers/dma/xilinx/ps_pcie_main.c\n> new file mode 100644\n> index 0000000..4ccd8ef\n> --- /dev/null\n> +++ b/drivers/dma/xilinx/ps_pcie_main.c\n> @@ -0,0 +1,200 @@\n> +/*\n> + * XILINX PS PCIe driver\n> + *\n> + * Copyright (C) 2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * Description\n> + * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers\n> + * on ZynqMP UltraScale+ Devices.\n> + * This PCIe driver creates a platform device with specific platform\n> + * info enabling creation of DMA device corresponding to the channel\n> + * information provided in the properties\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#include \"ps_pcie.h\"\n> +#include \"../dmaengine.h\"\n> +\n> +#define DRV_MODULE_NAME\t\t \"ps_pcie_dma\"\n> +\n> +static int ps_pcie_dma_probe(struct pci_dev *pdev,\n> +\t\t\t const struct pci_device_id *ent);\n> +static void ps_pcie_dma_remove(struct pci_dev *pdev);\n> +\n> +static u32 channel_properties_pcie_axi[] = {\n> +\t(u32)(PCIE_AXI_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),\n> +\t(u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),\n> +\t(u32)(CHANNEL_POLL_TIMER_FREQUENCY) };\n> +\n> +static u32 channel_properties_axi_pcie[] = {\n> +\t(u32)(AXI_PCIE_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),\n> +\t(u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),\n> +\t(u32)(CHANNEL_POLL_TIMER_FREQUENCY) };\n> +\n> +static struct property_entry generic_pcie_ep_property[] = {\n> +\tPROPERTY_ENTRY_U32(\"numchannels\", (u32)MAX_NUMBER_OF_CHANNELS),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel0\",\n> +\t\t\t\t channel_properties_pcie_axi),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel1\",\n> +\t\t\t\t channel_properties_axi_pcie),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel2\",\n> +\t\t\t\t channel_properties_pcie_axi),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel3\",\n> +\t\t\t\t channel_properties_axi_pcie),\n> +\t{ },\n> +};\n> +\n> +static const struct platform_device_info xlnx_std_platform_dev_info = {\n> +\t.name = XLNX_PLATFORM_DRIVER_NAME,\n> +\t.properties = generic_pcie_ep_property,\n> +};\n> +\n> +/**\n> + * ps_pcie_dma_probe - Driver probe function\n> + * @pdev: Pointer to the pci_dev structure\n> + * @ent: pci device id\n> + *\n> + * Return: '0' on success and failure value on error\n> + */\n> +static int ps_pcie_dma_probe(struct pci_dev *pdev,\n> +\t\t\t const struct pci_device_id *ent)\n> +{\n> +\tint err;\n> +\tstruct platform_device *platform_dev;\n> +\tstruct platform_device_info platform_dev_info;\n> +\n> +\tdev_info(&pdev->dev, \"PS PCIe DMA Driver probe\\n\");\n> +\n> +\terr = pcim_enable_device(pdev);\n> +\tif (err) {\n> +\t\tdev_err(&pdev->dev, \"Cannot enable PCI device, aborting\\n\");\n> +\t\treturn err;\n> +\t}\n> +\n> +\terr = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));\n> +\tif (err) {\n> +\t\tdev_info(&pdev->dev, \"Cannot set 64 bit DMA mask\\n\");\n> +\t\terr = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));\n> +\t\tif (err) {\n> +\t\t\tdev_err(&pdev->dev, \"DMA mask set error\\n\");\n> +\t\t\treturn err;\n> +\t\t}\n> +\t}\n> +\n> +\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));\n> +\tif (err) {\n> +\t\tdev_info(&pdev->dev, \"Cannot set 64 bit consistent DMA mask\\n\");\n> +\t\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));\n> +\t\tif (err) {\n> +\t\t\tdev_err(&pdev->dev, \"Cannot set consistent DMA mask\\n\");\n> +\t\t\treturn err;\n> +\t\t}\n> +\t}\n> +\n> +\tpci_set_master(pdev);\n> +\n> +\t/* For Root DMA platform device will be created through device tree */\n> +\tif (pdev->vendor == PCI_VENDOR_ID_XILINX &&\n> +\t pdev->device == ZYNQMP_RC_DMA_DEVID)\n> +\t\treturn 0;\n> +\n> +\tmemcpy(&platform_dev_info, &xlnx_std_platform_dev_info,\n> +\t sizeof(xlnx_std_platform_dev_info));\n> +\n> +\t/* Do device specific channel configuration changes to\n> +\t * platform_dev_info.properties if required\n> +\t * More information on channel properties can be found\n> +\t * at Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n> +\t */\n> +\n> +\tplatform_dev_info.parent = &pdev->dev;\n> +\tplatform_dev_info.data = &pdev;\n> +\tplatform_dev_info.size_data = sizeof(struct pci_dev **);\n> +\n> +\tplatform_dev = platform_device_register_full(&platform_dev_info);\n> +\tif (IS_ERR(platform_dev)) {\n> +\t\tdev_err(&pdev->dev,\n> +\t\t\t\"Cannot create platform device, aborting\\n\");\n> +\t\treturn PTR_ERR(platform_dev);\n> +\t}\n> +\n> +\tpci_set_drvdata(pdev, platform_dev);\n> +\n> +\tdev_info(&pdev->dev, \"PS PCIe DMA driver successfully probed\\n\");\n> +\n> +\treturn 0;\n> +}\n> +\n> +static struct pci_device_id ps_pcie_dma_tbl[] = {\n> +\t{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, ZYNQMP_DMA_DEVID) },\n> +\t{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, ZYNQMP_RC_DMA_DEVID) },\n> +\t{ }\n> +};\n> +\n> +static struct pci_driver ps_pcie_dma_driver = {\n> +\t.name = DRV_MODULE_NAME,\n> +\t.id_table = ps_pcie_dma_tbl,\n> +\t.probe = ps_pcie_dma_probe,\n> +\t.remove = ps_pcie_dma_remove,\n> +};\n> +\n> +/**\n> + * ps_pcie_init - Driver init function\n> + *\n> + * Return: 0 on success. Non zero on failure\n> + */\n> +static int __init ps_pcie_init(void)\n> +{\n> +\tint ret;\n> +\n> +\tpr_info(\"%s init()\\n\", DRV_MODULE_NAME);\n> +\n> +\tret = pci_register_driver(&ps_pcie_dma_driver);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tret = dma_platform_driver_register();\n> +\tif (ret)\n> +\t\tpci_unregister_driver(&ps_pcie_dma_driver);\n> +\n> +\treturn ret;\n> +}\n> +\n> +/**\n> + * ps_pcie_dma_remove - Driver remove function\n> + * @pdev: Pointer to the pci_dev structure\n> + *\n> + * Return: void\n> + */\n> +static void ps_pcie_dma_remove(struct pci_dev *pdev)\n> +{\n> +\tstruct platform_device *platform_dev;\n> +\n> +\tplatform_dev = (struct platform_device *)pci_get_drvdata(pdev);\n> +\n> +\tif (platform_dev)\n> +\t\tplatform_device_unregister(platform_dev);\n> +}\n> +\n> +/**\n> + * ps_pcie_exit - Driver exit function\n> + *\n> + * Return: void\n> + */\n> +static void __exit ps_pcie_exit(void)\n> +{\n> +\tpr_info(\"%s exit()\\n\", DRV_MODULE_NAME);\n> +\n> +\tdma_platform_driver_unregister();\n> +\tpci_unregister_driver(&ps_pcie_dma_driver);\n> +}\n> +\n> +module_init(ps_pcie_init);\n> +module_exit(ps_pcie_exit);\n> +\n> +MODULE_AUTHOR(\"Xilinx Inc\");\n> +MODULE_DESCRIPTION(\"Xilinx PS PCIe DMA Driver\");\n> +MODULE_LICENSE(\"GPL v2\");\n> diff --git a/include/linux/dma/ps_pcie_dma.h b/include/linux/dma/ps_pcie_dma.h\n> new file mode 100644\n> index 0000000..d11323a\n> --- /dev/null\n> +++ b/include/linux/dma/ps_pcie_dma.h\n> @@ -0,0 +1,69 @@\n> +/*\n> + * Xilinx PS PCIe DMA Engine support header file\n> + *\n> + * Copyright (C) 2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#ifndef __DMA_XILINX_PS_PCIE_H\n> +#define __DMA_XILINX_PS_PCIE_H\n> +\n> +#include \n> +#include \n> +\n> +#define XLNX_PLATFORM_DRIVER_NAME \"xlnx-platform-dma-driver\"\n> +\n> +#define ZYNQMP_DMA_DEVID\t(0xD024)\n> +#define ZYNQMP_RC_DMA_DEVID\t(0xD021)\n\n\nAre these hardcoded? If yes, maybe we have better location where these\nshould be put.\n\n\n> +\n> +#define MAX_ALLOWED_CHANNELS_IN_HW\t4\n> +\n> +#define MAX_NUMBER_OF_CHANNELS\tMAX_ALLOWED_CHANNELS_IN_HW\n> +\n> +#define DEFAULT_DMA_QUEUES\t4\n> +#define TWO_DMA_QUEUES\t\t2\n> +\n> +#define NUMBER_OF_BUFFER_DESCRIPTORS\t1999\n> +#define MAX_DESCRIPTORS\t\t\t65536\n> +\n> +#define CHANNEL_COAELSE_COUNT\t\t0\n> +\n> +#define CHANNEL_POLL_TIMER_FREQUENCY\t1000 /* in milli seconds */\n> +\n> +#define PCIE_AXI_DIRECTION\tDMA_TO_DEVICE\n> +#define AXI_PCIE_DIRECTION\tDMA_FROM_DEVICE\n> +\n> +/**\n> + * struct BAR_PARAMS - PCIe Bar Parameters\n> + * @BAR_PHYS_ADDR: PCIe BAR Physical address\n> + * @BAR_LENGTH: Length of PCIe BAR\n> + * @BAR_VIRT_ADDR: Virtual Address to access PCIe BAR\n> + */\n> +struct BAR_PARAMS {\n> +\tdma_addr_t BAR_PHYS_ADDR; /**< Base physical address of BAR memory */\n> +\tunsigned long BAR_LENGTH; /**< Length of BAR memory window */\n> +\tvoid *BAR_VIRT_ADDR; /**< Virtual Address of mapped BAR memory */\n> +};\n> +\n> +/**\n> + * struct ps_pcie_dma_channel_match - Match structure for dma clients\n> + * @pci_vendorid: PCIe Vendor id of PS PCIe DMA device\n> + * @pci_deviceid: PCIe Device id of PS PCIe DMA device\n> + * @board_number: Unique id to identify individual device in a system\n> + * @channel_number: Unique channel number of the device\n> + * @direction: DMA channel direction\n> + * @bar_params: Pointer to BAR_PARAMS for accessing application specific data\n> + */\n> +struct ps_pcie_dma_channel_match {\n> +\tu16 pci_vendorid;\n> +\tu16 pci_deviceid;\n> +\tu16 board_number;\n> +\tu16 channel_number;\n> +\tenum dma_data_direction direction;\n> +\tstruct BAR_PARAMS *bar_params;\n> +};\n> +\n> +#endif\n> \n\nThanks,\nMichal","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; 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\n\tTue, 19 Sep 2017 22:49:30 -0700 (PDT)","Reply-To":"monstr@monstr.eu","Subject":"Re: [PATCH v2 3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA\n\tdriver","To":"Ravi Shankar Jonnalagadda ,\n\tvinod.koul@intel.com, robh+dt@kernel.org, mark.rutland@arm.com,\n\tmichal.simek@xilinx.com, soren.brinkmann@xilinx.com,\n\tdan.j.williams@intel.com, bhelgaas@google.com, vjonnal@xilinx.com,\n\tlorenzo.pieralisi@arm.com, bharat.kumar.gogada@xilinx.com,\n\tdmaengine@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org,\n\tlinux-pci@vger.kernel.org, rgummal@xilinx.com","References":"<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>\n\t<1504873388-29195-4-git-send-email-vjonnal@xilinx.com>","From":"Michal Simek ","Message-ID":"<1e17381d-0e60-e563-4f74-96245fe00aaf@monstr.eu>","Date":"Wed, 20 Sep 2017 07:49:19 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.3.0","MIME-Version":"1.0","In-Reply-To":"<1504873388-29195-4-git-send-email-vjonnal@xilinx.com>","Content-Type":"multipart/signed; micalg=pgp-sha1;\n\tprotocol=\"application/pgp-signature\";\n\tboundary=\"XdTKFfbuBq9kglatFEa7htSw2crG8Q3Rv\"","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1775726,"web_url":"http://patchwork.ozlabs.org/comment/1775726/","msgid":"<20170926173207.GR30097@localhost>","list_archive_url":null,"date":"2017-09-26T17:32:07","subject":"Re: [PATCH v2 3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA\n\tdriver","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Fri, Sep 08, 2017 at 05:53:05PM +0530, Ravi Shankar Jonnalagadda wrote:\n\n> Adding support for ZynqmMP PS PCIe EP driver.\n> Adding support for ZynqmMP PS PCIe Root DMA driver.\n\n/s/Adding/Add/\n\nPlease descibe the dmaengines here so people can know what to expect.\n\n> Modifying Kconfig and Makefile to add the support.\n\nYou can remobe this\n\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> drivers/dma/Kconfig | 12 +++\n> drivers/dma/xilinx/Makefile | 2 +\n> drivers/dma/xilinx/ps_pcie.h | 44 +++++++++\n> drivers/dma/xilinx/ps_pcie_main.c | 200 ++++++++++++++++++++++++++++++++++++++\n> include/linux/dma/ps_pcie_dma.h | 69 +++++++++++++\n> 5 files changed, 327 insertions(+)\n> create mode 100644 drivers/dma/xilinx/ps_pcie.h\n> create mode 100644 drivers/dma/xilinx/ps_pcie_main.c\n> create mode 100644 include/linux/dma/ps_pcie_dma.h\n> \n> diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig\n> index fa8f9c0..e2fe4e5 100644\n> --- a/drivers/dma/Kconfig\n> +++ b/drivers/dma/Kconfig\n> @@ -586,6 +586,18 @@ config XILINX_ZYNQMP_DMA\n> \thelp\n> \t Enable support for Xilinx ZynqMP DMA controller.\n> \n> +config XILINX_PS_PCIE_DMA\n> +\ttristate \"Xilinx PS PCIe DMA support\"\n> +\tdepends on (PCI && X86_64 || ARM64)\n> +\tselect DMA_ENGINE\n> +\thelp\n> +\t Enable support for the Xilinx PS PCIe DMA engine present\n> +\t in recent Xilinx ZynqMP chipsets.\n> +\n> +\t Say Y here if you have such a chipset.\n> +\n> +\t If unsure, say N.\n\nCan you remove last two lines, they dont convey anything useful\n\n> +\n> config ZX_DMA\n> \ttristate \"ZTE ZX DMA support\"\n> \tdepends on ARCH_ZX || COMPILE_TEST\n> diff --git a/drivers/dma/xilinx/Makefile b/drivers/dma/xilinx/Makefile\n> index 9e91f8f..04f6f99 100644\n> --- a/drivers/dma/xilinx/Makefile\n> +++ b/drivers/dma/xilinx/Makefile\n> @@ -1,2 +1,4 @@\n> obj-$(CONFIG_XILINX_DMA) += xilinx_dma.o\n> obj-$(CONFIG_XILINX_ZYNQMP_DMA) += zynqmp_dma.o\n> +ps_pcie_dma-objs := ps_pcie_main.o ps_pcie_platform.o\n> +obj-$(CONFIG_XILINX_PS_PCIE_DMA) += ps_pcie_dma.o\n> diff --git a/drivers/dma/xilinx/ps_pcie.h b/drivers/dma/xilinx/ps_pcie.h\n> new file mode 100644\n> index 0000000..351f051\n> --- /dev/null\n> +++ b/drivers/dma/xilinx/ps_pcie.h\n> @@ -0,0 +1,44 @@\n> +/*\n> + * Xilinx PS PCIe DMA Engine platform header file\n> + *\n> + * Copyright (C) 2010-2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#ifndef __XILINX_PS_PCIE_H\n> +#define __XILINX_PS_PCIE_H\n> +\n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n> +#include \n\nDo you really need all these headers\n\n> +\n> +/**\n> + * dma_platform_driver_register - This will be invoked by module init\n> + *\n> + * Return: returns status of platform_driver_register\n> + */\n> +int dma_platform_driver_register(void);\n> +/**\n> + * dma_platform_driver_unregister - This will be invoked by module exit\n> + *\n> + * Return: returns void after unregustering platform driver\n\ntypo, please run spell checker & checkpatch on your patches\n\n> + */\n> +void dma_platform_driver_unregister(void);\n> +\n> +#endif\n> diff --git a/drivers/dma/xilinx/ps_pcie_main.c b/drivers/dma/xilinx/ps_pcie_main.c\n> new file mode 100644\n> index 0000000..4ccd8ef\n> --- /dev/null\n> +++ b/drivers/dma/xilinx/ps_pcie_main.c\n> @@ -0,0 +1,200 @@\n> +/*\n> + * XILINX PS PCIe driver\n> + *\n> + * Copyright (C) 2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * Description\n> + * PS PCIe DMA is memory mapped DMA used to execute PS to PL transfers\n> + * on ZynqMP UltraScale+ Devices.\n> + * This PCIe driver creates a platform device with specific platform\n> + * info enabling creation of DMA device corresponding to the channel\n> + * information provided in the properties\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#include \"ps_pcie.h\"\n> +#include \"../dmaengine.h\"\n> +\n> +#define DRV_MODULE_NAME\t\t \"ps_pcie_dma\"\n> +\n> +static int ps_pcie_dma_probe(struct pci_dev *pdev,\n> +\t\t\t const struct pci_device_id *ent);\n> +static void ps_pcie_dma_remove(struct pci_dev *pdev);\n\nwhy do you need fwd declarations of these?\n\n> +\n> +static u32 channel_properties_pcie_axi[] = {\n> +\t(u32)(PCIE_AXI_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),\n> +\t(u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),\n> +\t(u32)(CHANNEL_POLL_TIMER_FREQUENCY) };\n\nwhy the casts?\n\n> +\n> +static u32 channel_properties_axi_pcie[] = {\n> +\t(u32)(AXI_PCIE_DIRECTION), (u32)(NUMBER_OF_BUFFER_DESCRIPTORS),\n> +\t(u32)(DEFAULT_DMA_QUEUES), (u32)(CHANNEL_COAELSE_COUNT),\n> +\t(u32)(CHANNEL_POLL_TIMER_FREQUENCY) };\n> +\n> +static struct property_entry generic_pcie_ep_property[] = {\n> +\tPROPERTY_ENTRY_U32(\"numchannels\", (u32)MAX_NUMBER_OF_CHANNELS),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel0\",\n> +\t\t\t\t channel_properties_pcie_axi),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel1\",\n> +\t\t\t\t channel_properties_axi_pcie),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel2\",\n> +\t\t\t\t channel_properties_pcie_axi),\n> +\tPROPERTY_ENTRY_U32_ARRAY(\"ps_pcie_channel3\",\n> +\t\t\t\t channel_properties_axi_pcie),\n> +\t{ },\n> +};\n> +\n> +static const struct platform_device_info xlnx_std_platform_dev_info = {\n> +\t.name = XLNX_PLATFORM_DRIVER_NAME,\n> +\t.properties = generic_pcie_ep_property,\n> +};\n> +\n> +/**\n> + * ps_pcie_dma_probe - Driver probe function\n> + * @pdev: Pointer to the pci_dev structure\n> + * @ent: pci device id\n> + *\n> + * Return: '0' on success and failure value on error\n> + */\n\nI didnt get any useful info from this, pls get rid of these where they dont\nhelp anyone...\n\n> +static int ps_pcie_dma_probe(struct pci_dev *pdev,\n> +\t\t\t const struct pci_device_id *ent)\n> +{\n> +\tint err;\n> +\tstruct platform_device *platform_dev;\n> +\tstruct platform_device_info platform_dev_info;\n\nhelps reading if these are reverse christmas tree!\n\n> +\n> +\tdev_info(&pdev->dev, \"PS PCIe DMA Driver probe\\n\");\n\nuseless, pls remove\n\n> +\n> +\terr = pcim_enable_device(pdev);\n> +\tif (err) {\n> +\t\tdev_err(&pdev->dev, \"Cannot enable PCI device, aborting\\n\");\n> +\t\treturn err;\n> +\t}\n> +\n> +\terr = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));\n> +\tif (err) {\n> +\t\tdev_info(&pdev->dev, \"Cannot set 64 bit DMA mask\\n\");\n> +\t\terr = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));\n> +\t\tif (err) {\n> +\t\t\tdev_err(&pdev->dev, \"DMA mask set error\\n\");\n\nno disable device on err?\n\n> +\t\t\treturn err;\n> +\t\t}\n> +\t}\n> +\n> +\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));\n> +\tif (err) {\n> +\t\tdev_info(&pdev->dev, \"Cannot set 64 bit consistent DMA mask\\n\");\n> +\t\terr = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));\n> +\t\tif (err) {\n> +\t\t\tdev_err(&pdev->dev, \"Cannot set consistent DMA mask\\n\");\n> +\t\t\treturn err;\n> +\t\t}\n> +\t}\n> +\n> +\tpci_set_master(pdev);\n> +\n> +\t/* For Root DMA platform device will be created through device tree */\n> +\tif (pdev->vendor == PCI_VENDOR_ID_XILINX &&\n> +\t pdev->device == ZYNQMP_RC_DMA_DEVID)\n> +\t\treturn 0;\n\nthe indentations are terrible!\n\nWhy regiser for this ID then? Return 0 would be success, so not sure what\nyou are trying to do here?\n\n\n> +\n> +\tmemcpy(&platform_dev_info, &xlnx_std_platform_dev_info,\n> +\t sizeof(xlnx_std_platform_dev_info));\n> +\n> +\t/* Do device specific channel configuration changes to\n> +\t * platform_dev_info.properties if required\n> +\t * More information on channel properties can be found\n> +\t * at Documentation/devicetree/bindings/dma/xilinx/ps-pcie-dma.txt\n> +\t */\n\n/*\n * kernel code expects multiline\n * comments like this\n */\n\n> +\n> +\tplatform_dev_info.parent = &pdev->dev;\n> +\tplatform_dev_info.data = &pdev;\n> +\tplatform_dev_info.size_data = sizeof(struct pci_dev **);\n\n??\n\n> +\n> +\tplatform_dev = platform_device_register_full(&platform_dev_info);\n> +\tif (IS_ERR(platform_dev)) {\n> +\t\tdev_err(&pdev->dev,\n> +\t\t\t\"Cannot create platform device, aborting\\n\");\n> +\t\treturn PTR_ERR(platform_dev);\n> +\t}\n> +\n> +\tpci_set_drvdata(pdev, platform_dev);\n> +\n> +\tdev_info(&pdev->dev, \"PS PCIe DMA driver successfully probed\\n\");\n> +\n> +\treturn 0;\n> +}\n> +\n> +static struct pci_device_id ps_pcie_dma_tbl[] = {\n> +\t{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, ZYNQMP_DMA_DEVID) },\n> +\t{ PCI_DEVICE(PCI_VENDOR_ID_XILINX, ZYNQMP_RC_DMA_DEVID) },\n> +\t{ }\n> +};\n> +\n> +static struct pci_driver ps_pcie_dma_driver = {\n> +\t.name = DRV_MODULE_NAME,\n> +\t.id_table = ps_pcie_dma_tbl,\n> +\t.probe = ps_pcie_dma_probe,\n> +\t.remove = ps_pcie_dma_remove,\n> +};\n> +\n> +/**\n> + * ps_pcie_init - Driver init function\n> + *\n> + * Return: 0 on success. Non zero on failure\n> + */\n> +static int __init ps_pcie_init(void)\n> +{\n> +\tint ret;\n> +\n> +\tpr_info(\"%s init()\\n\", DRV_MODULE_NAME);\n> +\n> +\tret = pci_register_driver(&ps_pcie_dma_driver);\n> +\tif (ret)\n> +\t\treturn ret;\n> +\n> +\tret = dma_platform_driver_register();\n> +\tif (ret)\n> +\t\tpci_unregister_driver(&ps_pcie_dma_driver);\n> +\n> +\treturn ret;\n> +}\n> +\n> +/**\n> + * ps_pcie_dma_remove - Driver remove function\n> + * @pdev: Pointer to the pci_dev structure\n> + *\n> + * Return: void\n> + */\n> +static void ps_pcie_dma_remove(struct pci_dev *pdev)\n> +{\n> +\tstruct platform_device *platform_dev;\n> +\n> +\tplatform_dev = (struct platform_device *)pci_get_drvdata(pdev);\n\nno need to cast from void\n\n> +\n> +\tif (platform_dev)\n> +\t\tplatform_device_unregister(platform_dev);\n> +}\n> +\n> +/**\n> + * ps_pcie_exit - Driver exit function\n> + *\n> + * Return: void\n> + */\n> +static void __exit ps_pcie_exit(void)\n> +{\n> +\tpr_info(\"%s exit()\\n\", DRV_MODULE_NAME);\n> +\n> +\tdma_platform_driver_unregister();\n> +\tpci_unregister_driver(&ps_pcie_dma_driver);\n> +}\n> +\n> +module_init(ps_pcie_init);\n> +module_exit(ps_pcie_exit);\n> +\n> +MODULE_AUTHOR(\"Xilinx Inc\");\n> +MODULE_DESCRIPTION(\"Xilinx PS PCIe DMA Driver\");\n> +MODULE_LICENSE(\"GPL v2\");\n> diff --git a/include/linux/dma/ps_pcie_dma.h b/include/linux/dma/ps_pcie_dma.h\n> new file mode 100644\n> index 0000000..d11323a\n> --- /dev/null\n> +++ b/include/linux/dma/ps_pcie_dma.h\n> @@ -0,0 +1,69 @@\n> +/*\n> + * Xilinx PS PCIe DMA Engine support header file\n> + *\n> + * Copyright (C) 2017 Xilinx, Inc. All rights reserved.\n> + *\n> + * This program is free software: you can redistribute it and/or modify\n> + * it under the terms of the GNU General Public License version 2 as\n> + * published by the Free Software Foundation\n> + */\n> +\n> +#ifndef __DMA_XILINX_PS_PCIE_H\n> +#define __DMA_XILINX_PS_PCIE_H\n> +\n> +#include \n> +#include \n> +\n> +#define XLNX_PLATFORM_DRIVER_NAME \"xlnx-platform-dma-driver\"\n> +\n> +#define ZYNQMP_DMA_DEVID\t(0xD024)\n> +#define ZYNQMP_RC_DMA_DEVID\t(0xD021)\n> +\n> +#define MAX_ALLOWED_CHANNELS_IN_HW\t4\n> +\n> +#define MAX_NUMBER_OF_CHANNELS\tMAX_ALLOWED_CHANNELS_IN_HW\n> +\n> +#define DEFAULT_DMA_QUEUES\t4\n> +#define TWO_DMA_QUEUES\t\t2\n> +\n> +#define NUMBER_OF_BUFFER_DESCRIPTORS\t1999\n> +#define MAX_DESCRIPTORS\t\t\t65536\n> +\n> +#define CHANNEL_COAELSE_COUNT\t\t0\n> +\n> +#define CHANNEL_POLL_TIMER_FREQUENCY\t1000 /* in milli seconds */\n> +\n> +#define PCIE_AXI_DIRECTION\tDMA_TO_DEVICE\n> +#define AXI_PCIE_DIRECTION\tDMA_FROM_DEVICE\n> +\n> +/**\n> + * struct BAR_PARAMS - PCIe Bar Parameters\n> + * @BAR_PHYS_ADDR: PCIe BAR Physical address\n> + * @BAR_LENGTH: Length of PCIe BAR\n> + * @BAR_VIRT_ADDR: Virtual Address to access PCIe BAR\n> + */\n> +struct BAR_PARAMS {\n> +\tdma_addr_t BAR_PHYS_ADDR; /**< Base physical address of BAR memory */\n> +\tunsigned long BAR_LENGTH; /**< Length of BAR memory window */\n> +\tvoid *BAR_VIRT_ADDR; /**< Virtual Address of mapped BAR memory */\n\nokay you have same comment twice. What is with DAMN UPPER CASE\n\nIf you cannot do basic checks for patches, I also refuse to waste my time\nand review this any further!","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1nwg0M3fz9sCZ\n\tfor ;\n\tWed, 27 Sep 2017 03:28:19 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S965047AbdIZR2R (ORCPT );\n\tTue, 26 Sep 2017 13:28:17 -0400","from mga09.intel.com ([134.134.136.24]:59938 \"EHLO mga09.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S937278AbdIZR2P (ORCPT );\n\tTue, 26 Sep 2017 13:28:15 -0400","from fmsmga004.fm.intel.com ([10.253.24.48])\n\tby orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384;\n\t26 Sep 2017 10:28:14 -0700","from vkoul-udesk7.iind.intel.com (HELO localhost) ([10.223.84.143])\n\tby fmsmga004.fm.intel.com with ESMTP; 26 Sep 2017 10:28:09 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,441,1500966000\"; d=\"scan'208\";a=\"316448208\"","Date":"Tue, 26 Sep 2017 23:02:07 +0530","From":"Vinod Koul ","To":"Ravi Shankar Jonnalagadda ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com,\n\tsoren.brinkmann@xilinx.com, dan.j.williams@intel.com,\n\tbhelgaas@google.com, vjonnal@xilinx.com, lorenzo.pieralisi@arm.com,\n\tbharat.kumar.gogada@xilinx.com, dmaengine@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n\trgummal@xilinx.com","Subject":"Re: [PATCH v2 3/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe DMA\n\tdriver","Message-ID":"<20170926173207.GR30097@localhost>","References":"<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>\n\t<1504873388-29195-4-git-send-email-vjonnal@xilinx.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504873388-29195-4-git-send-email-vjonnal@xilinx.com>","User-Agent":"Mutt/1.5.24 (2015-08-30)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}},{"id":1775732,"web_url":"http://patchwork.ozlabs.org/comment/1775732/","msgid":"<20170926173435.GS30097@localhost>","list_archive_url":null,"date":"2017-09-26T17:34:35","subject":"Re: [PATCH v2 4/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe\n\tplatform DMA driver","submitter":{"id":8232,"url":"http://patchwork.ozlabs.org/api/people/8232/","name":"Vinod Koul","email":"vinod.koul@intel.com"},"content":"On Fri, Sep 08, 2017 at 05:53:07PM +0530, Ravi Shankar Jonnalagadda wrote:\n> Platform driver handles transactions for PCIe EP DMA and Root DMA\n> \n> Signed-off-by: Ravi Shankar Jonnalagadda \n> Signed-off-by: RaviKiran Gummaluri \n> ---\n> drivers/dma/xilinx/ps_pcie_platform.c | 3055 +++++++++++++++++++++++++++++++++\n\nI dont want to loose my sanity trying to review a 3k patch. If you don't put\nan effort to make your code easier to review, I dont want to see this...\n\nNacked-by: Vinod Koul ","headers":{"Return-Path":"","X-Original-To":"incoming-dt@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming-dt@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=)","Received":["from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1nzX1BcKz9t1G\n\tfor ;\n\tWed, 27 Sep 2017 03:30:48 +1000 (AEST)","(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S969334AbdIZRaq (ORCPT );\n\tTue, 26 Sep 2017 13:30:46 -0400","from mga06.intel.com ([134.134.136.31]:38869 \"EHLO mga06.intel.com\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S968060AbdIZRap (ORCPT );\n\tTue, 26 Sep 2017 13:30:45 -0400","from orsmga002.jf.intel.com ([10.7.209.21])\n\tby orsmga104.jf.intel.com with ESMTP; 26 Sep 2017 10:30:44 -0700","from vkoul-udesk7.iind.intel.com (HELO localhost) ([10.223.84.143])\n\tby orsmga002.jf.intel.com with ESMTP; 26 Sep 2017 10:30:39 -0700"],"X-ExtLoop1":"1","X-IronPort-AV":"E=Sophos;i=\"5.42,441,1500966000\"; d=\"scan'208\";a=\"139673241\"","Date":"Tue, 26 Sep 2017 23:04:35 +0530","From":"Vinod Koul ","To":"Ravi Shankar Jonnalagadda ","Cc":"robh+dt@kernel.org, mark.rutland@arm.com, michal.simek@xilinx.com,\n\tsoren.brinkmann@xilinx.com, dan.j.williams@intel.com,\n\tbhelgaas@google.com, vjonnal@xilinx.com, lorenzo.pieralisi@arm.com,\n\tbharat.kumar.gogada@xilinx.com, dmaengine@vger.kernel.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n\trgummal@xilinx.com","Subject":"Re: [PATCH v2 4/5] dmaengine: zynqmp_ps_pcie: Adding PS PCIe\n\tplatform DMA driver","Message-ID":"<20170926173435.GS30097@localhost>","References":"<1504873388-29195-1-git-send-email-vjonnal@xilinx.com>\n\t<1504873388-29195-6-git-send-email-vjonnal@xilinx.com>","MIME-Version":"1.0","Content-Type":"text/plain; charset=us-ascii","Content-Disposition":"inline","In-Reply-To":"<1504873388-29195-6-git-send-email-vjonnal@xilinx.com>","User-Agent":"Mutt/1.5.24 (2015-08-30)","Sender":"devicetree-owner@vger.kernel.org","Precedence":"bulk","List-ID":"","X-Mailing-List":"devicetree@vger.kernel.org"}}]