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{ "id": 810009, "url": "http://patchwork.ozlabs.org/api/covers/810009/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/20170905084306.19318-1-mperttunen@nvidia.com/", "project": { "id": 37, "url": "http://patchwork.ozlabs.org/api/projects/37/?format=api", "name": "Devicetree Bindings", "link_name": "devicetree-bindings", "list_id": "devicetree.vger.kernel.org", "list_email": "devicetree@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170905084306.19318-1-mperttunen@nvidia.com>", "list_archive_url": null, "date": "2017-09-05T08:43:00", "name": "[v2,0/6] Host1x and VIC support for Tegra186", "submitter": { "id": 26499, "url": "http://patchwork.ozlabs.org/api/people/26499/?format=api", "name": "Mikko Perttunen", "email": "mperttunen@nvidia.com" }, "mbox": "http://patchwork.ozlabs.org/project/devicetree-bindings/cover/20170905084306.19318-1-mperttunen@nvidia.com/mbox/", "series": [ { "id": 1516, "url": "http://patchwork.ozlabs.org/api/series/1516/?format=api", "web_url": "http://patchwork.ozlabs.org/project/devicetree-bindings/list/?series=1516", "date": "2017-09-05T08:43:04", "name": "Host1x and VIC support for Tegra186", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/1516/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/810009/comments/", "headers": { "Return-Path": "<devicetree-owner@vger.kernel.org>", "X-Original-To": "incoming-dt@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming-dt@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=devicetree-owner@vger.kernel.org; receiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tsecure) header.d=kapsi.fi header.i=@kapsi.fi header.b=\"gyKFXAqL\"; \n\tdkim-atps=neutral" ], "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xmgK94Npxz9sNq\n\tfor <incoming-dt@patchwork.ozlabs.org>;\n\tTue, 5 Sep 2017 18:45:33 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751771AbdIEIoP (ORCPT\n\t<rfc822;incoming-dt@patchwork.ozlabs.org>);\n\tTue, 5 Sep 2017 04:44:15 -0400", "from mail.kapsi.fi ([91.232.154.25]:44200 \"EHLO mail.kapsi.fi\"\n\trhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP\n\tid S1750905AbdIEInp (ORCPT <rfc822;devicetree@vger.kernel.org>);\n\tTue, 5 Sep 2017 04:43:45 -0400", "from dsl-hkibng41-567306-181.dhcp.inet.fi ([86.115.6.181]\n\thelo=localhost.localdomain) by mail.kapsi.fi with esmtpsa\n\t(TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n\t(Exim 4.84_2) (envelope-from <mperttunen@nvidia.com>)\n\tid 1dp9SM-0005vW-70; Tue, 05 Sep 2017 11:43:38 +0300" ], "DKIM-Signature": "v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=kapsi.fi; \n\ts=20161220; h=Message-Id:Date:Subject:Cc:To:From;\n\tbh=tcsFx4n+7XoN3PxN5IPuN615kTEhNNj37qfDKB773G4=; \n\tb=gyKFXAqLicXuOAQLAz/PmdaUFOn4/UjHV9sHaTg+FX4tDyDVk73fJff+xIm0ZvCZIqExWTiA86Gt3n7u34+QXapuQmFgDWSU3N+U0S4pUUn6Zxau4ZpzFBhi6c4FXZ7qMeKmoRigGwlmJV0y/LOSD/Dx7ArC5S5kD4he23nyMdrJQtvHfVSLVL9FoObdgAKOYM8kcsVUlgeVoNmrYQiQCab+CXK+EjpjNtSKAT3Zt87cw8Gets0HsItkk/NPGtFrknySBnNu9BH6CS9A9WDB0CjFIknUAMtJ5zYiUf8ytr6sjXmVq8e3eoCKHtJgIf08umR02K9p6KjkCpPdIks8sQ==;", "From": "Mikko Perttunen <mperttunen@nvidia.com>", "To": "thierry.reding@gmail.com, jonathanh@nvidia.com, robh+dt@kernel.org,\n\tmark.rutland@arm.com", "Cc": "digetx@gmail.com, amerilainen@nvidia.com, dnibade@nvidia.com,\n\tsgurrappadi@nvidia.com, dri-devel@lists.freedesktop.org,\n\tdevicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tlinux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,\n\tMikko Perttunen <mperttunen@nvidia.com>", "Subject": "[PATCH v2 0/6] Host1x and VIC support for Tegra186", "Date": "Tue, 5 Sep 2017 11:43:00 +0300", "Message-Id": "<20170905084306.19318-1-mperttunen@nvidia.com>", "X-Mailer": "git-send-email 2.14.1", "X-SA-Exim-Connect-IP": "86.115.6.181", "X-SA-Exim-Mail-From": "mperttunen@nvidia.com", "X-SA-Exim-Scanned": "No (on mail.kapsi.fi); SAEximRunCond expanded to false", "Sender": "devicetree-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<devicetree.vger.kernel.org>", "X-Mailing-List": "devicetree@vger.kernel.org" }, "content": "Hi,\n\nnot many changes in v2:\n\nChanged address-cells and size-cells for the Host1x device tree node\nto have value 1, since all subdevices fit in the lower 4G. Also dropped\nthe incorrect change about this from the dt-bindings patch. Thanks to\nRob for pointing this out.\n\nMikko\n\nNotes for v1:\n\nHi everyone,\n\nthis series adds basic support for the Host1x channel engine and the\nVIC 2d compositor unit on Tegra186. The first three patches do the\nrequired device tree changes, the fourth patch updates the device tree\nbinding documentation, and the two remaining patches add the actual\nimplementation, almost all of which is in Host1x itself.\n\nThe Tegra186 Host1x is a relatively large update over previous\ngenerations, which can be seen in the diffstat. The biggest change is\nthat Host1x is now contains separate hypervisor and vm register\napertures to support virtualization at the hardware level. This driver,\nhowever, currently assumes that this instance of Linux is the sole\noperating system having access to the hardware.\n\nThis combined with increased numbers of supported channels and\nsyncpoints have caused a number of register space changes that are\nresponsible for most of the updated code.\n\nThe series has been tested on the Jetson TX1 (T210) and TX2 (T186)\nusing the host1x_test test suite available at\n\nhttp://github.com/cyndis/host1x_test\n\nThe series itself is available at\n\nhttp://github.com/cyndis/linux, branch host1x-t186-1\n\nCheers,\nMikko\n\nMikko Perttunen (6):\n arm64: tegra: Add #power-domain-cells for BPMP\n arm64: tegra: Add host1x on Tegra186\n arm64: tegra: Add VIC on Tegra186\n dt-bindings: host1x: Add Tegra186 information\n gpu: host1x: Add Tegra186 support\n drm/tegra: Add Tegra186 support for VIC\n\n .../display/tegra/nvidia,tegra20-host1x.txt | 4 +\n arch/arm64/boot/dts/nvidia/tegra186.dtsi | 31 ++++\n drivers/gpu/drm/tegra/drm.c | 1 +\n drivers/gpu/drm/tegra/vic.c | 10 ++\n drivers/gpu/host1x/Makefile | 3 +-\n drivers/gpu/host1x/dev.c | 60 ++++++-\n drivers/gpu/host1x/dev.h | 4 +\n drivers/gpu/host1x/hw/cdma_hw.c | 49 +++---\n drivers/gpu/host1x/hw/debug_hw.c | 137 +---------------\n drivers/gpu/host1x/hw/debug_hw_1x01.c | 154 ++++++++++++++++++\n drivers/gpu/host1x/hw/debug_hw_1x06.c | 133 +++++++++++++++\n drivers/gpu/host1x/hw/host1x01.c | 2 +\n drivers/gpu/host1x/hw/host1x02.c | 2 +\n drivers/gpu/host1x/hw/host1x04.c | 2 +\n drivers/gpu/host1x/hw/host1x05.c | 2 +\n drivers/gpu/host1x/hw/host1x06.c | 44 +++++\n drivers/gpu/host1x/hw/host1x06.h | 26 +++\n drivers/gpu/host1x/hw/host1x06_hardware.h | 142 ++++++++++++++++\n drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h | 32 ++++\n drivers/gpu/host1x/hw/hw_host1x06_uclass.h | 181 +++++++++++++++++++++\n drivers/gpu/host1x/hw/hw_host1x06_vm.h | 47 ++++++\n drivers/gpu/host1x/hw/intr_hw.c | 29 ++--\n 22 files changed, 926 insertions(+), 169 deletions(-)\n create mode 100644 drivers/gpu/host1x/hw/debug_hw_1x01.c\n create mode 100644 drivers/gpu/host1x/hw/debug_hw_1x06.c\n create mode 100644 drivers/gpu/host1x/hw/host1x06.c\n create mode 100644 drivers/gpu/host1x/hw/host1x06.h\n create mode 100644 drivers/gpu/host1x/hw/host1x06_hardware.h\n create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_hypervisor.h\n create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_uclass.h\n create mode 100644 drivers/gpu/host1x/hw/hw_host1x06_vm.h" }