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{ "id": 806603, "url": "http://patchwork.ozlabs.org/api/covers/806603/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/cover/20170828142307.30061-1-l.stach@pengutronix.de/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170828142307.30061-1-l.stach@pengutronix.de>", "list_archive_url": null, "date": "2017-08-28T14:23:04", "name": "[0/3] DWC host without MSI controller", "submitter": { "id": 23583, "url": "http://patchwork.ozlabs.org/api/people/23583/?format=api", "name": "Lucas Stach", "email": "l.stach@pengutronix.de" }, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/cover/20170828142307.30061-1-l.stach@pengutronix.de/mbox/", "series": [ { "id": 182, "url": "http://patchwork.ozlabs.org/api/series/182/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=182", "date": "2017-08-28T14:23:05", "name": "DWC host without MSI controller", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/182/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/806603/comments/", "headers": { "Return-Path": "<linux-pci-owner@vger.kernel.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=vger.kernel.org\n\t(client-ip=209.132.180.67; helo=vger.kernel.org;\n\tenvelope-from=linux-pci-owner@vger.kernel.org;\n\treceiver=<UNKNOWN>)", "Received": [ "from vger.kernel.org (vger.kernel.org [209.132.180.67])\n\tby ozlabs.org (Postfix) with ESMTP id 3xgvBb2DZBz9sQl\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 29 Aug 2017 00:23:19 +1000 (AEST)", "(majordomo@vger.kernel.org) by vger.kernel.org via listexpand\n\tid S1751302AbdH1OXQ (ORCPT <rfc822;incoming@patchwork.ozlabs.org>);\n\tMon, 28 Aug 2017 10:23:16 -0400", "from metis.ext.4.pengutronix.de ([92.198.50.35]:50553 \"EHLO\n\tmetis.ext.4.pengutronix.de\" rhost-flags-OK-OK-OK-OK)\n\tby vger.kernel.org with ESMTP id S1751170AbdH1OXM (ORCPT\n\t<rfc822; linux-pci@vger.kernel.org>); Mon, 28 Aug 2017 10:23:12 -0400", "from dude.hi.pengutronix.de ([2001:67c:670:100:1d::7]\n\thelo=dude.pengutronix.de.)\n\tby metis.ext.pengutronix.de with esmtp (Exim 4.84_2)\n\t(envelope-from <l.stach@pengutronix.de>)\n\tid 1dmKwX-0005gz-7C; Mon, 28 Aug 2017 16:23:09 +0200" ], "From": "Lucas Stach <l.stach@pengutronix.de>", "To": "Bjorn Helgaas <bhelgaas@google.com>, Tim Harvey <tharvey@gateworks.com>,\n\tJingoo Han <jingoohan1@gmail.com>, Joao Pinto <Joao.Pinto@synopsys.com>,\n\tShawn Guo <shawnguo@kernel.org>", "Cc": "linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,\n\tpatchwork-lst@pengutronix.de, kernel@pengutronix.de", "Subject": "[PATCH 0/3] DWC host without MSI controller", "Date": "Mon, 28 Aug 2017 16:23:04 +0200", "Message-Id": "<20170828142307.30061-1-l.stach@pengutronix.de>", "X-Mailer": "git-send-email 2.11.0", "X-SA-Exim-Connect-IP": "2001:67c:670:100:1d::7", "X-SA-Exim-Mail-From": "l.stach@pengutronix.de", "X-SA-Exim-Scanned": "No (on metis.ext.pengutronix.de);\n\tSAEximRunCond expanded to false", "X-PTX-Original-Recipient": "linux-pci@vger.kernel.org", "Sender": "linux-pci-owner@vger.kernel.org", "Precedence": "bulk", "List-ID": "<linux-pci.vger.kernel.org>", "X-Mailing-List": "linux-pci@vger.kernel.org" }, "content": "Hi all,\n\nthis small series tries to fix/workaround a serious design flaw of the DWC PCIe\nhost controller: it is unable to work with both legacy and MSI IRQs enabled at\nthe same time. As soon as the first MSI is enabled in the DWC MSI controller,\nthe host stops forwarding legacy IRQs.\n\nIf the MSI controller is present, MSIs will be used for the PCIe port services\nIRQs, leaving endpoint devices which don't support MSIs unable to raise IRQs.\nIt is only safe to enable the MSI controller if it is validated that all PCIe\ndevices and drivers in the system support working MSIs. As most devices\nsupport falling back to using legacy PCIe IRQs if MSI support is missing it is\nmuch safer to disable the MSI by default and only enable it on validated\nsystems.\n\nFeedback welcome.\n\nRegards,\nLucas\n\nLucas Stach (3):\n PCI: designware: only register MSI controller when MSI irq line is\n valid\n PCI: imx6: allow MSI irq to be absent\n ARM: dts: imx6qdl: remove MSI irq line\n\n .../devicetree/bindings/pci/fsl,imx6q-pcie.txt | 8 ++++----\n arch/arm/boot/dts/imx6qdl.dtsi | 2 --\n drivers/pci/dwc/pci-imx6.c | 23 +++++++++++-----------\n drivers/pci/dwc/pcie-designware-host.c | 4 ++--\n 4 files changed, 17 insertions(+), 20 deletions(-)" }