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{ "id": 2219157, "url": "http://patchwork.ozlabs.org/api/covers/2219157/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260402125234.1371897-1-max.chou@sifive.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260402125234.1371897-1-max.chou@sifive.com>", "list_archive_url": null, "date": "2026-04-02T12:52:25", "name": "[v6,0/9] Add Zvfbfa extension support", "submitter": { "id": 86650, "url": "http://patchwork.ozlabs.org/api/people/86650/?format=api", "name": "Max Chou", "email": "max.chou@sifive.com" }, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/cover/20260402125234.1371897-1-max.chou@sifive.com/mbox/", "series": [ { "id": 498485, "url": "http://patchwork.ozlabs.org/api/series/498485/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=498485", "date": "2026-04-02T12:52:26", "name": "Add Zvfbfa extension support", "version": 6, "mbox": "http://patchwork.ozlabs.org/series/498485/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/covers/2219157/comments/", "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=sifive.com header.i=@sifive.com header.a=rsa-sha256\n header.s=google header.b=QNiNKVO0;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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helo=mail-pj1-x102f.google.com", "X-Spam_score_int": "-20", "X-Spam_score": "-2.1", "X-Spam_bar": "--", "X-Spam_report": "(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "This patch series adds support for the RISC-V Zvfbfa extension, which\nprovides additional BF16 vector compute support.\n\nThe isa spec of Zvfbfa extension is not ratified yet, but is frozen\n(v0.9) with a tag in official riscv-isa-manual repository.\nThis patch series is based on the latest frozen draft of the Zvfbfa\nspec v0.9.\n\nThe Zvfbfa extension adds a 1-bit field, altfmt, to the vtype CSR in\nbit position 8.\nThe Zvfbfa extension requires the Zve32f and Zfbfmin extensions.\n\nSpecification:\nhttps://github.com/riscv/riscv-isa-manual/releases/tag/zvfbfa-0.9\n\nChanges in v6:\n- Remove the experimental `x-` prefix in cpu property.\n- Rebase to latest riscv-to-apply.next branch (commit 479e3e4)\n\nChanges in v5:\n- Fix typo in patch 1/5/8\n- Remove unnecessary do_bf16_nanbox\n\nChanges in v4:\n- Rebase on riscv-to-apply.next (commit 21101a7)\n- Update commit message of patch 2 (target/riscv: Add the Zvfbfa\n extension implied rule)\n- Update checking flow of illegal ALTFMT SEW patterns at patch 3\n (target/riscv: rvv: Add new VTYPE CSR field - altfmt)\n\nChanges in v3:\n- Rebased on riscv-to-apply.next (commit f66f234)\n- Fix typo in v2 patch 5 commit message\n\nChanges from v2:\n- Removed RFC designation from the series\n- Updated commit message for patch 3 (VTYPE CSR field -\n altfmt) to clearly explain:\n * VEDIV field removal (bits 8-9) since EDIV extension is not\n planned to be part of the base V extension\n * ALTFMT field addition at bit 8\n * RESERVED field change from bit 10 to bit 9\n- Added new patch 4: Introduce reset_ill_vtype helper function to\n consolidate illegal vtype CSR reset logic\n\nv4: <20260304132514.2889449-1-max.chou@sifive.com>\nv3: <20260127014227.406653-1-max.chou@sifive.com>\nv2: <20260108132631.9429-1-max.chou@sifive.com>\nv1: <20250915084037.1816893-1-max.chou@sifive.com>\n\nrnax\n\n\nMax Chou (9):\n target/riscv: Add cfg properties for Zvfbfa extensions\n target/riscv: Add the Zvfbfa extension implied rule\n target/riscv: rvv: Add new VTYPE CSR field - altfmt\n target/riscv: rvv: Introduce reset_ill_vtype to reset illegal vtype\n CSR\n target/riscv: Use the tb->cs_base as the extend tb flags\n target/riscv: Introduce altfmt into DisasContext\n target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension\n target/riscv: rvv: Support Zvfbfa vector bf16 operations\n target/riscv: Expose Zvfbfa extension as a cpu property\n\n include/exec/translation-block.h | 1 +\n target/riscv/cpu.c | 15 +-\n target/riscv/cpu.h | 7 +-\n target/riscv/cpu_cfg_fields.h.inc | 1 +\n target/riscv/helper.h | 60 ++\n target/riscv/insn_trans/trans_rvv.c.inc | 988 +++++++++++++++---------\n target/riscv/internals.h | 1 +\n target/riscv/tcg/tcg-cpu.c | 15 +-\n target/riscv/translate.c | 11 +\n target/riscv/vector_helper.c | 389 +++++++++-\n 10 files changed, 1088 insertions(+), 400 deletions(-)" }