[{"id":3675634,"web_url":"http://patchwork.ozlabs.org/comment/3675634/","msgid":"","list_archive_url":null,"date":"2026-04-10T03:25:02","subject":"Re: [PATCH v6 0/9] Add Zvfbfa extension support","submitter":{"id":64571,"url":"http://patchwork.ozlabs.org/api/people/64571/","name":"Alistair Francis","email":"alistair23@gmail.com"},"content":"On Thu, Apr 2, 2026 at 11:50 PM Max Chou wrote:\n>\n> This patch series adds support for the RISC-V Zvfbfa extension, which\n> provides additional BF16 vector compute support.\n>\n> The isa spec of Zvfbfa extension is not ratified yet, but is frozen\n> (v0.9) with a tag in official riscv-isa-manual repository.\n> This patch series is based on the latest frozen draft of the Zvfbfa\n> spec v0.9.\n>\n> The Zvfbfa extension adds a 1-bit field, altfmt, to the vtype CSR in\n> bit position 8.\n> The Zvfbfa extension requires the Zve32f and Zfbfmin extensions.\n>\n> Specification:\n> https://github.com/riscv/riscv-isa-manual/releases/tag/zvfbfa-0.9\n>\n> Changes in v6:\n> - Remove the experimental `x-` prefix in cpu property.\n> - Rebase to latest riscv-to-apply.next branch (commit 479e3e4)\n>\n> Changes in v5:\n> - Fix typo in patch 1/5/8\n> - Remove unnecessary do_bf16_nanbox\n>\n> Changes in v4:\n> - Rebase on riscv-to-apply.next (commit 21101a7)\n> - Update commit message of patch 2 (target/riscv: Add the Zvfbfa\n> extension implied rule)\n> - Update checking flow of illegal ALTFMT SEW patterns at patch 3\n> (target/riscv: rvv: Add new VTYPE CSR field - altfmt)\n>\n> Changes in v3:\n> - Rebased on riscv-to-apply.next (commit f66f234)\n> - Fix typo in v2 patch 5 commit message\n>\n> Changes from v2:\n> - Removed RFC designation from the series\n> - Updated commit message for patch 3 (VTYPE CSR field -\n> altfmt) to clearly explain:\n> * VEDIV field removal (bits 8-9) since EDIV extension is not\n> planned to be part of the base V extension\n> * ALTFMT field addition at bit 8\n> * RESERVED field change from bit 10 to bit 9\n> - Added new patch 4: Introduce reset_ill_vtype helper function to\n> consolidate illegal vtype CSR reset logic\n>\n> v4: <20260304132514.2889449-1-max.chou@sifive.com>\n> v3: <20260127014227.406653-1-max.chou@sifive.com>\n> v2: <20260108132631.9429-1-max.chou@sifive.com>\n> v1: <20250915084037.1816893-1-max.chou@sifive.com>\n>\n> rnax\n>\n>\n> Max Chou (9):\n> target/riscv: Add cfg properties for Zvfbfa extensions\n> target/riscv: Add the Zvfbfa extension implied rule\n> target/riscv: rvv: Add new VTYPE CSR field - altfmt\n> target/riscv: rvv: Introduce reset_ill_vtype to reset illegal vtype\n> CSR\n> target/riscv: Use the tb->cs_base as the extend tb flags\n> target/riscv: Introduce altfmt into DisasContext\n> target/riscv: Introduce BF16 canonical NaN for Zvfbfa extension\n> target/riscv: rvv: Support Zvfbfa vector bf16 operations\n> target/riscv: Expose Zvfbfa extension as a cpu property\n\nThanks!\n\nApplied to riscv-to-apply.next\n\nAlistair\n\n>\n> include/exec/translation-block.h | 1 +\n> target/riscv/cpu.c | 15 +-\n> target/riscv/cpu.h | 7 +-\n> target/riscv/cpu_cfg_fields.h.inc | 1 +\n> target/riscv/helper.h | 60 ++\n> target/riscv/insn_trans/trans_rvv.c.inc | 988 +++++++++++++++---------\n> target/riscv/internals.h | 1 +\n> target/riscv/tcg/tcg-cpu.c | 15 +-\n> target/riscv/translate.c | 11 +\n> target/riscv/vector_helper.c | 389 +++++++++-\n> 10 files changed, 1088 insertions(+), 400 deletions(-)\n>\n> --\n> 2.52.0\n>\n>","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=NE8CdIWT;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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Thu, 09 Apr 2026\n 20:25:28 -0700 (PDT)","MIME-Version":"1.0","References":"<20260402125234.1371897-1-max.chou@sifive.com>","In-Reply-To":"<20260402125234.1371897-1-max.chou@sifive.com>","From":"Alistair Francis ","Date":"Fri, 10 Apr 2026 13:25:02 +1000","X-Gm-Features":"AQROBzBGG14qawWPI27eYzGYD00-L67phPBckcOwb8PXlUhwAddjoVgPByy9lxM","Message-ID":"\n ","Subject":"Re: [PATCH v6 0/9] Add Zvfbfa extension support","To":"Max Chou ","Cc":"qemu-devel@nongnu.org, qemu-riscv@nongnu.org,\n Palmer Dabbelt ,\n Alistair Francis ,\n Weiwei Li ,\n Daniel Henrique Barboza ,\n Liu Zhiwei ,\n Chao Liu ","Content-Type":"text/plain; charset=\"UTF-8\"","Content-Transfer-Encoding":"quoted-printable","Received-SPF":"pass client-ip=2a00:1450:4864:20::62f;\n envelope-from=alistair23@gmail.com; helo=mail-ej1-x62f.google.com","X-Spam_score_int":"-17","X-Spam_score":"-1.8","X-Spam_bar":"-","X-Spam_report":"(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}}]