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GET /api/1.2/patches/814770/?format=api
HTTP 200 OK
Allow: GET, PUT, PATCH, HEAD, OPTIONS
Content-Type: application/json
Vary: Accept

{
    "id": 814770,
    "url": "http://patchwork.ozlabs.org/api/1.2/patches/814770/?format=api",
    "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/20170918042157.19062-1-stewart@linux.vnet.ibm.com/",
    "project": {
        "id": 44,
        "url": "http://patchwork.ozlabs.org/api/1.2/projects/44/?format=api",
        "name": "skiboot firmware development",
        "link_name": "skiboot",
        "list_id": "skiboot.lists.ozlabs.org",
        "list_email": "skiboot@lists.ozlabs.org",
        "web_url": "http://github.com/open-power/skiboot",
        "scm_url": "http://github.com/open-power/skiboot",
        "webscm_url": "",
        "list_archive_url": "",
        "list_archive_url_format": "",
        "commit_url_format": ""
    },
    "msgid": "<20170918042157.19062-1-stewart@linux.vnet.ibm.com>",
    "list_archive_url": null,
    "date": "2017-09-18T04:21:57",
    "name": "PHB4: Default to PCIe GEN3 on POWER9 DD2.00",
    "commit_ref": null,
    "pull_url": null,
    "state": "accepted",
    "archived": false,
    "hash": "b64caec61d4ac19239816b57f515ace82402ba37",
    "submitter": {
        "id": 48041,
        "url": "http://patchwork.ozlabs.org/api/1.2/people/48041/?format=api",
        "name": "Stewart Smith",
        "email": "stewart@linux.vnet.ibm.com"
    },
    "delegate": null,
    "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/20170918042157.19062-1-stewart@linux.vnet.ibm.com/mbox/",
    "series": [
        {
            "id": 3558,
            "url": "http://patchwork.ozlabs.org/api/1.2/series/3558/?format=api",
            "web_url": "http://patchwork.ozlabs.org/project/skiboot/list/?series=3558",
            "date": "2017-09-18T04:21:57",
            "name": "PHB4: Default to PCIe GEN3 on POWER9 DD2.00",
            "version": 1,
            "mbox": "http://patchwork.ozlabs.org/series/3558/mbox/"
        }
    ],
    "comments": "http://patchwork.ozlabs.org/api/patches/814770/comments/",
    "check": "pending",
    "checks": "http://patchwork.ozlabs.org/api/patches/814770/checks/",
    "tags": {},
    "related": [],
    "headers": {
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            "from b03ledav005.gho.boulder.ibm.com\n\t(b03ledav005.gho.boulder.ibm.com [9.17.130.236])\n\tby b03cxnp08025.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v8I4M23d459014; Sun, 17 Sep 2017 21:22:02 -0700",
            "from b03ledav005.gho.boulder.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 88402BE039;\n\tSun, 17 Sep 2017 22:22:02 -0600 (MDT)",
            "from birb.localdomain (unknown [9.185.16.148])\n\tby b03ledav005.gho.boulder.ibm.com (Postfix) with ESMTP id 116CCBE03B;\n\tSun, 17 Sep 2017 22:22:02 -0600 (MDT)",
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        "From": "Stewart Smith <stewart@linux.vnet.ibm.com>",
        "To": "skiboot@lists.ozlabs.org",
        "Date": "Mon, 18 Sep 2017 14:21:57 +1000",
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        "Message-Id": "<20170918042157.19062-1-stewart@linux.vnet.ibm.com>",
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        "Subject": "[Skiboot] [PATCH] PHB4: Default to PCIe GEN3 on POWER9 DD2.00",
        "X-BeenThere": "skiboot@lists.ozlabs.org",
        "X-Mailman-Version": "2.1.24",
        "Precedence": "list",
        "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>",
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        "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org",
        "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>"
    },
    "content": "You can use the NVRAM override for DD2.00 screened parts.\n\nSigned-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>\n---\n hw/phb4.c | 6 ++++++\n 1 file changed, 6 insertions(+)",
    "diff": "diff --git a/hw/phb4.c b/hw/phb4.c\nindex fea9125699fe..5371949fd997 100644\n--- a/hw/phb4.c\n+++ b/hw/phb4.c\n@@ -4741,12 +4741,14 @@ static void phb4_create(struct dt_node *np)\n \tchar *path;\n \tuint32_t irq_base, irq_flags;\n \tint i;\n+\tstruct proc_chip *chip;\n \n \tassert(p);\n \n \t/* Populate base stuff */\n \tp->index = dt_prop_get_u32(np, \"ibm,phb-index\");\n \tp->chip_id = dt_prop_get_u32(np, \"ibm,chip-id\");\n+\tchip = get_chip(p->chip_id);\n \tp->regs = (void *)dt_get_address(np, 0, NULL);\n \tp->int_mmio = (void *)dt_get_address(np, 1, NULL);\n \tp->phb.dt_node = np;\n@@ -4833,6 +4835,10 @@ static void phb4_create(struct dt_node *np)\n \tp->max_link_speed = 4;\n \tif (p->rev == PHB4_REV_NIMBUS_DD10)\n \t\tp->max_link_speed = 2;\n+\tif (p->rev == PHB4_REV_NIMBUS_DD20 && chip->ec_rev == 0) {\n+\t\tp->max_link_speed = 3;\n+\t\tPHBINF(p, \"Default max link speed for P9 DD2.00 is GEN3\\n\");\n+\t}\n \tif (dt_has_node_property(np, \"ibm,max-link-speed\", NULL))\n \t\tp->max_link_speed = dt_prop_get_u32(np, \"ibm,max-link-speed\");\n \tif (pcie_max_link_speed)\n",
    "prefixes": []
}