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GET /api/1.2/patches/810716/?format=api
{ "id": 810716, "url": "http://patchwork.ozlabs.org/api/1.2/patches/810716/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-33-richard.henderson@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170906160612.22769-33-richard.henderson@linaro.org>", "list_archive_url": null, "date": "2017-09-06T16:06:12", "name": "[PULL,32/32] target/arm: Perform per-insn cross-page check only for Thumb", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "6bb1f8c249900826b1f93011aa3f4b8c5efe455f", "submitter": { "id": 72104, "url": "http://patchwork.ozlabs.org/api/1.2/people/72104/?format=api", "name": "Richard Henderson", "email": "richard.henderson@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20170906160612.22769-33-richard.henderson@linaro.org/mbox/", "series": [ { "id": 1847, "url": "http://patchwork.ozlabs.org/api/1.2/series/1847/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=1847", "date": "2017-09-06T16:05:41", "name": "[PULL,01/32] tcg: Add generic DISAS_NORETURN", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/1847/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/810716/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/810716/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (1024-bit key;\n\tunprotected) header.d=linaro.org header.i=@linaro.org\n\theader.b=\"WEZRS3Zj\"; dkim-atps=neutral" ], "Received": [ "from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xnTRy3wjrz9s7F\n\tfor <incoming@patchwork.ozlabs.org>;\n\tThu, 7 Sep 2017 02:24:14 +1000 (AEST)", "from localhost ([::1]:37027 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>)\n\tid 1dpd7c-0006IC-KA\n\tfor incoming@patchwork.ozlabs.org; Wed, 06 Sep 2017 12:24:12 -0400", "from eggs.gnu.org ([2001:4830:134:3::10]:42025)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqx-0000aP-Q8\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:07:09 -0400", "from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from <richard.henderson@linaro.org>) id 1dpcqw-0003A3-JE\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:59 -0400", "from mail-pg0-x22c.google.com ([2607:f8b0:400e:c05::22c]:37876)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from <richard.henderson@linaro.org>)\n\tid 1dpcqw-00038p-Dg\n\tfor qemu-devel@nongnu.org; Wed, 06 Sep 2017 12:06:58 -0400", "by mail-pg0-x22c.google.com with SMTP id d8so15976971pgt.4\n\tfor <qemu-devel@nongnu.org>; Wed, 06 Sep 2017 09:06:58 -0700 (PDT)", "from bigtime.twiddle.net (97-126-108-236.tukw.qwest.net.\n\t[97.126.108.236]) by smtp.gmail.com with ESMTPSA id\n\tt65sm262863pfk.59.2017.09.06.09.06.55\n\t(version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256);\n\tWed, 06 Sep 2017 09:06:56 -0700 (PDT)" ], "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=FcT2poeH+q1L1w+cKeuwQSS5u5zh9VSMqgupWpqmAAU=;\n\tb=WEZRS3Zj3SvIUobu2mj0kXoOJdlc+XtUNXXRUocuCXCAZJqyVlCBxmwo1khSzT91B4\n\t53Uv8i8fMyhrSlBKr8Ch0VNw97Q8igCw0HmWV45diW+iCNZ5Lm1kUSSith2UrcHnM94y\n\tvlW/3hmVWIZyD4UnqXfn/2bZMUgrfVsscsm7M=", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=FcT2poeH+q1L1w+cKeuwQSS5u5zh9VSMqgupWpqmAAU=;\n\tb=VSEcTrF3ckPeawb8guAkvWkJo4DU1jJHke5/e9z/wAZ/otOGfN6ocjGMppf4zYVB1q\n\tzH7DsazXR8wwggGdxAJQ1Q8uG4d7FNT6CptsOKcH5XNFDdA8hKdPGQ3UG5RfsDh1RBrZ\n\tFMIBZ+bUzdclpKra3aT4PyQ9rAfcyAGCTuM+1lbxC3w+woytHuVUzsIxtxKUcL1qdT3B\n\t2qJIYEps1Z48kA7GsfZxM41nlRflcPZBUhZ7L3C1yEXauRkSGWqrjvm7X6EYCZAU29Pd\n\t4h026RIlD3lrHz6Qc5cnO6AexqqCEPR+6ffbVvHK7TIkjTuW182dOLPHkvBTP8e6zfRV\n\tgHsg==", "X-Gm-Message-State": "AHPjjUjqVX05vtbDfUZthRAzVqGSRD0LOgT5HAtvM/fsM/gYTzVv8bmZ\n\tqnO6/9LxLiJgrtQushslgg==", "X-Google-Smtp-Source": "ADKCNb4cF16fLGKFoJyLYeJ/KvF8lFeCYeDOiMsbgS7lHT6WwCvBxdDZ3LOltSC4GIVcaDAtlUfykg==", "X-Received": "by 10.99.2.208 with SMTP id 199mr8129299pgc.441.1504714017250;\n\tWed, 06 Sep 2017 09:06:57 -0700 (PDT)", "From": "Richard Henderson <richard.henderson@linaro.org>", "To": "qemu-devel@nongnu.org", "Date": "Wed, 6 Sep 2017 09:06:12 -0700", "Message-Id": "<20170906160612.22769-33-richard.henderson@linaro.org>", "X-Mailer": "git-send-email 2.13.5", "In-Reply-To": "<20170906160612.22769-1-richard.henderson@linaro.org>", "References": "<20170906160612.22769-1-richard.henderson@linaro.org>", "X-detected-operating-system": "by eggs.gnu.org: Genre and OS details not\n\trecognized.", "X-Received-From": "2607:f8b0:400e:c05::22c", "Subject": "[Qemu-devel] [PULL 32/32] target/arm: Perform per-insn cross-page\n\tcheck only for Thumb", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.21", "Precedence": "list", "List-Id": "<qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<http://lists.nongnu.org/archive/html/qemu-devel/>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n\t<mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Cc": "peter.maydell@linaro.org, Richard Henderson <rth@twiddle.net>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "\"Qemu-devel\"\n\t<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>" }, "content": "From: Richard Henderson <rth@twiddle.net>\n\nARM is a fixed-length ISA and we can compute the page crossing\ncondition exactly once during init_disas_context.\n\nReviewed-by: Emilio G. Cota <cota@braap.org>\nSigned-off-by: Richard Henderson <rth@twiddle.net>\n---\n target/arm/translate.c | 58 ++++++++++++++++++++++++++++----------------------\n 1 file changed, 33 insertions(+), 25 deletions(-)", "diff": "diff --git a/target/arm/translate.c b/target/arm/translate.c\nindex 9e7bfbcf0c..6946e56a3a 100644\n--- a/target/arm/translate.c\n+++ b/target/arm/translate.c\n@@ -11888,6 +11888,13 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase,\n max_insns = 1;\n }\n \n+ /* ARM is a fixed-length ISA. Bound the number of insns to execute\n+ to those left on the page. */\n+ if (!dc->thumb) {\n+ int bound = (dc->next_page_start - dc->base.pc_first) / 4;\n+ max_insns = MIN(max_insns, bound);\n+ }\n+\n cpu_F0s = tcg_temp_new_i32();\n cpu_F1s = tcg_temp_new_i32();\n cpu_F0d = tcg_temp_new_i64();\n@@ -12015,34 +12022,12 @@ static bool arm_pre_translate_insn(DisasContext *dc)\n return false;\n }\n \n-static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc)\n+static void arm_post_translate_insn(DisasContext *dc)\n {\n if (dc->condjmp && !dc->base.is_jmp) {\n gen_set_label(dc->condlabel);\n dc->condjmp = 0;\n }\n-\n- /* Translation stops when a conditional branch is encountered.\n- * Otherwise the subsequent code could get translated several times.\n- * Also stop translation when a page boundary is reached. This\n- * ensures prefetch aborts occur at the right place.\n- *\n- * We want to stop the TB if the next insn starts in a new page,\n- * or if it spans between this page and the next. This means that\n- * if we're looking at the last halfword in the page we need to\n- * see if it's a 16-bit Thumb insn (which will fit in this TB)\n- * or a 32-bit Thumb insn (which won't).\n- * This is to avoid generating a silly TB with a single 16-bit insn\n- * in it at the end of this page (which would execute correctly\n- * but isn't very efficient).\n- */\n- if (dc->base.is_jmp == DISAS_NEXT\n- && (dc->pc >= dc->next_page_start\n- || (dc->pc >= dc->next_page_start - 3\n- && insn_crosses_page(env, dc)))) {\n- dc->base.is_jmp = DISAS_TOO_MANY;\n- }\n-\n dc->base.pc_next = dc->pc;\n translator_loop_temp_check(&dc->base);\n }\n@@ -12061,7 +12046,10 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n dc->pc += 4;\n disas_arm_insn(dc, insn);\n \n- arm_post_translate_insn(env, dc);\n+ arm_post_translate_insn(dc);\n+\n+ /* ARM is a fixed-length ISA. We performed the cross-page check\n+ in init_disas_context by adjusting max_insns. */\n }\n \n static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n@@ -12085,7 +12073,27 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)\n }\n }\n \n- arm_post_translate_insn(env, dc);\n+ arm_post_translate_insn(dc);\n+\n+ /* Thumb is a variable-length ISA. Stop translation when the next insn\n+ * will touch a new page. This ensures that prefetch aborts occur at\n+ * the right place.\n+ *\n+ * We want to stop the TB if the next insn starts in a new page,\n+ * or if it spans between this page and the next. This means that\n+ * if we're looking at the last halfword in the page we need to\n+ * see if it's a 16-bit Thumb insn (which will fit in this TB)\n+ * or a 32-bit Thumb insn (which won't).\n+ * This is to avoid generating a silly TB with a single 16-bit insn\n+ * in it at the end of this page (which would execute correctly\n+ * but isn't very efficient).\n+ */\n+ if (dc->base.is_jmp == DISAS_NEXT\n+ && (dc->pc >= dc->next_page_start\n+ || (dc->pc >= dc->next_page_start - 3\n+ && insn_crosses_page(env, dc)))) {\n+ dc->base.is_jmp = DISAS_TOO_MANY;\n+ }\n }\n \n static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)\n", "prefixes": [ "PULL", "32/32" ] }