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[97.126.108.236]) by smtp.gmail.com with ESMTPSA id t65sm262863pfk.59.2017.09.06.09.06.55 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Wed, 06 Sep 2017 09:06:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 6 Sep 2017 09:06:12 -0700 Message-Id: <20170906160612.22769-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170906160612.22769-1-richard.henderson@linaro.org> References: <20170906160612.22769-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:400e:c05::22c Subject: [Qemu-devel] [PULL 32/32] target/arm: Perform per-insn cross-page check only for Thumb X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, Richard Henderson Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Richard Henderson ARM is a fixed-length ISA and we can compute the page crossing condition exactly once during init_disas_context. Reviewed-by: Emilio G. Cota Signed-off-by: Richard Henderson --- target/arm/translate.c | 58 ++++++++++++++++++++++++++++---------------------- 1 file changed, 33 insertions(+), 25 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 9e7bfbcf0c..6946e56a3a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -11888,6 +11888,13 @@ static int arm_tr_init_disas_context(DisasContextBase *dcbase, max_insns = 1; } + /* ARM is a fixed-length ISA. Bound the number of insns to execute + to those left on the page. */ + if (!dc->thumb) { + int bound = (dc->next_page_start - dc->base.pc_first) / 4; + max_insns = MIN(max_insns, bound); + } + cpu_F0s = tcg_temp_new_i32(); cpu_F1s = tcg_temp_new_i32(); cpu_F0d = tcg_temp_new_i64(); @@ -12015,34 +12022,12 @@ static bool arm_pre_translate_insn(DisasContext *dc) return false; } -static void arm_post_translate_insn(CPUARMState *env, DisasContext *dc) +static void arm_post_translate_insn(DisasContext *dc) { if (dc->condjmp && !dc->base.is_jmp) { gen_set_label(dc->condlabel); dc->condjmp = 0; } - - /* Translation stops when a conditional branch is encountered. - * Otherwise the subsequent code could get translated several times. - * Also stop translation when a page boundary is reached. This - * ensures prefetch aborts occur at the right place. - * - * We want to stop the TB if the next insn starts in a new page, - * or if it spans between this page and the next. This means that - * if we're looking at the last halfword in the page we need to - * see if it's a 16-bit Thumb insn (which will fit in this TB) - * or a 32-bit Thumb insn (which won't). - * This is to avoid generating a silly TB with a single 16-bit insn - * in it at the end of this page (which would execute correctly - * but isn't very efficient). - */ - if (dc->base.is_jmp == DISAS_NEXT - && (dc->pc >= dc->next_page_start - || (dc->pc >= dc->next_page_start - 3 - && insn_crosses_page(env, dc)))) { - dc->base.is_jmp = DISAS_TOO_MANY; - } - dc->base.pc_next = dc->pc; translator_loop_temp_check(&dc->base); } @@ -12061,7 +12046,10 @@ static void arm_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) dc->pc += 4; disas_arm_insn(dc, insn); - arm_post_translate_insn(env, dc); + arm_post_translate_insn(dc); + + /* ARM is a fixed-length ISA. We performed the cross-page check + in init_disas_context by adjusting max_insns. */ } static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) @@ -12085,7 +12073,27 @@ static void thumb_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) } } - arm_post_translate_insn(env, dc); + arm_post_translate_insn(dc); + + /* Thumb is a variable-length ISA. Stop translation when the next insn + * will touch a new page. This ensures that prefetch aborts occur at + * the right place. + * + * We want to stop the TB if the next insn starts in a new page, + * or if it spans between this page and the next. This means that + * if we're looking at the last halfword in the page we need to + * see if it's a 16-bit Thumb insn (which will fit in this TB) + * or a 32-bit Thumb insn (which won't). + * This is to avoid generating a silly TB with a single 16-bit insn + * in it at the end of this page (which would execute correctly + * but isn't very efficient). + */ + if (dc->base.is_jmp == DISAS_NEXT + && (dc->pc >= dc->next_page_start + || (dc->pc >= dc->next_page_start - 3 + && insn_crosses_page(env, dc)))) { + dc->base.is_jmp = DISAS_TOO_MANY; + } } static void arm_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu)