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GET /api/1.2/patches/809517/?format=api
{ "id": 809517, "url": "http://patchwork.ozlabs.org/api/1.2/patches/809517/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/20170904053832.12229-2-judge.packham@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170904053832.12229-2-judge.packham@gmail.com>", "list_archive_url": null, "date": "2017-09-04T05:38:32", "name": "[U-Boot,next,v2,2/2] ARM: mvebu: add additional information to board_add_ram_info()", "commit_ref": "631407c5c03b8503b7f297452154d6100d95510b", "pull_url": null, "state": "accepted", "archived": false, "hash": "4eceb09b5d2e7cb9f56062ca94ddcef8d32e636a", "submitter": { "id": 6125, "url": "http://patchwork.ozlabs.org/api/1.2/people/6125/?format=api", "name": "Chris Packham", "email": "judge.packham@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/20170904053832.12229-2-judge.packham@gmail.com/mbox/", "series": [ { "id": 1306, "url": "http://patchwork.ozlabs.org/api/1.2/series/1306/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/list/?series=1306", "date": "2017-09-04T05:38:31", "name": "[U-Boot,next,v2,1/2] ARM: mvebu: Add SoC IDs for Marvell's integrated CPUs", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/1306/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/809517/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/809517/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"BIJKZn2K\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xlzFV0DDCz9s78\n\tfor <incoming@patchwork.ozlabs.org>;\n\tMon, 4 Sep 2017 15:39:57 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid A62AAC21DF0; Mon, 4 Sep 2017 05:39:18 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id A6B42C21EDF;\n\tMon, 4 Sep 2017 05:39:16 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 95B72C21ED8; Mon, 4 Sep 2017 05:39:02 +0000 (UTC)", "from mail-pf0-f193.google.com (mail-pf0-f193.google.com\n\t[209.85.192.193])\n\tby lists.denx.de (Postfix) with ESMTPS id DCADCC21E41\n\tfor <u-boot@lists.denx.de>; Mon, 4 Sep 2017 05:38:58 +0000 (UTC)", "by mail-pf0-f193.google.com with SMTP id g13so3727907pfm.2\n\tfor <u-boot@lists.denx.de>; Sun, 03 Sep 2017 22:38:58 -0700 (PDT)", "from chrisp-dl.ws.atlnz.lc ([2001:df5:b000:22:3a2c:4aff:fe70:2b02])\n\tby smtp.gmail.com with ESMTPSA id\n\tj187sm8789776pgc.10.2017.09.03.22.38.53\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tSun, 03 Sep 2017 22:38:56 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.0 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE, RCVD_IN_MSPIKE_H2,\n\tT_DKIM_INVALID autolearn=unavailable\n\tautolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:cc:subject:date:message-id:in-reply-to:references;\n\tbh=9msrpjGYi1nzEpgNgK9PgV2+NzxrLu3JQvP2W4bYsUI=;\n\tb=BIJKZn2Ku3AM10UbkpJ0fTYwc+hudWhRqXlGCyNQF6Nul7scSG3N+ZAnKqdZ49jHIM\n\tJyg0sO+bypJ3XCRtXpb6FWwWXXpJqrPP7XhjyJ5kSRY1uwXXuK/YZY57kHOkfKhlN2Pw\n\tjI0ycE7exteMupKokfh5dISjkcwFVQZShmwkqOdhHAxXcqXFcdkMyX0WQfrfnPaBVrGP\n\tMCLCp34QRgm94WIY120GlXwqN3OaVMjuQfkybsnN/B6EpzTKqB09USFduOUig5JjSQbW\n\trnMiyDUt1SFIHHSrwhZRhV2XpPANCp8ia2Nz5Jx49cSfNlj0LM94p7nAT/AkKgzC5Bz2\n\tI2og==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=9msrpjGYi1nzEpgNgK9PgV2+NzxrLu3JQvP2W4bYsUI=;\n\tb=IZyLLcD2tKhzHzEwmQoNNGwrjQmnxnIrPyFAFjNYzoYSpU6/aD36d+t8g2ZGh9N6vz\n\toXHTeRb1WJfbVJRzO5HBLuNFKKVSoO+LRlURnA8oTXrfvvly0+KI/Fx6RYeHfBzrxWL3\n\tNHxlpLL+tDwpx/fYvl7sh0GEyOjlxFiP+oE/z2wdWGm4p4caGef3xBhtRlE78AGh7pgy\n\t2AwhNTcJ1XdqdbydLPdxTkeMxJl+f+X2FJ7usbMzXt2JkPWsD2/m7w6RNLsw4JTydi2c\n\tqvneF//0WCHMNV9P4U1dRGRIwq8iVWPw86zYWU1YAGfani0MBJEndE1zpU0EUTtEVa/E\n\tudBQ==", "X-Gm-Message-State": "AHPjjUgpiNqkaDLjNYtcmCl/1QO73KOhkN0jW6ionWt15aMkdOGbgb4B\n\tANczu8Ws5MVz9T6o/W8=", "X-Google-Smtp-Source": "ADKCNb6emZ5mr/EvfTbj7i8HvDu0VZ4B6GKWWrp2K1b5whN/Q2WRXWUDYhISPD1fd3p/TyYc2qISTQ==", "X-Received": "by 10.84.232.3 with SMTP id h3mr8868501plk.230.1504503537189;\n\tSun, 03 Sep 2017 22:38:57 -0700 (PDT)", "From": "Chris Packham <judge.packham@gmail.com>", "To": "u-boot@lists.denx.de", "Date": "Mon, 4 Sep 2017 17:38:32 +1200", "Message-Id": "<20170904053832.12229-2-judge.packham@gmail.com>", "X-Mailer": "git-send-email 2.14.1", "In-Reply-To": "<20170904053832.12229-1-judge.packham@gmail.com>", "References": "<20170904053832.12229-1-judge.packham@gmail.com>", "Cc": "Stefan Roese <sr@denx.de>, Chris Packham <judge.packham@gmail.com>,\n\tLuka Perkov <luka.perkov@sartura.hr>", "Subject": "[U-Boot] [next PATCH v2 2/2] ARM: mvebu: add additional information\n\tto board_add_ram_info()", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "From: Joshua Scott <joshua.scott@alliedtelesis.co.nz>\n\nDisplay more information about the current RAM configuration. With these\nchanges the output on a 88F6820 board is\n\n SoC: MV88F6820-A0 at 1600 MHz\n DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled)\n\nSigned-off-by: Joshua Scott <joshua.scott@alliedtelesis.co.nz>\nSigned-off-by: Chris Packham <judge.packham@gmail.com>\n---\nOne of the hardware designers at $dayjob expressed a desire to keep\ntrack of various tweaks to the DDR setup during hardware debugging\nsessions. This is the result.\n\nI've based this on what is available for the fsl platforms. It might be\nnice to add a few more things but I'm concious of keeping the\ninformation relevant and succinct.\n\nChanges in v2:\n- A375 and A38x have 16/32b DDR bus\n\n arch/arm/mach-mvebu/dram.c | 45 +++++++++++++++++++++++++++++++++++++++++++++\n 1 file changed, 45 insertions(+)", "diff": "diff --git a/arch/arm/mach-mvebu/dram.c b/arch/arm/mach-mvebu/dram.c\nindex e3f304c36683..55e9ad726a88 100644\n--- a/arch/arm/mach-mvebu/dram.c\n+++ b/arch/arm/mach-mvebu/dram.c\n@@ -216,6 +216,35 @@ static int ecc_enabled(void)\n \n \treturn 0;\n }\n+\n+/* Return the width of the DRAM bus, or 0 for unknown. */\n+static int bus_width(void)\n+{\n+\tint full_width = 0;\n+\n+\tif (reg_read(REG_SDRAM_CONFIG_ADDR) & (1 << REG_SDRAM_CONFIG_WIDTH_OFFS))\n+\t\tfull_width = 1;\n+\n+\tswitch (mvebu_soc_family()) {\n+\tcase MVEBU_SOC_AXP:\n+\t return full_width ? 64 : 32;\n+\t break;\n+\tcase MVEBU_SOC_A375:\n+\tcase MVEBU_SOC_A38X:\n+\tcase MVEBU_SOC_MSYS:\n+\t return full_width ? 32 : 16;\n+\tdefault:\n+\t return 0;\n+\t}\n+}\n+\n+static int cycle_mode(void)\n+{\n+\tint val = reg_read(REG_DUNIT_CTRL_LOW_ADDR);\n+\n+\treturn (val >> REG_DUNIT_CTRL_LOW_2T_OFFS) & REG_DUNIT_CTRL_LOW_2T_MASK;\n+}\n+\n #else\n static void dram_ecc_scrubbing(void)\n {\n@@ -295,10 +324,26 @@ int dram_init_banksize(void)\n void board_add_ram_info(int use_default)\n {\n \tstruct sar_freq_modes sar_freq;\n+\tint mode;\n+\tint width;\n \n \tget_sar_freq(&sar_freq);\n \tprintf(\" (%d MHz, \", sar_freq.d_clk);\n \n+\twidth = bus_width();\n+\tif (width)\n+\t\tprintf(\"%d-bit, \", width);\n+\n+\tmode = cycle_mode();\n+\t/* Mode 0 = Single cycle\n+\t * Mode 1 = Two cycles (2T)\n+\t * Mode 2 = Three cycles (3T)\n+\t */\n+\tif (mode == 1)\n+\t\tprintf(\"2T, \");\n+\tif (mode == 2)\n+\t\tprintf(\"3T, \");\n+\n \tif (ecc_enabled())\n \t\tprintf(\"ECC\");\n \telse\n", "prefixes": [ "U-Boot", "next", "v2", "2/2" ] }