[{"id":1762450,"web_url":"http://patchwork.ozlabs.org/comment/1762450/","msgid":"","list_archive_url":null,"date":"2017-09-04T06:43:56","subject":"Re: [U-Boot] [next PATCH v2 2/2] ARM: mvebu: add additional\n\tinformation to board_add_ram_info()","submitter":{"id":13,"url":"http://patchwork.ozlabs.org/api/people/13/","name":"Stefan Roese","email":"sr@denx.de"},"content":"On 04.09.2017 07:38, Chris Packham wrote:\n> From: Joshua Scott \n> \n> Display more information about the current RAM configuration. With these\n> changes the output on a 88F6820 board is\n> \n> SoC: MV88F6820-A0 at 1600 MHz\n> DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled)\n> \n> Signed-off-by: Joshua Scott \n> Signed-off-by: Chris Packham \n> ---\n> One of the hardware designers at $dayjob expressed a desire to keep\n> track of various tweaks to the DDR setup during hardware debugging\n> sessions. This is the result.\n> \n> I've based this on what is available for the fsl platforms. It might be\n> nice to add a few more things but I'm concious of keeping the\n> information relevant and succinct.\n> \n> Changes in v2:\n> - A375 and A38x have 16/32b DDR bus\n> \n> arch/arm/mach-mvebu/dram.c | 45 +++++++++++++++++++++++++++++++++++++++++++++\n> 1 file changed, 45 insertions(+)\n\nReviewed-by: Stefan Roese \n\nThanks,\nStefan","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xm0gl2j1fz9s72\n\tfor ;\n\tMon, 4 Sep 2017 16:44:19 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid EA42BC21DD0; Mon, 4 Sep 2017 06:44:08 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id 59ED0C21DAD;\n\tMon, 4 Sep 2017 06:44:06 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid ABAC2C21DD0; Mon, 4 Sep 2017 06:44:04 +0000 (UTC)","from mx1.mailbox.org (mx1.mailbox.org [80.241.60.212])\n\tby lists.denx.de (Postfix) with ESMTPS id C74F3C21DAD\n\tfor ; Mon, 4 Sep 2017 06:44:03 +0000 (UTC)","from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mx1.mailbox.org (Postfix) with ESMTPS id 7C513442C2;\n\tMon, 4 Sep 2017 08:44:01 +0200 (CEST)","from smtp1.mailbox.org ([80.241.60.240])\n\tby spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de\n\t[80.241.56.116]) (amavisd-new, port 10030)\n\twith ESMTP id 04gfO8XoLLg7; Mon, 4 Sep 2017 08:43:57 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-Virus-Scanned":"amavisd-new at heinlein-support.de","To":"Chris Packham , u-boot@lists.denx.de","References":"<20170904053832.12229-1-judge.packham@gmail.com>\n\t<20170904053832.12229-2-judge.packham@gmail.com>","From":"Stefan Roese ","Message-ID":"","Date":"Mon, 4 Sep 2017 08:43:56 +0200","MIME-Version":"1.0","In-Reply-To":"<20170904053832.12229-2-judge.packham@gmail.com>","Content-Language":"en-US","Cc":"Luka Perkov ","Subject":"Re: [U-Boot] [next PATCH v2 2/2] ARM: mvebu: add additional\n\tinformation to board_add_ram_info()","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}},{"id":1775278,"web_url":"http://patchwork.ozlabs.org/comment/1775278/","msgid":"<3c21ca12-64f1-e830-cd8c-8a0f669f9304@denx.de>","list_archive_url":null,"date":"2017-09-26T08:51:36","subject":"Re: [U-Boot] [next PATCH v2 2/2] ARM: mvebu: add additional\n\tinformation to board_add_ram_info()","submitter":{"id":13,"url":"http://patchwork.ozlabs.org/api/people/13/","name":"Stefan Roese","email":"sr@denx.de"},"content":"On 04.09.2017 07:38, Chris Packham wrote:\n> From: Joshua Scott \n> \n> Display more information about the current RAM configuration. With these\n> changes the output on a 88F6820 board is\n> \n> SoC: MV88F6820-A0 at 1600 MHz\n> DRAM: 2 GiB (800 MHz, 32-bit, ECC not enabled)\n> \n> Signed-off-by: Joshua Scott \n> Signed-off-by: Chris Packham \n> ---\n> One of the hardware designers at $dayjob expressed a desire to keep\n> track of various tweaks to the DDR setup during hardware debugging\n> sessions. This is the result.\n> \n> I've based this on what is available for the fsl platforms. It might be\n> nice to add a few more things but I'm concious of keeping the\n> information relevant and succinct.\n> \n> Changes in v2:\n> - A375 and A38x have 16/32b DDR bus\n\nApplied to u-boot-marvell/master.\n\nThanks,\nStefan","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":"ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=)","Received":["from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3y1ZTm0GzKz9t3B\n\tfor ;\n\tTue, 26 Sep 2017 18:52:44 +1000 (AEST)","by lists.denx.de (Postfix, from userid 105)\n\tid C6101C21EE4; Tue, 26 Sep 2017 08:52:05 +0000 (UTC)","from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id D4CDCC21EBC;\n\tTue, 26 Sep 2017 08:51:51 +0000 (UTC)","by lists.denx.de (Postfix, from userid 105)\n\tid 81695C21D7B; Tue, 26 Sep 2017 08:51:42 +0000 (UTC)","from mx2.mailbox.org (mx2.mailbox.org [80.241.60.215])\n\tby lists.denx.de (Postfix) with ESMTPS id 4EFBCC21EEF\n\tfor ; Tue, 26 Sep 2017 08:51:40 +0000 (UTC)","from smtp1.mailbox.org (smtp1.mailbox.org [80.241.60.240])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby mx2.mailbox.org (Postfix) with ESMTPS id C4E1D4C54C;\n\tTue, 26 Sep 2017 10:51:39 +0200 (CEST)","from smtp1.mailbox.org ([80.241.60.240])\n\tby spamfilter02.heinlein-hosting.de (spamfilter02.heinlein-hosting.de\n\t[80.241.56.116]) (amavisd-new, port 10030)\n\twith ESMTP id t-uA3xkfQsBj; Tue, 26 Sep 2017 10:51:37 +0200 (CEST)"],"X-Spam-Checker-Version":"SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de","X-Spam-Level":"","X-Spam-Status":"No, score=-0.7 required=5.0 tests=RCVD_IN_DNSWL_LOW\n\tautolearn=unavailable autolearn_force=no version=3.4.0","X-Virus-Scanned":"amavisd-new at heinlein-support.de","To":"Chris Packham , u-boot@lists.denx.de","References":"<20170904053832.12229-1-judge.packham@gmail.com>\n\t<20170904053832.12229-2-judge.packham@gmail.com>","From":"Stefan Roese ","Message-ID":"<3c21ca12-64f1-e830-cd8c-8a0f669f9304@denx.de>","Date":"Tue, 26 Sep 2017 10:51:36 +0200","MIME-Version":"1.0","In-Reply-To":"<20170904053832.12229-2-judge.packham@gmail.com>","Content-Language":"en-US","Cc":"Luka Perkov ,\n\tPrafulla Wadaskar ","Subject":"Re: [U-Boot] [next PATCH v2 2/2] ARM: mvebu: add additional\n\tinformation to board_add_ram_info()","X-BeenThere":"u-boot@lists.denx.de","X-Mailman-Version":"2.1.18","Precedence":"list","List-Id":"U-Boot discussion ","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Content-Transfer-Encoding":"base64","Content-Type":"text/plain; charset=\"utf-8\"; Format=\"flowed\"","Errors-To":"u-boot-bounces@lists.denx.de","Sender":"\"U-Boot\" "}}]