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GET /api/1.2/patches/805045/?format=api
{ "id": 805045, "url": "http://patchwork.ozlabs.org/api/1.2/patches/805045/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com/", "project": { "id": 2, "url": "http://patchwork.ozlabs.org/api/1.2/projects/2/?format=api", "name": "Linux PPC development", "link_name": "linuxppc-dev", "list_id": "linuxppc-dev.lists.ozlabs.org", "list_email": "linuxppc-dev@lists.ozlabs.org", "web_url": "https://github.com/linuxppc/wiki/wiki", "scm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git", "webscm_url": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/", "list_archive_url_format": "https://lore.kernel.org/linuxppc-dev/{}/", "commit_url_format": "https://git.kernel.org/pub/scm/linux/kernel/git/powerpc/linux.git/commit/?id={}" }, "msgid": "<1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com>", "list_archive_url": "https://lore.kernel.org/linuxppc-dev/1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com/", "date": "2017-08-23T14:58:06", "name": "cxl: Add support for POWER9 DD2", "commit_ref": null, "pull_url": null, "state": "changes-requested", "archived": false, "hash": "6d1624f22c68e7d0a816424b659fe564df98f25e", "submitter": { "id": 67351, "url": "http://patchwork.ozlabs.org/api/1.2/people/67351/?format=api", "name": "Christophe Lombard", "email": "clombard@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linuxppc-dev/patch/1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/805045/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/805045/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@ozlabs.org", "linuxppc-dev@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xcrQ44tlgz9s8V\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 24 Aug 2017 01:07:40 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xcrQ43zVbzDqm5\n\tfor <patchwork-incoming@ozlabs.org>;\n\tThu, 24 Aug 2017 01:07:40 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xcrCG0zfFzDqZw\n\tfor <linuxppc-dev@lists.ozlabs.org>;\n\tThu, 24 Aug 2017 00:58:17 +1000 (AEST)", "from pps.filterd (m0098393.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7NEunmh064129\n\tfor <linuxppc-dev@lists.ozlabs.org>; Wed, 23 Aug 2017 10:58:16 -0400", "from e06smtp13.uk.ibm.com (e06smtp13.uk.ibm.com [195.75.94.109])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2chb4mk213-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <linuxppc-dev@lists.ozlabs.org>; Wed, 23 Aug 2017 10:58:15 -0400", "from localhost\n\tby e06smtp13.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <linuxppc-dev@lists.ozlabs.org> from\n\t<clombard@linux.vnet.ibm.com>; Wed, 23 Aug 2017 15:58:12 +0100", "from b06cxnps4074.portsmouth.uk.ibm.com (9.149.109.196)\n\tby e06smtp13.uk.ibm.com (192.168.101.143) with IBM ESMTP SMTP\n\tGateway: Authorized Use Only! Violators will be prosecuted; \n\tWed, 23 Aug 2017 15:58:09 +0100", "from d06av26.portsmouth.uk.ibm.com (d06av26.portsmouth.uk.ibm.com\n\t[9.149.105.62])\n\tby b06cxnps4074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v7NEw8L722609960; Wed, 23 Aug 2017 14:58:08 GMT", "from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 82522AE04D;\n\tWed, 23 Aug 2017 15:53:46 +0100 (BST)", "from d06av26.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 85042AE045;\n\tWed, 23 Aug 2017 15:53:45 +0100 (BST)", "from lombard-w520.ibm.com (unknown [9.164.175.89])\n\tby d06av26.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n\tWed, 23 Aug 2017 15:53:45 +0100 (BST)" ], "From": "Christophe Lombard <clombard@linux.vnet.ibm.com>", "To": "linuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com,\n\tvaibhav@linux.vnet.ibm.com, andrew.donnellan@au1.ibm.com", "Subject": "[PATCH] cxl: Add support for POWER9 DD2", "Date": "Wed, 23 Aug 2017 16:58:06 +0200", "X-Mailer": "git-send-email 2.7.4", "X-TM-AS-GCONF": "00", "x-cbid": "17082314-0012-0000-0000-00000571CA93", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082314-0013-0000-0000-000018E9AA64", "Message-Id": "<1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-23_05:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708230224", "X-BeenThere": "linuxppc-dev@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Linux on PowerPC Developers Mail List\n\t<linuxppc-dev.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/linuxppc-dev/>", "List-Post": "<mailto:linuxppc-dev@lists.ozlabs.org>", "List-Help": "<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/linuxppc-dev>,\n\t<mailto:linuxppc-dev-request@lists.ozlabs.org?subject=subscribe>", "Errors-To": "linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org", "Sender": "\"Linuxppc-dev\"\n\t<linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org>" }, "content": "The PSL initialization sequence has been updated to DD2.\nThis patch adapts to the changes, retaining compatibility with DD1.\n\nTests performed on some of the new hardware.\n\nSigned-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com>\n---\n drivers/misc/cxl/cxl.h | 2 ++\n drivers/misc/cxl/pci.c | 57 +++++++++++++++++++++++++++++++-------------------\n 2 files changed, 38 insertions(+), 21 deletions(-)", "diff": "diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h\nindex b1afecc..0167df8 100644\n--- a/drivers/misc/cxl/cxl.h\n+++ b/drivers/misc/cxl/cxl.h\n@@ -100,6 +100,8 @@ static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};\n static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};\n /* PSL registers - CAIA 2 */\n static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};\n+static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110};\n+static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};\n static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};\n static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};\n static const cxl_p1_reg_t CXL_PSL9_FIR2 = {0x0308};\ndiff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c\nindex d18b3d9..a981c65 100644\n--- a/drivers/misc/cxl/pci.c\n+++ b/drivers/misc/cxl/pci.c\n@@ -475,37 +475,52 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,\n \tpsl_fircntl |= 0x1ULL; /* ce_thresh */\n \tcxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);\n \n-\t/* vccredits=0x1 pcklat=0x4 */\n-\tcxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);\n-\n-\t/*\n-\t * For debugging with trace arrays.\n-\t * Configure RX trace 0 segmented mode.\n-\t * Configure CT trace 0 segmented mode.\n-\t * Configure LA0 trace 0 segmented mode.\n-\t * Configure LA1 trace 0 segmented mode.\n+\t/* Setup the PSL to transmit packets on the PCIe before the\n+\t * CAPP is enabled\n \t */\n-\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);\n-\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);\n-\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);\n-\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);\n+\tcxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000002A10ULL);\n+\n+\t/* For debugging with trace arrays */\n+\t/* Configure RX trace 0 segmented mode */\n+\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000000ULL);\n+\t/* Configure RX trace 1 segmented mode */\n+\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xAA00000000000001ULL);\n+\t/* Configure CT trace 0 segmented mode */\n+\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xA2B8000000000003ULL);\n+\t/* Configure LA0 trace 0 segmented mode */\n+\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x83FFC00000000005ULL);\n+\t/* Configure JM0 trace 0 segmented mode */\n+\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000007ULL);\n+\t/* Configure DMA trace 0 segmented mode */\n+\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000008ULL);\n+\t/* Configure DMA trace 1 segmented mode */\n+\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000009ULL);\n \n \t/*\n \t * A response to an ASB_Notify request is returned by the\n \t * system as an MMIO write to the address defined in\n \t * the PSL_TNR_ADDR register\n \t */\n-\t/* PSL_TNR_ADDR */\n+\t/* keep the Reset Value: 0x00020000E0000000 */\n+\n+\t/* Enable XSL rty limit */\n+\tcxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);\n \n-\t/* NORST */\n-\tcxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);\n+\t/* Change XSL_INV dummy readtheshold */\n+\tcxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);\n \n-\t/* allocate the apc machines */\n-\tcxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);\n+\tif (phb_index == 3) {\n+\t\t/* disable machines 31-47 and 20-27 for DMA */\n+\t\tcxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);\n+\t}\n+\n+\t/* Snoop machines */\n+\tcxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);\n \n-\t/* Disable vc dd1 fix */\n-\tif (cxl_is_power9_dd1())\n-\t\tcxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);\n+\tif (cxl_is_power9_dd1()) {\n+\t\t/* Disabling deadlock counter CAR */\n+\t\tcxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);\n+\t}\n \n \treturn 0;\n }\n", "prefixes": [] }