[{"id":1755875,"web_url":"http://patchwork.ozlabs.org/comment/1755875/","msgid":"","date":"2017-08-24T05:24:44","subject":"Re: [PATCH] cxl: Add support for POWER9 DD2","submitter":{"id":66955,"url":"http://patchwork.ozlabs.org/api/people/66955/","name":"Andrew Donnellan","email":"andrew.donnellan@au1.ibm.com"},"content":"On 24/08/17 00:58, Christophe Lombard wrote:\n> The PSL initialization sequence has been updated to DD2.\n> This patch adapts to the changes, retaining compatibility with DD1.\n> \n> Tests performed on some of the new hardware.\n\nIf we're retaining compatibility with DD1 I assume it's been tested on \nsome of the old hardware too?\n\nIt seems this includes some changes to DD1 fix-ups as well.\n\n> \n> Signed-off-by: Christophe Lombard > ---\n> drivers/misc/cxl/cxl.h | 2 ++\n> drivers/misc/cxl/pci.c | 57 +++++++++++++++++++++++++++++++-------------------\n> 2 files changed, 38 insertions(+), 21 deletions(-)\n> \n> diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h\n> index b1afecc..0167df8 100644\n> --- a/drivers/misc/cxl/cxl.h\n> +++ b/drivers/misc/cxl/cxl.h\n> @@ -100,6 +100,8 @@ static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};\n> static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};\n> /* PSL registers - CAIA 2 */\n> static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};\n> +static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110};\n> +static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};\n> static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};\n> static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};\n> static const cxl_p1_reg_t CXL_PSL9_FIR2 = {0x0308};\n> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c\n> index d18b3d9..a981c65 100644\n> --- a/drivers/misc/cxl/pci.c\n> +++ b/drivers/misc/cxl/pci.c\n> @@ -475,37 +475,52 @@ static int init_implementation_adapter_regs_psl9(struct cxl *adapter,\n> \tpsl_fircntl |= 0x1ULL; /* ce_thresh */\n> \tcxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);\n> \n> -\t/* vccredits=0x1 pcklat=0x4 */\n> -\tcxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);\n> -\n> -\t/*\n> -\t * For debugging with trace arrays.\n> -\t * Configure RX trace 0 segmented mode.\n> -\t * Configure CT trace 0 segmented mode.\n> -\t * Configure LA0 trace 0 segmented mode.\n> -\t * Configure LA1 trace 0 segmented mode.\n> +\t/* Setup the PSL to transmit packets on the PCIe before the\n> +\t * CAPP is enabled\n> \t */\n> -\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);\n> -\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);\n> -\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);\n> -\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);\n> +\tcxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000002A10ULL);\n> +\n> +\t/* For debugging with trace arrays */\n> +\t/* Configure RX trace 0 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000000ULL);\n> +\t/* Configure RX trace 1 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xAA00000000000001ULL);\n> +\t/* Configure CT trace 0 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xA2B8000000000003ULL);\n> +\t/* Configure LA0 trace 0 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x83FFC00000000005ULL);\n> +\t/* Configure JM0 trace 0 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000007ULL);\n> +\t/* Configure DMA trace 0 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000008ULL);\n> +\t/* Configure DMA trace 1 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000009ULL);\n> \n> \t/*\n> \t * A response to an ASB_Notify request is returned by the\n> \t * system as an MMIO write to the address defined in\n> \t * the PSL_TNR_ADDR register\n> \t */\n> -\t/* PSL_TNR_ADDR */\n> +\t/* keep the Reset Value: 0x00020000E0000000 */\n\nI was confused by this comment for a while - maybe keep PSL_TNR_ADDR at \nthe beginning of the comment, it's not completely clear from the \nprevious block alone.\n\n> +\n> +\t/* Enable XSL rty limit */\n> +\tcxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);\n> \n> -\t/* NORST */\n> -\tcxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);\n> +\t/* Change XSL_INV dummy readtheshold */\n\nread threshold?\n\n> +\tcxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);\n> \n> -\t/* allocate the apc machines */\n> -\tcxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);\n> +\tif (phb_index == 3) {\n> +\t\t/* disable machines 31-47 and 20-27 for DMA */\n> +\t\tcxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000FF3FFFF0000ULL);\n> +\t}\n> +\n> +\t/* Snoop machines */\n> +\tcxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);\n> \n> -\t/* Disable vc dd1 fix */\n> -\tif (cxl_is_power9_dd1())\n> -\t\tcxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);\n> +\tif (cxl_is_power9_dd1()) {\n> +\t\t/* Disabling deadlock counter CAR */\n> +\t\tcxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);\n> +\t}\n> \n> \treturn 0;\n> }\n>","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xdCST1XCQz9sRW\n\tfor ;\n\tThu, 24 Aug 2017 15:26:01 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xdCST0QShzDrLV\n\tfor ;\n\tThu, 24 Aug 2017 15:26:01 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xdCR941dVzDqY3\n\tfor ;\n\tThu, 24 Aug 2017 15:24:53 +1000 (AEST)","from pps.filterd (m0098417.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7O5O9jN090710\n\tfor ; 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Violators will be prosecuted; \n\tThu, 24 Aug 2017 15:24:45 +1000","from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139])\n\tby d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tv7O5Ojkb33358020\n\tfor ; Thu, 24 Aug 2017 15:24:45 +1000","from d23av04.au.ibm.com (localhost [127.0.0.1])\n\tby d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tv7O5OjYM019080\n\tfor ; Thu, 24 Aug 2017 15:24:45 +1000","from ozlabs.au.ibm.com (ozlabs.au.ibm.com [9.192.253.14])\n\tby d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tv7O5Ojl8019077; Thu, 24 Aug 2017 15:24:45 +1000","from [10.61.2.125] (haven.au.ibm.com [9.192.254.114])\n\t(using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits))\n\t(No client certificate requested)\n\tby ozlabs.au.ibm.com (Postfix) with ESMTPSA id 4EE4CA01C4;\n\tThu, 24 Aug 2017 15:24:44 +1000 (AEST)"],"Subject":"Re: [PATCH] cxl: Add support for POWER9 DD2","To":"Christophe Lombard ,\n\tlinuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com,\n\tvaibhav@linux.vnet.ibm.com","References":"<1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com>","From":"Andrew Donnellan ","Date":"Thu, 24 Aug 2017 15:24:44 +1000","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Language":"en-AU","Content-Transfer-Encoding":"7bit","X-TM-AS-MML":"disable","x-cbid":"17082405-1617-0000-0000-000001FC87DC","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17082405-1618-0000-0000-000048489CBB","Message-Id":"","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-24_01:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708240087","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1755935,"web_url":"http://patchwork.ozlabs.org/comment/1755935/","msgid":"<87378hv3vb.fsf@vajain21.in.ibm.com>","date":"2017-08-24T07:09:28","subject":"Re: [PATCH] cxl: Add support for POWER9 DD2","submitter":{"id":66174,"url":"http://patchwork.ozlabs.org/api/people/66174/","name":"Vaibhav Jain","email":"vaibhav@linux.vnet.ibm.com"},"content":"Hi Christophe,\n\nChristophe Lombard writes:\n> +\t/* For debugging with trace arrays */\n> +\t/* Configure RX trace 0 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000000ULL);\n> +\t/* Configure RX trace 1 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xAA00000000000001ULL);\n> +\t/* Configure CT trace 0 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xA2B8000000000003ULL);\n> +\t/* Configure LA0 trace 0 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x83FFC00000000005ULL);\n> +\t/* Configure JM0 trace 0 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000007ULL);\n> +\t/* Configure DMA trace 0 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000008ULL);\n> +\t/* Configure DMA trace 1 segmented mode */\n> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000009ULL);\nPlease wrap this block that configures the trace arrays in #ifdef\nDEBUG. Or it will be better if we remove it from here as the register is\nalready accessible via debugfs.\n\n---\nVaibhav Jain \nLinux Technology Center, IBM India Pvt. Ltd.","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xdFnb5XZ0z9t2Z\n\tfor ;\n\tThu, 24 Aug 2017 17:10:59 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xdFnb4dvMzDqYV\n\tfor ;\n\tThu, 24 Aug 2017 17:10:59 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com\n\t[148.163.156.1])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xdFm44c7QzDqJ3\n\tfor ;\n\tThu, 24 Aug 2017 17:09:40 +1000 (AEST)","from pps.filterd (m0098396.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7O78jek123227\n\tfor ; Thu, 24 Aug 2017 03:09:38 -0400","from e23smtp05.au.ibm.com (e23smtp05.au.ibm.com [202.81.31.147])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2chrudwnqt-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Thu, 24 Aug 2017 03:09:38 -0400","from localhost\n\tby e23smtp05.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tThu, 24 Aug 2017 17:09:33 +1000","from d23av04.au.ibm.com (d23av04.au.ibm.com [9.190.235.139])\n\tby d23relay08.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tv7O79XrT31916272\n\tfor ; Thu, 24 Aug 2017 17:09:33 +1000","from d23av04.au.ibm.com (localhost [127.0.0.1])\n\tby d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tv7O79Xp4015922\n\tfor ; Thu, 24 Aug 2017 17:09:33 +1000","from vajain21.in.ibm.com ([9.109.220.181])\n\tby d23av04.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with SMTP id\n\tv7O79T4r015860; Thu, 24 Aug 2017 17:09:30 +1000","by vajain21.in.ibm.com (sSMTP sendmail emulation);\n\tThu, 24 Aug 2017 12:39:28 +0530"],"From":"Vaibhav Jain ","To":"Christophe Lombard ,\n\tlinuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com,\n\tandrew.donnellan@au1.ibm.com","Subject":"Re: [PATCH] cxl: Add support for POWER9 DD2","In-Reply-To":"<1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com>","References":"<1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com>","Date":"Thu, 24 Aug 2017 12:39:28 +0530","MIME-Version":"1.0","Content-Type":"text/plain","X-TM-AS-MML":"disable","x-cbid":"17082407-0016-0000-0000-000002615B58","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17082407-0017-0000-0000-000006E41532","Message-Id":"<87378hv3vb.fsf@vajain21.in.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-24_03:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708240116","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1755939,"web_url":"http://patchwork.ozlabs.org/comment/1755939/","msgid":"","date":"2017-08-24T07:20:44","subject":"Re: [PATCH] cxl: Add support for POWER9 DD2","submitter":{"id":67351,"url":"http://patchwork.ozlabs.org/api/people/67351/","name":"Christophe Lombard","email":"clombard@linux.vnet.ibm.com"},"content":"Le 24/08/2017 à 09:09, Vaibhav Jain a écrit :\n> Hi Christophe,\n>\n> Christophe Lombard writes:\n>> +\t/* For debugging with trace arrays */\n>> +\t/* Configure RX trace 0 segmented mode */\n>> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000000ULL);\n>> +\t/* Configure RX trace 1 segmented mode */\n>> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xAA00000000000001ULL);\n>> +\t/* Configure CT trace 0 segmented mode */\n>> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xA2B8000000000003ULL);\n>> +\t/* Configure LA0 trace 0 segmented mode */\n>> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x83FFC00000000005ULL);\n>> +\t/* Configure JM0 trace 0 segmented mode */\n>> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000007ULL);\n>> +\t/* Configure DMA trace 0 segmented mode */\n>> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000008ULL);\n>> +\t/* Configure DMA trace 1 segmented mode */\n>> +\tcxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000009ULL);\n> Please wrap this block that configures the trace arrays in #ifdef\n> DEBUG. Or it will be better if we remove it from here as the register is\n> already accessible via debugfs.\n>\n> ---\n> Vaibhav Jain \n> Linux Technology Center, IBM India Pvt. Ltd.\n\nokay, I will remove this block\n\nThanks","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xdG2G669lz9sRm\n\tfor ;\n\tThu, 24 Aug 2017 17:21:58 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xdG2G5768zDrKJ\n\tfor ;\n\tThu, 24 Aug 2017 17:21:58 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xdG120q64zDqMX\n\tfor ;\n\tThu, 24 Aug 2017 17:20:53 +1000 (AEST)","from pps.filterd (m0098414.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7O7JO6F132115\n\tfor ; Thu, 24 Aug 2017 03:20:51 -0400","from e06smtp15.uk.ibm.com (e06smtp15.uk.ibm.com [195.75.94.111])\n\tby mx0b-001b2d01.pphosted.com with ESMTP id 2chq9b6r7k-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor ; Thu, 24 Aug 2017 03:20:51 -0400","from localhost\n\tby e06smtp15.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! 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Violators will be prosecuted; \n\tThu, 24 Aug 2017 08:20:46 +0100","from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com\n\t[9.149.105.61])\n\tby b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v7O7KjR818546758; Thu, 24 Aug 2017 07:20:45 GMT","from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 3BC8311C052;\n\tThu, 24 Aug 2017 08:17:25 +0100 (BST)","from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id B9F2711C050;\n\tThu, 24 Aug 2017 08:17:24 +0100 (BST)","from [9.167.235.238] (unknown [9.167.235.238])\n\tby d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n\tThu, 24 Aug 2017 08:17:24 +0100 (BST)"],"Subject":"Re: [PATCH] cxl: Add support for POWER9 DD2","To":"Vaibhav Jain , linuxppc-dev@lists.ozlabs.org,\n\tfbarrat@linux.vnet.ibm.com, andrew.donnellan@au1.ibm.com","References":"<1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com>\n\t<87378hv3vb.fsf@vajain21.in.ibm.com>","From":"christophe lombard ","Date":"Thu, 24 Aug 2017 09:20:44 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"<87378hv3vb.fsf@vajain21.in.ibm.com>","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Transfer-Encoding":"8bit","Content-Language":"fr-xx-classique","X-TM-AS-GCONF":"00","x-cbid":"17082407-0020-0000-0000-000003B0E6A4","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17082407-0021-0000-0000-000042406A72","Message-Id":"","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-24_03:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708240119","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}},{"id":1755941,"web_url":"http://patchwork.ozlabs.org/comment/1755941/","msgid":"<662aff24-cb60-432c-a6b8-cd04e7498711@linux.vnet.ibm.com>","date":"2017-08-24T07:23:05","subject":"Re: [PATCH] cxl: Add support for POWER9 DD2","submitter":{"id":67351,"url":"http://patchwork.ozlabs.org/api/people/67351/","name":"Christophe Lombard","email":"clombard@linux.vnet.ibm.com"},"content":"Le 24/08/2017 à 07:24, Andrew Donnellan a écrit :\n> On 24/08/17 00:58, Christophe Lombard wrote:\n>> The PSL initialization sequence has been updated to DD2.\n>> This patch adapts to the changes, retaining compatibility with DD1.\n>>\n>> Tests performed on some of the new hardware.\n>\n> If we're retaining compatibility with DD1 I assume it's been tested on \n> some of the old hardware too?\n\nright, it's been tested on boston machine with dd1\n\n>\n> It seems this includes some changes to DD1 fix-ups as well.\n\ncorrect\n\n>\n>>\n>> Signed-off-by: Christophe Lombard > ---\n>> drivers/misc/cxl/cxl.h | 2 ++\n>> drivers/misc/cxl/pci.c | 57 \n>> +++++++++++++++++++++++++++++++-------------------\n>> 2 files changed, 38 insertions(+), 21 deletions(-)\n>>\n>> diff --git a/drivers/misc/cxl/cxl.h b/drivers/misc/cxl/cxl.h\n>> index b1afecc..0167df8 100644\n>> --- a/drivers/misc/cxl/cxl.h\n>> +++ b/drivers/misc/cxl/cxl.h\n>> @@ -100,6 +100,8 @@ static const cxl_p1_reg_t CXL_XSL_FEC = {0x0158};\n>> static const cxl_p1_reg_t CXL_XSL_DSNCTL = {0x0168};\n>> /* PSL registers - CAIA 2 */\n>> static const cxl_p1_reg_t CXL_PSL9_CONTROL = {0x0020};\n>> +static const cxl_p1_reg_t CXL_XSL9_INV = {0x0110};\n>> +static const cxl_p1_reg_t CXL_XSL9_DEF = {0x0140};\n>> static const cxl_p1_reg_t CXL_XSL9_DSNCTL = {0x0168};\n>> static const cxl_p1_reg_t CXL_PSL9_FIR1 = {0x0300};\n>> static const cxl_p1_reg_t CXL_PSL9_FIR2 = {0x0308};\n>> diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pci.c\n>> index d18b3d9..a981c65 100644\n>> --- a/drivers/misc/cxl/pci.c\n>> +++ b/drivers/misc/cxl/pci.c\n>> @@ -475,37 +475,52 @@ static int \n>> init_implementation_adapter_regs_psl9(struct cxl *adapter,\n>> psl_fircntl |= 0x1ULL; /* ce_thresh */\n>> cxl_p1_write(adapter, CXL_PSL9_FIR_CNTL, psl_fircntl);\n>> - /* vccredits=0x1 pcklat=0x4 */\n>> - cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0000000000001810ULL);\n>> -\n>> - /*\n>> - * For debugging with trace arrays.\n>> - * Configure RX trace 0 segmented mode.\n>> - * Configure CT trace 0 segmented mode.\n>> - * Configure LA0 trace 0 segmented mode.\n>> - * Configure LA1 trace 0 segmented mode.\n>> + /* Setup the PSL to transmit packets on the PCIe before the\n>> + * CAPP is enabled\n>> */\n>> - cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000000ULL);\n>> - cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000003ULL);\n>> - cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000005ULL);\n>> - cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8040800080000006ULL);\n>> + cxl_p1_write(adapter, CXL_PSL9_DSNDCTL, 0x0001001000002A10ULL);\n>> +\n>> + /* For debugging with trace arrays */\n>> + /* Configure RX trace 0 segmented mode */\n>> + cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000000ULL);\n>> + /* Configure RX trace 1 segmented mode */\n>> + cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xAA00000000000001ULL);\n>> + /* Configure CT trace 0 segmented mode */\n>> + cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0xA2B8000000000003ULL);\n>> + /* Configure LA0 trace 0 segmented mode */\n>> + cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x83FFC00000000005ULL);\n>> + /* Configure JM0 trace 0 segmented mode */\n>> + cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000007ULL);\n>> + /* Configure DMA trace 0 segmented mode */\n>> + cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000008ULL);\n>> + /* Configure DMA trace 1 segmented mode */\n>> + cxl_p1_write(adapter, CXL_PSL9_TRACECFG, 0x8200000000000009ULL);\n>> /*\n>> * A response to an ASB_Notify request is returned by the\n>> * system as an MMIO write to the address defined in\n>> * the PSL_TNR_ADDR register\n>> */\n>> - /* PSL_TNR_ADDR */\n>> + /* keep the Reset Value: 0x00020000E0000000 */\n>\n> I was confused by this comment for a while - maybe keep PSL_TNR_ADDR \n> at the beginning of the comment, it's not completely clear from the \n> previous block alone.\n\nokay, will do.\n\n>\n>> +\n>> + /* Enable XSL rty limit */\n>> + cxl_p1_write(adapter, CXL_XSL9_DEF, 0x51F8000000000005ULL);\n>> - /* NORST */\n>> - cxl_p1_write(adapter, CXL_PSL9_DEBUG, 0x8000000000000000ULL);\n>> + /* Change XSL_INV dummy readtheshold */\n>\n> read threshold?\n>\n>> + cxl_p1_write(adapter, CXL_XSL9_INV, 0x0000040007FFC200ULL);\n>> - /* allocate the apc machines */\n>> - cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, 0x40000003FFFF0000ULL);\n>> + if (phb_index == 3) {\n>> + /* disable machines 31-47 and 20-27 for DMA */\n>> + cxl_p1_write(adapter, CXL_PSL9_APCDEDTYPE, \n>> 0x40000FF3FFFF0000ULL);\n>> + }\n>> +\n>> + /* Snoop machines */\n>> + cxl_p1_write(adapter, CXL_PSL9_APCDEDALLOC, 0x800F000200000000ULL);\n>> - /* Disable vc dd1 fix */\n>> - if (cxl_is_power9_dd1())\n>> - cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0400000000000001ULL);\n>> + if (cxl_is_power9_dd1()) {\n>> + /* Disabling deadlock counter CAR */\n>> + cxl_p1_write(adapter, CXL_PSL9_GP_CT, 0x0020000000000001ULL);\n>> + }\n>> return 0;\n>> }\n>>\n>","headers":{"Return-Path":"","X-Original-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Delivered-To":["patchwork-incoming@ozlabs.org","linuxppc-dev@lists.ozlabs.org"],"Received":["from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xdG536kqkz9sRm\n\tfor ;\n\tThu, 24 Aug 2017 17:24:23 +1000 (AEST)","from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xdG535vmNzDrKl\n\tfor ;\n\tThu, 24 Aug 2017 17:24:23 +1000 (AEST)","from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xdG3k1d3MzDqNc\n\tfor ;\n\tThu, 24 Aug 2017 17:23:14 +1000 (AEST)","from pps.filterd (m0098416.ppops.net [127.0.0.1])\n\tby mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7O7JSTa124703\n\tfor ; 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Violators will be prosecuted; \n\tThu, 24 Aug 2017 08:23:07 +0100","from d06av25.portsmouth.uk.ibm.com (d06av25.portsmouth.uk.ibm.com\n\t[9.149.105.61])\n\tby b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with\n\tESMTP id v7O7N6Fk20709510; Thu, 24 Aug 2017 07:23:06 GMT","from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 3473911C04C;\n\tThu, 24 Aug 2017 08:19:46 +0100 (BST)","from d06av25.portsmouth.uk.ibm.com (unknown [127.0.0.1])\n\tby IMSVA (Postfix) with ESMTP id 95DF711C04A;\n\tThu, 24 Aug 2017 08:19:45 +0100 (BST)","from [9.167.235.238] (unknown [9.167.235.238])\n\tby d06av25.portsmouth.uk.ibm.com (Postfix) with ESMTP;\n\tThu, 24 Aug 2017 08:19:45 +0100 (BST)"],"Subject":"Re: [PATCH] cxl: Add support for POWER9 DD2","To":"Andrew Donnellan ,\n\tlinuxppc-dev@lists.ozlabs.org, fbarrat@linux.vnet.ibm.com,\n\tvaibhav@linux.vnet.ibm.com","References":"<1503500286-1684-1-git-send-email-clombard@linux.vnet.ibm.com>\n\t","From":"christophe lombard ","Date":"Thu, 24 Aug 2017 09:23:05 +0200","User-Agent":"Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101\n\tThunderbird/52.2.1","MIME-Version":"1.0","In-Reply-To":"","Content-Type":"text/plain; charset=utf-8; format=flowed","Content-Transfer-Encoding":"8bit","Content-Language":"fr-xx-classique","X-TM-AS-GCONF":"00","x-cbid":"17082407-0020-0000-0000-000003B0E6C4","X-IBM-AV-DETECTION":"SAVI=unused REMOTE=unused XFE=unused","x-cbparentid":"17082407-0021-0000-0000-000042406A96","Message-Id":"<662aff24-cb60-432c-a6b8-cd04e7498711@linux.vnet.ibm.com>","X-Proofpoint-Virus-Version":"vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-24_03:, , signatures=0","X-Proofpoint-Spam-Details":"rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=0\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708240119","X-BeenThere":"linuxppc-dev@lists.ozlabs.org","X-Mailman-Version":"2.1.23","Precedence":"list","List-Id":"Linux on PowerPC Developers Mail List\n\t","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Errors-To":"linuxppc-dev-bounces+patchwork-incoming=ozlabs.org@lists.ozlabs.org","Sender":"\"Linuxppc-dev\"\n\t"}}]