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GET /api/1.2/patches/804294/?format=api
{ "id": 804294, "url": "http://patchwork.ozlabs.org/api/1.2/patches/804294/?format=api", "web_url": "http://patchwork.ozlabs.org/project/skiboot/patch/20170822064927.15200-4-hegdevasant@linux.vnet.ibm.com/", "project": { "id": 44, "url": "http://patchwork.ozlabs.org/api/1.2/projects/44/?format=api", "name": "skiboot firmware development", "link_name": "skiboot", "list_id": "skiboot.lists.ozlabs.org", "list_email": "skiboot@lists.ozlabs.org", "web_url": "http://github.com/open-power/skiboot", "scm_url": "http://github.com/open-power/skiboot", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20170822064927.15200-4-hegdevasant@linux.vnet.ibm.com>", "list_archive_url": null, "date": "2017-08-22T06:49:26", "name": "[4/5] hdata: Add memory hierarchy under xscom node", "commit_ref": null, "pull_url": null, "state": "superseded", "archived": false, "hash": "e68bbf08a55f98fc239e5d23a490bb9ec957f1ca", "submitter": { "id": 22361, "url": "http://patchwork.ozlabs.org/api/1.2/people/22361/?format=api", "name": "Vasant Hegde", "email": "hegdevasant@linux.vnet.ibm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/skiboot/patch/20170822064927.15200-4-hegdevasant@linux.vnet.ibm.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/804294/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/804294/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Delivered-To": [ "patchwork-incoming@bilbo.ozlabs.org", "skiboot@lists.ozlabs.org" ], "Received": [ "from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68])\n\t(using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3xc1Rr6FXtz9t2m\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 22 Aug 2017 16:51:20 +1000 (AEST)", "from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3])\n\tby lists.ozlabs.org (Postfix) with ESMTP id 3xc1Rr4tgLzDrJm\n\tfor <incoming@patchwork.ozlabs.org>;\n\tTue, 22 Aug 2017 16:51:20 +1000 (AEST)", "from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com\n\t[148.163.158.5])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256\n\tbits)) (No client certificate requested)\n\tby lists.ozlabs.org (Postfix) with ESMTPS id 3xc1RB75mrzDrJ7\n\tfor <skiboot@lists.ozlabs.org>; Tue, 22 Aug 2017 16:50:46 +1000 (AEST)", "from pps.filterd (m0098421.ppops.net [127.0.0.1])\n\tby mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id\n\tv7M6nELx021086\n\tfor <skiboot@lists.ozlabs.org>; Tue, 22 Aug 2017 02:50:44 -0400", "from e23smtp03.au.ibm.com (e23smtp03.au.ibm.com [202.81.31.145])\n\tby mx0a-001b2d01.pphosted.com with ESMTP id 2cgcmvv834-1\n\t(version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT)\n\tfor <skiboot@lists.ozlabs.org>; Tue, 22 Aug 2017 02:50:44 -0400", "from localhost\n\tby e23smtp03.au.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use\n\tOnly! Violators will be prosecuted\n\tfor <skiboot@lists.ozlabs.org> from <hegdevasant@linux.vnet.ibm.com>; \n\tTue, 22 Aug 2017 16:50:41 +1000", "from d23relay07.au.ibm.com (202.81.31.226)\n\tby e23smtp03.au.ibm.com (202.81.31.209) with IBM ESMTP SMTP Gateway:\n\tAuthorized Use Only! Violators will be prosecuted; \n\tTue, 22 Aug 2017 16:50:39 +1000", "from d23av05.au.ibm.com (d23av05.au.ibm.com [9.190.234.119])\n\tby d23relay07.au.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id\n\tv7M6oURV37290154\n\tfor <skiboot@lists.ozlabs.org>; Tue, 22 Aug 2017 16:50:38 +1000", "from d23av05.au.ibm.com (localhost [127.0.0.1])\n\tby d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVout) with ESMTP id\n\tv7M6o6PI026822\n\tfor <skiboot@lists.ozlabs.org>; Tue, 22 Aug 2017 16:50:06 +1000", "from hegdevasant.in.ibm.com (hegdevasant.in.ibm.com [9.122.211.32]\n\t(may be forged))\n\tby d23av05.au.ibm.com (8.14.4/8.14.4/NCO v10.0 AVin) with ESMTP id\n\tv7M6o05r025980; Tue, 22 Aug 2017 16:50:04 +1000" ], "From": "Vasant Hegde <hegdevasant@linux.vnet.ibm.com>", "To": "skiboot@lists.ozlabs.org", "Date": "Tue, 22 Aug 2017 12:19:26 +0530", "X-Mailer": "git-send-email 2.9.3", "In-Reply-To": "<20170822064927.15200-1-hegdevasant@linux.vnet.ibm.com>", "References": "<20170822064927.15200-1-hegdevasant@linux.vnet.ibm.com>", "X-TM-AS-MML": "disable", "x-cbid": "17082206-0008-0000-0000-000001544479", "X-IBM-AV-DETECTION": "SAVI=unused REMOTE=unused XFE=unused", "x-cbparentid": "17082206-0009-0000-0000-000009872AC2", "Message-Id": "<20170822064927.15200-4-hegdevasant@linux.vnet.ibm.com>", "X-Proofpoint-Virus-Version": "vendor=fsecure engine=2.50.10432:, ,\n\tdefinitions=2017-08-22_03:, , signatures=0", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n\tspamscore=0 suspectscore=1\n\tmalwarescore=0 phishscore=0 adultscore=0 bulkscore=0 classifier=spam\n\tadjust=0 reason=mlx scancount=1 engine=8.0.1-1707230000\n\tdefinitions=main-1708220107", "Subject": "[Skiboot] [PATCH 4/5] hdata: Add memory hierarchy under xscom node", "X-BeenThere": "skiboot@lists.ozlabs.org", "X-Mailman-Version": "2.1.23", "Precedence": "list", "List-Id": "Mailing list for skiboot development <skiboot.lists.ozlabs.org>", "List-Unsubscribe": "<https://lists.ozlabs.org/options/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=unsubscribe>", "List-Archive": "<http://lists.ozlabs.org/pipermail/skiboot/>", "List-Post": "<mailto:skiboot@lists.ozlabs.org>", "List-Help": "<mailto:skiboot-request@lists.ozlabs.org?subject=help>", "List-Subscribe": "<https://lists.ozlabs.org/listinfo/skiboot>,\n\t<mailto:skiboot-request@lists.ozlabs.org?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org", "Sender": "\"Skiboot\"\n\t<skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org>" }, "content": "We have memory to chip mapping. But doesn't have complete memory hierarchy.\nThis patch adds memory hierarchy under xscom node. This is specific to\nP9 system as these hierarchy may change between processor generation.\n\nIt uses memory controller ID details and populates nodes like:\n xscom@<addr>/mcbist@<mcbist_id>/mcs@<mcs_id>/mca@<mca_id>/dimm@<resource_id>\n\nAlso this patch adds few properties under dimm node.\nFinally make sure xscom nodes created before calling memory_parse().\n\nSigned-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>\n---\n hdata/memory.c | 118 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++-\n hdata/spira.c | 6 +--\n 2 files changed, 119 insertions(+), 5 deletions(-)", "diff": "diff --git a/hdata/memory.c b/hdata/memory.c\nindex dbb0ac4..d1570eb 100644\n--- a/hdata/memory.c\n+++ b/hdata/memory.c\n@@ -22,6 +22,7 @@\n #include <mem_region.h>\n #include <types.h>\n #include <inttypes.h>\n+#include <processor.h>\n \n #include \"spira.h\"\n #include \"hdata.h\"\n@@ -44,8 +45,13 @@ struct HDIF_ms_area_address_range {\n \t__be32 chip;\n \t__be32 mirror_attr;\n \t__be64 mirror_start;\n+\t__be32 controller_id;\n } __packed;\n \n+#define MS_CONTROLLER_MCBIST_ID(id)\tGETFIELD(PPC_BITMASK32(0, 1), id)\n+#define MS_CONTROLLER_MCS_ID(id)\tGETFIELD(PPC_BITMASK32(4, 7), id)\n+#define MS_CONTROLLER_MCA_ID(id)\tGETFIELD(PPC_BITMASK32(8, 23), id)\n+\n struct HDIF_ms_area_id {\n \t__be16 id;\n #define MS_PTYPE_RISER_CARD\t0x8000\n@@ -313,6 +319,109 @@ static void vpd_add_ram_area(const struct HDIF_common_hdr *msarea)\n \t}\n }\n \n+static void add_mca_dimm_info(struct dt_node *mca,\n+\t\t\t const struct HDIF_common_hdr *msarea)\n+{\n+\tunsigned int i;\n+\tconst struct HDIF_child_ptr *ramptr;\n+\tconst struct HDIF_common_hdr *ramarea;\n+\tconst struct spira_fru_id *fru_id;\n+\tconst struct HDIF_ram_area_id *ram_id;\n+\tconst struct HDIF_ram_area_size *ram_area_sz;\n+\tstruct dt_node *dimm;\n+\n+\tramptr = HDIF_child_arr(msarea, 0);\n+\tif (!CHECK_SPPTR(ramptr)) {\n+\t\tprerror(\"MS AREA: No RAM area at %p\\n\", msarea);\n+\t\treturn;\n+\t}\n+\n+\tfor (i = 0; i < be32_to_cpu(ramptr->count); i++) {\n+\t\tramarea = HDIF_child(msarea, ramptr, i, \"RAM \");\n+\t\tif (!CHECK_SPPTR(ramarea))\n+\t\t\tcontinue;\n+\n+\t\tfru_id = HDIF_get_idata(ramarea, 0, NULL);\n+\t\tif (!fru_id)\n+\t\t\tcontinue;\n+\n+\t\t/* Use Resource ID to add dimm node */\n+\t\tdimm = dt_find_by_name_addr(mca, \"dimm\",\n+\t\t\t\t\t be16_to_cpu(fru_id->rsrc_id));\n+\t\tif (dimm)\n+\t\t\tcontinue;\n+\t\tdimm= dt_new_addr(mca, \"dimm\", be16_to_cpu(fru_id->rsrc_id));\n+\t\tassert(dimm);\n+\n+\t\t/* Add location code */\n+\t\tslca_vpd_add_loc_code(dimm, be16_to_cpu(fru_id->slca_index));\n+\n+\t\t/* DIMM size */\n+\t\tram_area_sz = HDIF_get_idata(ramarea, 3, NULL);\n+\t\tif (!CHECK_SPPTR(ram_area_sz))\n+\t\t\tcontinue;\n+\t\tdt_add_property_cells(dimm, \"size\", be32_to_cpu(ram_area_sz->mb));\n+\n+\t\t/* DIMM state */\n+\t\tram_id = HDIF_get_idata(ramarea, 2, NULL);\n+\t\tif (!CHECK_SPPTR(ram_id))\n+\t\t\tcontinue;\n+\t\tif ((be16_to_cpu(ram_id->flags) & RAM_AREA_INSTALLED) &&\n+\t\t (be16_to_cpu(ram_id->flags) & RAM_AREA_FUNCTIONAL))\n+\t\t\tdt_add_property_string(dimm, \"status\", \"okay\");\n+\t\telse\n+\t\t\tdt_add_property_string(dimm, \"status\", \"disabled\");\n+\t}\n+}\n+\n+static void add_memory_controller(const struct HDIF_common_hdr *msarea,\n+\t\t\t\t const struct HDIF_ms_area_address_range *arange)\n+{\n+\tuint32_t chip_id, version;\n+\tuint32_t controller_id, mcbist_id, mcs_id, mca_id;\n+\tstruct dt_node *xscom, *mcbist, *mcs, *mca;\n+\n+\t/*\n+\t * Memory hierarchy may change between processor version. Presently\n+\t * its creating memory hierarchy for P9 (Nimbus) only.\n+\t */\n+\tversion = PVR_TYPE(mfspr(SPR_PVR));\n+\tif (version != PVR_TYPE_P9)\n+\t\treturn;\n+\n+\tchip_id = pcid_to_chip_id(be32_to_cpu(arange->chip));\n+\tcontroller_id = be32_to_cpu(arange->controller_id);\n+\txscom = find_xscom_for_chip(chip_id);\n+\tif (!xscom) {\n+\t\tprlog(PR_WARNING,\n+\t\t \"MS AREA: Can't find XSCOM for chip %d\\n\", chip_id);\n+\t\treturn;\n+\t}\n+\n+\tmcbist_id = MS_CONTROLLER_MCBIST_ID(controller_id);\n+\tmcbist = dt_find_by_name_addr(xscom, \"mcbist\", mcbist_id);\n+\tif (!mcbist) {\n+\t\tmcbist = dt_new_addr(xscom, \"mcbist\", mcbist_id);\n+\t\tassert(mcbist);\n+\t}\n+\n+\tmcs_id = MS_CONTROLLER_MCS_ID(controller_id);\n+\tmcs = dt_find_by_name_addr(mcbist, \"mcs\", mcs_id);\n+\tif (!mcs) {\n+\t\tmcs = dt_new_addr(mcbist, \"mcs\", mcs_id);\n+\t\tassert(mcs);\n+\t}\n+\n+\tmca_id = MS_CONTROLLER_MCA_ID(controller_id);\n+\tmca = dt_find_by_name_addr(mcs, \"mca\", mca_id);\n+\tif (!mca) {\n+\t\tmca = dt_new_addr(mcs, \"mca\", mca_id);\n+\t\tassert(mca);\n+\t}\n+\n+\tadd_mca_dimm_info(mca, msarea);\n+}\n+\n static void get_msareas(struct dt_node *root,\n \t\t\tconst struct HDIF_common_hdr *ms_vpd)\n {\n@@ -332,7 +441,7 @@ static void get_msareas(struct dt_node *root,\n \t\tconst struct HDIF_ms_area_address_range *arange;\n \t\tconst struct HDIF_ms_area_id *id;\n \t\tconst void *fruid;\n-\t\tunsigned int size, j;\n+\t\tunsigned int size, j, offset;\n \t\tu16 flags;\n \n \t\tmsarea = HDIF_child(ms_vpd, msptr, i, \"MSAREA\");\n@@ -372,7 +481,8 @@ static void get_msareas(struct dt_node *root,\n \t\t\treturn;\n \t\t}\n \n-\t\tif (be32_to_cpu(arr->eactsz) < sizeof(*arange)) {\n+\t\toffset = offsetof(struct HDIF_ms_area_address_range, mirror_start);\n+\t\tif (be32_to_cpu(arr->eactsz) < offset) {\n \t\t\tprerror(\"MS VPD: %p msarea #%i arange size too small!\\n\",\n \t\t\t\tms_vpd, i);\n \t\t\treturn;\n@@ -392,6 +502,10 @@ static void get_msareas(struct dt_node *root,\n \t\t/* This offset is from the arr, not the header! */\n \t\tarange = (void *)arr + be32_to_cpu(arr->offset);\n \t\tfor (j = 0; j < be32_to_cpu(arr->ecnt); j++) {\n+\t\t\toffset = offsetof(struct HDIF_ms_area_address_range, controller_id);\n+\t\t\tif (be32_to_cpu(arr->eactsz) >= offset)\n+\t\t\t\tadd_memory_controller(msarea, arange);\n+\n \t\t\tif (!add_address_range(root, id, arange))\n \t\t\t\treturn;\n \t\t\tarange = (void *)arange + be32_to_cpu(arr->esize);\ndiff --git a/hdata/spira.c b/hdata/spira.c\nindex b58be7c..8833271 100644\n--- a/hdata/spira.c\n+++ b/hdata/spira.c\n@@ -1314,12 +1314,12 @@ int parse_hdat(bool is_opal)\n \t/* IPL params */\n \tadd_iplparams();\n \n-\t/* Parse MS VPD */\n-\tmemory_parse();\n-\n \t/* Add XSCOM node (must be before chiptod, IO and FSP) */\n \tadd_xscom();\n \n+\t/* Parse MS VPD */\n+\tmemory_parse();\n+\n \t/* Add any FSPs */\n \tfsp_parse();\n \n", "prefixes": [ "4/5" ] }