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GET /api/1.2/patches/801900/?format=api
{ "id": 801900, "url": "http://patchwork.ozlabs.org/api/1.2/patches/801900/?format=api", "web_url": "http://patchwork.ozlabs.org/project/uboot/patch/1502862122-14771-14-git-send-email-bmeng.cn@gmail.com/", "project": { "id": 18, "url": "http://patchwork.ozlabs.org/api/1.2/projects/18/?format=api", "name": "U-Boot", "link_name": "uboot", "list_id": "u-boot.lists.denx.de", "list_email": "u-boot@lists.denx.de", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<1502862122-14771-14-git-send-email-bmeng.cn@gmail.com>", "list_archive_url": null, "date": "2017-08-16T05:42:02", "name": "[U-Boot,13/13] x86: Support Intel Cherry Hill board", "commit_ref": "eb45787b396f197f2d4c3bc3556c48421528f62b", "pull_url": null, "state": "accepted", "archived": false, "hash": "a801e0ed0f8a4317a163d881e2cab3d004551b26", "submitter": { "id": 64981, "url": "http://patchwork.ozlabs.org/api/1.2/people/64981/?format=api", "name": "Bin Meng", "email": "bmeng.cn@gmail.com" }, "delegate": { "id": 56520, "url": "http://patchwork.ozlabs.org/api/1.2/users/56520/?format=api", "username": "bmeng", "first_name": "Bin", "last_name": "Meng", "email": "bmeng.cn@gmail.com" }, "mbox": "http://patchwork.ozlabs.org/project/uboot/patch/1502862122-14771-14-git-send-email-bmeng.cn@gmail.com/mbox/", "series": [], "comments": "http://patchwork.ozlabs.org/api/patches/801900/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/801900/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<u-boot-bounces@lists.denx.de>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@bilbo.ozlabs.org", "Authentication-Results": [ "ozlabs.org;\n\tspf=none (mailfrom) smtp.mailfrom=lists.denx.de\n\t(client-ip=81.169.180.215; helo=lists.denx.de;\n\tenvelope-from=u-boot-bounces@lists.denx.de;\n\treceiver=<UNKNOWN>)", "ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"UXY8qOy7\"; dkim-atps=neutral" ], "Received": [ "from lists.denx.de (dione.denx.de [81.169.180.215])\n\tby ozlabs.org (Postfix) with ESMTP id 3xXJFK2Tf9z9s78\n\tfor <incoming@patchwork.ozlabs.org>;\n\tWed, 16 Aug 2017 15:44:21 +1000 (AEST)", "by lists.denx.de (Postfix, from userid 105)\n\tid 18DADC21E12; Wed, 16 Aug 2017 05:41:37 +0000 (UTC)", "from lists.denx.de (localhost [IPv6:::1])\n\tby lists.denx.de (Postfix) with ESMTP id B324AC21DE8;\n\tWed, 16 Aug 2017 05:39:11 +0000 (UTC)", "by lists.denx.de (Postfix, from userid 105)\n\tid 54827C21D99; Wed, 16 Aug 2017 05:38:05 +0000 (UTC)", "from mail-io0-f170.google.com (mail-io0-f170.google.com\n\t[209.85.223.170])\n\tby lists.denx.de (Postfix) with ESMTPS id 840C1C21E18\n\tfor <u-boot@lists.denx.de>; Wed, 16 Aug 2017 05:38:01 +0000 (UTC)", "by mail-io0-f170.google.com with SMTP id m88so9871814iod.2\n\tfor <u-boot@lists.denx.de>; Tue, 15 Aug 2017 22:38:01 -0700 (PDT)", "from ala-d2121-lx1.wrs.com (unknown-156-139.windriver.com.\n\t[147.11.156.139])\n\tby smtp.gmail.com with ESMTPSA id g13sm30442ioi.0.2017.08.15.22.37.58\n\t(version=TLS1_1 cipher=ECDHE-RSA-AES128-SHA bits=128/128);\n\tTue, 15 Aug 2017 22:37:58 -0700 (PDT)" ], "X-Spam-Checker-Version": "SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de", "X-Spam-Level": "", "X-Spam-Status": "No, score=0.8 required=5.0 tests=FREEMAIL_FROM,\n\tRCVD_IN_DNSWL_NONE,RCVD_IN_MSPIKE_H2,T_DKIM_INVALID,UPPERCASE_50_75\n\tautolearn=no autolearn_force=no version=3.4.0", "DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=from:to:subject:date:message-id:in-reply-to:references;\n\tbh=/vnGQBwomRdi+9mqLHG2j4I7dcGaPqIOO9szF3sG4aE=;\n\tb=UXY8qOy7DXlZTlHcrv741Pt8imkHwRmIy1HnQFH9Zz/pLYSwCckY648XmiB1daM0V1\n\tgh8gkSaGF1lCyl7EdG5ytlT4uwXp/5O9WXpy4hhT706aTDhquIA9LjVBFwty/XjOzMXJ\n\t9dB6DvcUiAcT9H1bdmK8od06HiMcceg6nh6AFEbieLsBFitk1euD0I1P5QlEtRiv4alD\n\tW2BDEYwAx3i3TjEuDo4dHKQTdvTEwJuWZpAeaaCyMY8PrFmdYc3MqTD4lt2hDMOhXHkP\n\t5L14AqKxlcbtk6RjerzD+hEAR34vhfYftKmVwjx429NTs0tLAJdYWjpHGZJcWuroQrZq\n\tFcxw==", "X-Google-DKIM-Signature": "v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:from:to:subject:date:message-id:in-reply-to\n\t:references;\n\tbh=/vnGQBwomRdi+9mqLHG2j4I7dcGaPqIOO9szF3sG4aE=;\n\tb=hzhIFCoDE6CgVjdy++fzSiKeao6+my+KBxZM5i1ytMx+jWikvxW1xXfgxSswNpHu8j\n\tgzowqC7oyOkBCxUGvSDp7aINVOKhwxalM2NVpaCtLA2G6iZckF5MSrBoePst83KxTHSS\n\tCoCdzoykOkGszMKt4Lwdv1XYq9PMMX9IytwjJb7vbXfOjgzTavDqIjCQKKwFCG1Syzna\n\tanyoB4U1bV9i+bBdn1ILq37tZvcbFjOEtHrhlWg/X+MC5a3CUOUabA56VYtDIJ0Qf7kd\n\toc5fMBqvSxp46k824twegpLNisZBFm9I9g+ty6TtGoO7zYqGebZRkd5wzC7e9tibnrl9\n\tNZbA==", "X-Gm-Message-State": "AHYfb5gkk4C+xw9QN1TQovjRdDxjJEE5KVGf7SWNHFdp/+qpduSS2H0w\n\tG9I5vBNAP4xfGw==", "X-Received": "by 10.107.7.6 with SMTP id 6mr499023ioh.275.1502861879860;\n\tTue, 15 Aug 2017 22:37:59 -0700 (PDT)", "From": "Bin Meng <bmeng.cn@gmail.com>", "To": "Simon Glass <sjg@chromium.org>,\n\tU-Boot Mailing List <u-boot@lists.denx.de>", "Date": "Tue, 15 Aug 2017 22:42:02 -0700", "Message-Id": "<1502862122-14771-14-git-send-email-bmeng.cn@gmail.com>", "X-Mailer": "git-send-email 1.7.9.5", "In-Reply-To": "<1502862122-14771-1-git-send-email-bmeng.cn@gmail.com>", "References": "<1502862122-14771-1-git-send-email-bmeng.cn@gmail.com>", "Subject": "[U-Boot] [PATCH 13/13] x86: Support Intel Cherry Hill board", "X-BeenThere": "u-boot@lists.denx.de", "X-Mailman-Version": "2.1.18", "Precedence": "list", "List-Id": "U-Boot discussion <u-boot.lists.denx.de>", "List-Unsubscribe": "<https://lists.denx.de/options/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=unsubscribe>", "List-Archive": "<http://lists.denx.de/pipermail/u-boot/>", "List-Post": "<mailto:u-boot@lists.denx.de>", "List-Help": "<mailto:u-boot-request@lists.denx.de?subject=help>", "List-Subscribe": "<https://lists.denx.de/listinfo/u-boot>,\n\t<mailto:u-boot-request@lists.denx.de?subject=subscribe>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "base64", "Errors-To": "u-boot-bounces@lists.denx.de", "Sender": "\"U-Boot\" <u-boot-bounces@lists.denx.de>" }, "content": "This adds support to Intel Cherry Hill board, a board based on\nIntel Braswell SoC. The following devices are validated:\n\n- serial port as the serial console\n- on-board Realtek 8169 ethernet controller\n- SATA AHCI controller\n- EMMC/SDHC controller\n- USB 3.0 xHCI controller\n- PCIe x1 slot with a graphics card\n- ICH SPI controller with an 8MB Macronix SPI flash\n- Integrated graphics device as the video console\n\nSigned-off-by: Bin Meng <bmeng.cn@gmail.com>\n\n---\n\n arch/x86/dts/Makefile | 1 +\n arch/x86/dts/cherryhill.dts | 215 +++++++++++++\n board/intel/Kconfig | 10 +\n board/intel/cherryhill/Kconfig | 25 ++\n board/intel/cherryhill/MAINTAINERS | 6 +\n board/intel/cherryhill/Makefile | 7 +\n board/intel/cherryhill/cherryhill.c | 596 ++++++++++++++++++++++++++++++++++++\n board/intel/cherryhill/start.S | 9 +\n configs/cherryhill_defconfig | 36 +++\n doc/README.x86 | 30 ++\n include/configs/cherryhill.h | 22 ++\n 11 files changed, 957 insertions(+)\n create mode 100644 arch/x86/dts/cherryhill.dts\n create mode 100644 board/intel/cherryhill/Kconfig\n create mode 100644 board/intel/cherryhill/MAINTAINERS\n create mode 100644 board/intel/cherryhill/Makefile\n create mode 100644 board/intel/cherryhill/cherryhill.c\n create mode 100644 board/intel/cherryhill/start.S\n create mode 100644 configs/cherryhill_defconfig\n create mode 100644 include/configs/cherryhill.h", "diff": "diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile\nindex 6589495..6d0c4b6 100644\n--- a/arch/x86/dts/Makefile\n+++ b/arch/x86/dts/Makefile\n@@ -3,6 +3,7 @@\n #\n \n dtb-y += bayleybay.dtb \\\n+\tcherryhill.dtb \\\n \tchromebook_link.dtb \\\n \tchromebox_panther.dtb \\\n \tchromebook_samus.dtb \\\ndiff --git a/arch/x86/dts/cherryhill.dts b/arch/x86/dts/cherryhill.dts\nnew file mode 100644\nindex 0000000..1ccb605\n--- /dev/null\n+++ b/arch/x86/dts/cherryhill.dts\n@@ -0,0 +1,215 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+/dts-v1/;\n+\n+#include <asm/arch-braswell/fsp/fsp_configs.h>\n+#include <dt-bindings/interrupt-router/intel-irq.h>\n+\n+/include/ \"skeleton.dtsi\"\n+/include/ \"serial.dtsi\"\n+/include/ \"rtc.dtsi\"\n+/include/ \"tsc_timer.dtsi\"\n+\n+/ {\n+\tmodel = \"Intel Cherry Hill\";\n+\tcompatible = \"intel,cherryhill\", \"intel,braswell\";\n+\n+\taliases {\n+\t\tserial0 = &serial;\n+\t\tspi0 = &spi;\n+\t};\n+\n+\tconfig {\n+\t\tsilent_console = <0>;\n+\t};\n+\n+\tchosen {\n+\t\tstdout-path = \"/serial\";\n+\t};\n+\n+\tcpus {\n+\t\t#address-cells = <1>;\n+\t\t#size-cells = <0>;\n+\n+\t\tcpu@0 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"intel,braswell-cpu\";\n+\t\t\treg = <0>;\n+\t\t\tintel,apic-id = <0>;\n+\t\t};\n+\n+\t\tcpu@1 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"intel,braswell-cpu\";\n+\t\t\treg = <1>;\n+\t\t\tintel,apic-id = <2>;\n+\t\t};\n+\n+\t\tcpu@2 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"intel,braswell-cpu\";\n+\t\t\treg = <2>;\n+\t\t\tintel,apic-id = <4>;\n+\t\t};\n+\n+\t\tcpu@3 {\n+\t\t\tdevice_type = \"cpu\";\n+\t\t\tcompatible = \"intel,braswell-cpu\";\n+\t\t\treg = <3>;\n+\t\t\tintel,apic-id = <6>;\n+\t\t};\n+\t};\n+\n+\tpci {\n+\t\tcompatible = \"pci-x86\";\n+\t\t#address-cells = <3>;\n+\t\t#size-cells = <2>;\n+\t\tu-boot,dm-pre-reloc;\n+\t\tranges = <0x02000000 0x0 0x80000000 0x80000000 0 0x40000000\n+\t\t\t 0x42000000 0x0 0xc0000000 0xc0000000 0 0x20000000\n+\t\t\t 0x01000000 0x0 0x2000 0x2000 0 0xe000>;\n+\n+\t\tpch@1f,0 {\n+\t\t\treg = <0x0000f800 0 0 0 0>;\n+\t\t\tcompatible = \"intel,pch9\";\n+\t\t\t#address-cells = <1>;\n+\t\t\t#size-cells = <1>;\n+\n+\t\t\tirq-router {\n+\t\t\t\tcompatible = \"intel,irq-router\";\n+\t\t\t\tintel,pirq-config = \"ibase\";\n+\t\t\t\tintel,ibase-offset = <0x50>;\n+\t\t\t\tintel,pirq-link = <8 8>;\n+\t\t\t\tintel,pirq-mask = <0xdee0>;\n+\t\t\t\tintel,pirq-routing = <\n+\t\t\t\t\t/* Braswell PCI devices */\n+\t\t\t\t\tPCI_BDF(0, 2, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 3, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 11, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 16, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 17, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 18, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 19, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 20, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 21, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 24, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 24, 1) INTC PIRQC\n+\t\t\t\t\tPCI_BDF(0, 24, 2) INTD PIRQD\n+\t\t\t\t\tPCI_BDF(0, 24, 3) INTB PIRQB\n+\t\t\t\t\tPCI_BDF(0, 24, 4) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 24, 5) INTC PIRQC\n+\t\t\t\t\tPCI_BDF(0, 24, 6) INTD PIRQD\n+\t\t\t\t\tPCI_BDF(0, 24, 7) INTB PIRQB\n+\t\t\t\t\tPCI_BDF(0, 26, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 27, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 28, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 28, 1) INTB PIRQB\n+\t\t\t\t\tPCI_BDF(0, 28, 2) INTC PIRQC\n+\t\t\t\t\tPCI_BDF(0, 28, 3) INTD PIRQD\n+\t\t\t\t\tPCI_BDF(0, 30, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 30, 3) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 30, 4) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(0, 31, 0) INTB PIRQB\n+\t\t\t\t\tPCI_BDF(0, 31, 3) INTB PIRQB\n+\n+\t\t\t\t\t/*\n+\t\t\t\t\t * PCIe root ports downstream\n+\t\t\t\t\t * interrupts\n+\t\t\t\t\t */\n+\t\t\t\t\tPCI_BDF(1, 0, 0) INTA PIRQA\n+\t\t\t\t\tPCI_BDF(1, 0, 0) INTB PIRQB\n+\t\t\t\t\tPCI_BDF(1, 0, 0) INTC PIRQC\n+\t\t\t\t\tPCI_BDF(1, 0, 0) INTD PIRQD\n+\t\t\t\t\tPCI_BDF(2, 0, 0) INTA PIRQB\n+\t\t\t\t\tPCI_BDF(2, 0, 0) INTB PIRQC\n+\t\t\t\t\tPCI_BDF(2, 0, 0) INTC PIRQD\n+\t\t\t\t\tPCI_BDF(2, 0, 0) INTD PIRQA\n+\t\t\t\t\tPCI_BDF(3, 0, 0) INTA PIRQC\n+\t\t\t\t\tPCI_BDF(3, 0, 0) INTB PIRQD\n+\t\t\t\t\tPCI_BDF(3, 0, 0) INTC PIRQA\n+\t\t\t\t\tPCI_BDF(3, 0, 0) INTD PIRQB\n+\t\t\t\t\tPCI_BDF(4, 0, 0) INTA PIRQD\n+\t\t\t\t\tPCI_BDF(4, 0, 0) INTB PIRQA\n+\t\t\t\t\tPCI_BDF(4, 0, 0) INTC PIRQB\n+\t\t\t\t\tPCI_BDF(4, 0, 0) INTD PIRQC\n+\t\t\t\t>;\n+\t\t\t};\n+\n+\t\t\tspi: spi {\n+\t\t\t\t#address-cells = <1>;\n+\t\t\t\t#size-cells = <0>;\n+\t\t\t\tcompatible = \"intel,ich9-spi\";\n+\n+\t\t\t\tspi-flash@0 {\n+\t\t\t\t\t#address-cells = <1>;\n+\t\t\t\t\t#size-cells = <1>;\n+\t\t\t\t\treg = <0>;\n+\t\t\t\t\tcompatible = \"macronix,mx25u6435f\", \"spi-flash\";\n+\t\t\t\t\tmemory-map = <0xff800000 0x00800000>;\n+\t\t\t\t\trw-mrc-cache {\n+\t\t\t\t\t\tlabel = \"rw-mrc-cache\";\n+\t\t\t\t\t\treg = <0x005e0000 0x00010000>;\n+\t\t\t\t\t};\n+\t\t\t\t};\n+\t\t\t};\n+\t\t};\n+\t};\n+\n+\tfsp {\n+\t\tcompatible = \"intel,braswell-fsp\";\n+\t\tfsp,memory-upd {\n+\t\t\tcompatible = \"intel,braswell-fsp-memory\";\n+\t\t\tfsp,mrc-init-tseg-size = <MRC_INIT_TSEG_SIZE_4MB>;\n+\t\t\tfsp,mrc-init-mmio-size = <MRC_INIT_MMIO_SIZE_2048MB>;\n+\t\t\tfsp,mrc-init-spd-addr1 = <0xa0>;\n+\t\t\tfsp,mrc-init-spd-addr2 = <0xa2>;\n+\t\t\tfsp,igd-dvmt50-pre-alloc = <IGD_DVMT50_PRE_ALLOC_32MB>;\n+\t\t\tfsp,aperture-size = <APERTURE_SIZE_256MB>;\n+\t\t\tfsp,gtt-size = <GTT_SIZE_1MB>;\n+\t\t\tfsp,enable-dvfs;\n+\t\t\tfsp,memory-type = <DRAM_TYPE_DDR3>;\n+\t\t};\n+\t\tfsp,silicon-upd {\n+\t\t\tcompatible = \"intel,braswell-fsp-silicon\";\n+\t\t\tfsp,sdcard-mode = <SDCARD_MODE_PCI>;\n+\t\t\tfsp,enable-hsuart1;\n+\t\t\tfsp,enable-sata;\n+\t\t\tfsp,enable-xhci;\n+\t\t\tfsp,lpe-mode = <LPE_MODE_PCI>;\n+\t\t\tfsp,enable-dma0;\n+\t\t\tfsp,enable-dma1;\n+\t\t\tfsp,enable-i2c0;\n+\t\t\tfsp,enable-i2c1;\n+\t\t\tfsp,enable-i2c2;\n+\t\t\tfsp,enable-i2c3;\n+\t\t\tfsp,enable-i2c4;\n+\t\t\tfsp,enable-i2c5;\n+\t\t\tfsp,enable-i2c6;\n+\t\t\tfsp,emmc-mode = <EMMC_MODE_PCI>;\n+\t\t\tfsp,sata-speed = <SATA_SPEED_GEN3>;\n+\t\t\tfsp,pmic-i2c-bus = <0>;\n+\t\t\tfsp,enable-isp;\n+\t\t\tfsp,isp-pci-dev-config = <ISP_PCI_DEV_CONFIG_2>;\n+\t\t\tfsp,turbo-mode;\n+\t\t\tfsp,pnp-settings = <PNP_SETTING_POWER_AND_PERF>;\n+\t\t\tfsp,sd-detect-chk;\n+\t\t};\n+\t};\n+\n+\tmicrocode {\n+\t\tupdate@0 {\n+#include \"microcode/m01406c2220.dtsi\"\n+\t\t};\n+\t\tupdate@1 {\n+#include \"microcode/m01406c3363.dtsi\"\n+\t\t};\n+\t\tupdate@2 {\n+#include \"microcode/m01406c440a.dtsi\"\n+\t\t};\n+\t};\n+\n+};\ndiff --git a/board/intel/Kconfig b/board/intel/Kconfig\nindex d7d950e..4ebf808 100644\n--- a/board/intel/Kconfig\n+++ b/board/intel/Kconfig\n@@ -18,6 +18,15 @@ config TARGET_BAYLEYBAY\n \t 4GB memory, HDMI/DP/VGA display, HD audio, SATA, USB2, USB3, SD, eMMC,\n \t PCIe and some other sensor interfaces.\n \n+config TARGET_CHERRYHILL\n+\tbool \"Cherry Hill\"\n+\thelp\n+\t This is the Intel Cherry Hill Customer Reference Board. It is in a\n+\t mini-ITX form factor containing the Intel Braswell SoC, which has\n+\t a 64-bit quad-core, single-thread, Intel Atom processor, along with\n+\t serial console, 10/100/1000 Ethernet, SD-Card, USB 2/3, SATA, PCIe,\n+\t some GPIOs, one HDMI and two DP video out.\n+\n config TARGET_COUGARCANYON2\n \tbool \"Cougar Canyon 2\"\n \thelp\n@@ -69,6 +78,7 @@ config TARGET_MINNOWMAX\n endchoice\n \n source \"board/intel/bayleybay/Kconfig\"\n+source \"board/intel/cherryhill/Kconfig\"\n source \"board/intel/cougarcanyon2/Kconfig\"\n source \"board/intel/crownbay/Kconfig\"\n source \"board/intel/edison/Kconfig\"\ndiff --git a/board/intel/cherryhill/Kconfig b/board/intel/cherryhill/Kconfig\nnew file mode 100644\nindex 0000000..a4fa004\n--- /dev/null\n+++ b/board/intel/cherryhill/Kconfig\n@@ -0,0 +1,25 @@\n+if TARGET_CHERRYHILL\n+\n+config SYS_BOARD\n+\tdefault \"cherryhill\"\n+\n+config SYS_VENDOR\n+\tdefault \"intel\"\n+\n+config SYS_SOC\n+\tdefault \"braswell\"\n+\n+config SYS_CONFIG_NAME\n+\tdefault \"cherryhill\"\n+\n+config SYS_TEXT_BASE\n+\tdefault 0xffe00000\n+\n+config BOARD_SPECIFIC_OPTIONS # dummy\n+\tdef_bool y\n+\tselect X86_RESET_VECTOR\n+\tselect INTEL_BRASWELL\n+\tselect BOARD_ROMSIZE_KB_8192\n+\tselect SPI_FLASH_MACRONIX\n+\n+endif\ndiff --git a/board/intel/cherryhill/MAINTAINERS b/board/intel/cherryhill/MAINTAINERS\nnew file mode 100644\nindex 0000000..6e90f64\n--- /dev/null\n+++ b/board/intel/cherryhill/MAINTAINERS\n@@ -0,0 +1,6 @@\n+INTEL CHERRYHILL BOARD\n+M:\tBin Meng <bmeng.cn@gmail.com>\n+S:\tMaintained\n+F:\tboard/intel/cherryhill/\n+F:\tinclude/configs/cherryhill.h\n+F:\tconfigs/cherryhill_defconfig\ndiff --git a/board/intel/cherryhill/Makefile b/board/intel/cherryhill/Makefile\nnew file mode 100644\nindex 0000000..0dbb055\n--- /dev/null\n+++ b/board/intel/cherryhill/Makefile\n@@ -0,0 +1,7 @@\n+#\n+# Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+#\n+# SPDX-License-Identifier:\tGPL-2.0+\n+#\n+\n+obj-y\t+= cherryhill.o start.o\ndiff --git a/board/intel/cherryhill/cherryhill.c b/board/intel/cherryhill/cherryhill.c\nnew file mode 100644\nindex 0000000..d86dc97\n--- /dev/null\n+++ b/board/intel/cherryhill/cherryhill.c\n@@ -0,0 +1,596 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#include <common.h>\n+#include <asm/arch/gpio.h>\n+#include <asm/fsp/fsp_support.h>\n+\n+static const struct gpio_family gpio_family[] = {\n+\tGPIO_FAMILY_CONF(\"SOUTHEAST_2_hshvfamily_2x3_rcomp_7_0\", NA, 0,\n+\t\t\t VOLT_1_8, NA, NA, NA, 0, ENABLE, 2, SOUTHEAST),\n+\n+\t/* end of the table */\n+\tGPIO_FAMILY_CONF(\"GPIO FAMILY TABLE END\", NA, 0,\n+\t\t\t VOLT_1_8, NA, NA, NA, 0, DISABLE, 0, TERMINATOR),\n+};\n+\n+static const struct gpio_pad gpio_pad[] = {\n+\tGPIO_PAD_CONF(\"N37: CX_PRDY_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 29, NA, 0x4c38, NORTH),\n+\tGPIO_PAD_CONF(\"N35: CX_PRDY_B_2\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 27, NA, 0x4c28, NORTH),\n+\tGPIO_PAD_CONF(\"N39: CX_PREQ_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 20, NA, 0x4858, NORTH),\n+\tGPIO_PAD_CONF(\"N48: GP_CAMERASB00\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 37, NA, 0x5018, NORTH),\n+\tGPIO_PAD_CONF(\"N53: GP_CAMERASB01\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 42, NA, 0x5040, NORTH),\n+\tGPIO_PAD_CONF(\"N46: GP_CAMERASB02\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 35, NA, 0x5008, NORTH),\n+\tGPIO_PAD_CONF(\"N51: GP_CAMERASB03\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 40, NA, 0x5030, NORTH),\n+\tGPIO_PAD_CONF(\"N56: GP_CAMERASB04\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 45, NA, 0x5058, NORTH),\n+\tGPIO_PAD_CONF(\"N45: GP_CAMERASB05\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 34, NA, 0x5000, NORTH),\n+\tGPIO_PAD_CONF(\"N49: GP_CAMERASB06\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 38, NA, 0x5020, NORTH),\n+\tGPIO_PAD_CONF(\"N54: GP_CAMERASB07\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 43, NA, 0x5048, NORTH),\n+\tGPIO_PAD_CONF(\"N47: GP_CAMERASB08\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 36, NA, 0x5010, NORTH),\n+\tGPIO_PAD_CONF(\"N52: GP_CAMERASB09\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 41, NA, 0x5038, NORTH),\n+\tGPIO_PAD_CONF(\"N50: GP_CAMERASB10\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 39, NA, 0x5028, NORTH),\n+\tGPIO_PAD_CONF(\"N55: GP_CAMERASB11\", GPIO, M1, GPO, LOW,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 44, NA, 0x5050, NORTH),\n+\tGPIO_PAD_CONF(\"N00: GPIO_DFX0\", NATIVE, M5, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 0, NA, 0x4400, NORTH),\n+\tGPIO_PAD_CONF(\"N03: GPIO_DFX1\", NATIVE, M5, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 3, NA, 0x4418, NORTH),\n+\tGPIO_PAD_CONF(\"N07: GPIO_DFX2\", NATIVE, M5, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 2, NA, 0x4438, NORTH),\n+\tGPIO_PAD_CONF(\"N01: GPIO_DFX3\", NATIVE, M5, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,\n+\t\t NA, 1, NA, 0x4408, NORTH),\n+\tGPIO_PAD_CONF(\"N05: GPIO_DFX4\", GPIO, M1, GPO, HIGH, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 5, NA, 0x4428, NORTH),\n+\tGPIO_PAD_CONF(\"N04: GPIO_DFX5\", GPIO, M1, GPO, HIGH, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 4, NA, 0x4420, NORTH),\n+\tGPIO_PAD_CONF(\"N08: GPIO_DFX6\", NATIVE, M8, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 8, NA, 0x4440, NORTH),\n+\tGPIO_PAD_CONF(\"N02: GPIO_DFX7\", GPIO, M1, GPO, LOW, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 2, NA, 0x4410, NORTH),\n+\tGPIO_PAD_CONF(\"N15: GPIO_SUS0\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 9 , NA, 0x4800, NORTH),\n+\tGPIO_PAD_CONF(\"N19: GPIO_SUS1\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 13, NA, 0x4820, NORTH),\n+\tGPIO_PAD_CONF(\"N24: GPIO_SUS2\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 18, NA, 0x4848, NORTH),\n+\tGPIO_PAD_CONF(\"N17: GPIO_SUS3\", NATIVE, M6, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 11, NA, 0x4810, NORTH),\n+\tGPIO_PAD_CONF(\"N22: GPIO_SUS4\", GPIO, M1, GPO, HIGH, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 16, NA, 0x4838, NORTH),\n+\tGPIO_PAD_CONF(\"N20: GPIO_SUS5\", GPIO, M1, GPO, HIGH, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 14, NA, 0x4828, NORTH),\n+\tGPIO_PAD_CONF(\"N25: GPIO_SUS6\", GPIO, M1, GPI, NA, NA,\n+\t\t TRIG_EDGE_LOW, L9, NA, NA, NA, NON_MASKABLE,\n+\t\t EN_EDGE_RX_DATA, NO_INVERSION,\n+\t\t NA, 19, SCI, 0x4850, NORTH),\n+\tGPIO_PAD_CONF(\"N18: GPIO_SUS7\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 12, SMI, 0x4818, NORTH),\n+\tGPIO_PAD_CONF(\"N71: HV_DDI0_DDC_SCL\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 57, NA, 0x5458, NORTH),\n+\tGPIO_PAD_CONF(\"N66: HV_DDI0_DDC_SDA\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 52, NA, 0x5430, NORTH),\n+\tGPIO_PAD_CONF(\"N61: HV_DDI0_HPD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,\n+\t\t NA, 47, NA, 0x5408, NORTH),\n+\tGPIO_PAD_CONF(\"N64: HV_DDI1_HPD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,\n+\t\t NA, 50, NA, 0x5420, NORTH),\n+\tGPIO_PAD_CONF(\"N67: HV_DDI2_DDC_SCL\", NATIVE, M3, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 53, NA, 0x5438, NORTH),\n+\tGPIO_PAD_CONF(\"N62: HV_DDI2_DDC_SDA\", NATIVE, M3, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 48, NA, 0x5410, NORTH),\n+\tGPIO_PAD_CONF(\"N68: HV_DDI2_HPD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,\n+\t\t NA, 54, NA, 0x5440, NORTH),\n+\tGPIO_PAD_CONF(\"N65: PANEL0_BKLTCTL\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 51, NA, 0x5428, NORTH),\n+\tGPIO_PAD_CONF(\"N60: PANEL0_BKLTEN\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 46, NA, 0x5400, NORTH),\n+\tGPIO_PAD_CONF(\"N72: PANEL0_VDDEN\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 58, NA, 0x5460, NORTH),\n+\tGPIO_PAD_CONF(\"N63: PANEL1_BKLTCTL\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 49, NA, 0x5418, NORTH),\n+\tGPIO_PAD_CONF(\"N70: PANEL1_BKLTEN\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 56, NA, 0x5450, NORTH),\n+\tGPIO_PAD_CONF(\"N69: PANEL1_VDDEN\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 55, NA, 0x5448, NORTH),\n+\tGPIO_PAD_CONF(\"N32: PROCHOT_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 24, NA, 0x4c10, NORTH),\n+\tGPIO_PAD_CONF(\"N16: SEC_GPIO_SUS10\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 10, NA, 0x4808, NORTH),\n+\tGPIO_PAD_CONF(\"N21: SEC_GPIO_SUS11\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 15, NA, 0x4830, NORTH),\n+\tGPIO_PAD_CONF(\"N23: SEC_GPIO_SUS8\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 17, NA, 0x4840, NORTH),\n+\tGPIO_PAD_CONF(\"N27: SEC_GPIO_SUS9\", GPIO, M1, GPI, LOW, NA,\n+\t\t TRIG_LEVEL, L15, NA, NA, NA, NON_MASKABLE,\n+\t\t EN_RX_DATA, INV_RX_DATA,\n+\t\t NA, 21, SCI, 0x4860, NORTH),\n+\tGPIO_PAD_CONF(\"N31: TCK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 23, NA, 0x4c08, NORTH),\n+\tGPIO_PAD_CONF(\"N41: TDI\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 33, NA, 0x4c58, NORTH),\n+\tGPIO_PAD_CONF(\"N39: TDO\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 31, NA, 0x4c48, NORTH),\n+\tGPIO_PAD_CONF(\"N36: TDO_2\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 28, NA, 0x4c30, NORTH),\n+\tGPIO_PAD_CONF(\"N34: TMS\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 26, NA, 0x4c20, NORTH),\n+\tGPIO_PAD_CONF(\"N30: TRST_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 22, NA, 0x4c00, NORTH),\n+\n+\tGPIO_PAD_CONF(\"E21: MF_ISH_GPIO_0\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 18, NA, 0x4830, EAST),\n+\tGPIO_PAD_CONF(\"E18: MF_ISH_GPIO_1\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 15, NA, 0x4818, EAST),\n+\tGPIO_PAD_CONF(\"E24: MF_ISH_GPIO_2\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 21, NA, 0x4848, EAST),\n+\tGPIO_PAD_CONF(\"E15: MF_ISH_GPIO_3\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 12, NA, 0x4800, EAST),\n+\tGPIO_PAD_CONF(\"E22: MF_ISH_GPIO_4\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, L0, NA, NA, NA, NON_MASKABLE, NA, NO_INVERSION,\n+\t\t NA, 19, NA, 0x4838, EAST),\n+\tGPIO_PAD_CONF(\"E19: MF_ISH_GPIO_5\", GPIO, M1, GPO, HIGH, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 16, NA, 0x4820, EAST),\n+\tGPIO_PAD_CONF(\"E25: MF_ISH_GPIO_6\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 22, NA, 0x4850, EAST),\n+\tGPIO_PAD_CONF(\"E16: MF_ISH_GPIO_7\", GPIO, M1, GPO, HIGH, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 13, NA, 0x4808, EAST),\n+\tGPIO_PAD_CONF(\"E23: MF_ISH_GPIO_8\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 20, NA, 0x4840, EAST),\n+\tGPIO_PAD_CONF(\"E20: MF_ISH_GPIO_9\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 17, NA, 0x4828, EAST),\n+\tGPIO_PAD_CONF(\"E26: MF_ISH_I2C1_SDA\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 23, NA, 0x4858, EAST),\n+\tGPIO_PAD_CONF(\"E17: MF_ISH_I2C1_SCL\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 14, NA, 0x4810, EAST),\n+\tGPIO_PAD_CONF(\"E04: PMU_AC_PRESENT\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 4, NA, 0x4420, EAST),\n+\tGPIO_PAD_CONF(\"E01: PMU_BATLOW_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 1, NA, 0x4408, EAST),\n+\tGPIO_PAD_CONF(\"E05: PMU_PLTRST_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 5, NA, 0x4428, EAST),\n+\tGPIO_PAD_CONF(\"E07: PMU_SLP_LAN_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 7, NA, 0x4438, EAST),\n+\tGPIO_PAD_CONF(\"E03: PMU_SLP_S0IX_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 3, NA, 0x4418, EAST),\n+\tGPIO_PAD_CONF(\"E00: PMU_SLP_S3_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 0, NA, 0x4400, EAST),\n+\tGPIO_PAD_CONF(\"E09: PMU_SLP_S4_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 9, NA, 0x4448, EAST),\n+\tGPIO_PAD_CONF(\"E06: PMU_SUSCLK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 6, NA, 0x4430, EAST),\n+\tGPIO_PAD_CONF(\"E10: PMU_WAKE_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 10, NA, 0x4450, EAST),\n+\tGPIO_PAD_CONF(\"E11: PMU_WAKE_LAN_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 11, NA, 0x4458, EAST),\n+\tGPIO_PAD_CONF(\"E02: SUS_STAT_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 2, NA, 0x4410, EAST),\n+\n+\tGPIO_PAD_CONF(\"SE16: SDMMC1_CLK\", NATIVE, M1, NA, NA, HIGH,\n+\t\t NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 9, NA, 0x4808, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE23: SDMMC1_CMD\", NATIVE, M1, NA, NA, HIGH,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 16, NA, 0x4840, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE17: SDMMC1_D0\", NATIVE, M1, NA, NA, HIGH,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 10, NA, 0x4810, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE24: SDMMC1_D1\", NATIVE, M1, NA, NA, HIGH,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 17, NA, 0x4848, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE20: SDMMC1_D2\", NATIVE, M1, NA, NA, HIGH,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 13, NA, 0x4828, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE26: SDMMC1_D3_CD_B\", NATIVE, M1, NA, NA, HIGH,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 19, NA, 0x4858, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE67: MMC1_D4_SD_WE\", NATIVE, M1, NA, NA, HIGH,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 41, NA, 0x5438, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE65: MMC1_D5\", NATIVE, M1, NA, NA, HIGH,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 39, NA, 0x5428, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE63: MMC1_D6\", NATIVE, M1, NA, NA, HIGH,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 37, NA, 0x5418, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE68: MMC1_D7\", NATIVE, M1, NA, NA, HIGH,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 42, NA, 0x5440, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE69: MMC1_RCLK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 43, NA, 0x5448, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE77: GPIO_ALERT\", GPIO, M1, GPI, NA, NA,\n+\t\t TRIG_LEVEL, L2, NA, NA, NA, NON_MASKABLE,\n+\t\t EN_RX_DATA, INV_RX_DATA,\n+\t\t NA, 46, NA, 0x5810, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE79: ILB_SERIRQ\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 48, NA, 0x5820, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE51: MF_LPC_CLKOUT0\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 32, NA, 0x5030, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE49: MF_LPC_CLKOUT1\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 30, NA, 0x5020, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE47: MF_LPC_AD0\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 28, NA, 0x5010, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE52: MF_LPC_AD1\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 33, NA, 0x5038, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE45: MF_LPC_AD2\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 26, NA, 0x5000, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE50: MF_LPC_AD3\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 31, NA, 0x5028, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE46: LPC_CLKRUNB\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 27, NA, 0x5008, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE48: LPC_FRAMEB\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 29, NA, 0x5018, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE00: MF_PLT_CLK0\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 0, NA, 0x4400, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE02: MF_PLT_CLK1\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 1, NA, 0x4410, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE07: MF_PLT_CLK2\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 7, NA, 0x4438, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE04: MF_PLT_CLK3\", GPIO, M1, GPI, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 4, NA, 0x4420, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE03: MF_PLT_CLK4\", GPIO, M1, GPO, LOW, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 3, NA, 0x4418, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE06: MF_PLT_CLK5\", GPIO, M3, GPO, LOW, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 6, NA, 0x4430, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE83: SUSPWRDNACK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 52, NA, 0x5840, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE05: PWM0\", GPIO, M1, GPO, LOW, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 5, NA, 0x4428, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE01: PWM1\", GPIO, M1, GPO, HIGH, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 1, NA, 0x4408, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE85: SDMMC3_1P8_EN\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 54, NA, 0x5850, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE81: SDMMC3_CD_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 50, NA, 0x5830, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE31: SDMMC3_CLK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 21, NA, 0x4c08, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE34: SDMMC3_CMD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 24, NA, 0x4c20, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE35: SDMMC3_D0\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 25, NA, 0x4c28, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE30: SDMMC3_D1\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 20, NA, 0x4c00, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE33: SDMMC3_D2\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 23, NA, 0x4c18, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE32: SDMMC3_D3\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 22, NA, 0x4c10, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE78: SDMMC3_PWR_EN_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_L, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 47, NA, 0x5818, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE19: SDMMC2_CLK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 12, NA, 0x4820, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE22: SDMMC2_CMD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 15, NA, 0x4838, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE25: SDMMC2_D0\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 18, NA, 0x4850, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE18: SDMMC2_D1\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 11, NA, 0x4818, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE21: SDMMC2_D2\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 14, NA, 0x4830, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE15: SDMMC2_D3_CD_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 8, NA, 0x4800, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE62: SPI1_CLK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 36, NA, 0x5410, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE61: SPI1_CS0_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 35, NA, 0x5408, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE66: SPI1_CS1_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 40, NA, 0x5430, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE60: SPI1_MISO\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 34, NA, 0x5400, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE64: SPI1_MOSI\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 38, NA, 0x5420, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE80: USB_OC0_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 49, NA, 0x5828, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SE75: USB_OC1_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 44, NA, 0x5800, SOUTHEAST),\n+\tGPIO_PAD_CONF(\"SW02: FST_SPI_CLK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 2, NA, 0x4410, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW06: FST_SPI_CS0_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 6, NA, 0x4430, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW04: FST_SPI_CS1_B\", GPIO, M1, GPO, HIGH, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 4, NA, 0x4420, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW07: FST_SPI_CS2_B\", GPIO, M1, GPO, LOW, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 7, NA, 0x4438, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW01: FST_SPI_D0\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 1, NA, 0x4408, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW05: FST_SPI_D1\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 5, NA, 0x4428, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW00: FST_SPI_D2\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 0, NA, 0x4400, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW03: FST_SPI_D3\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 3, NA, 0x4418, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW30: MF_HDA_CLK\", NATIVE, M2, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 16, NA, 0x4c00, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW37: MF_HDA_DOCKENB\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 23, NA, 0x4c38, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW34: MF_HDA_DOCKRSTB\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 20, NA, 0x4c20, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW31: MF_HDA_RSTB\", NATIVE, M2, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 17, NA, 0x4c08, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW32: MF_HDA_SDI0\", NATIVE, M2, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 18, NA, 0x4c10, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW36: MF_HDA_SDI1\", NATIVE, M2, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 22, NA, 0x4c30, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW33: MF_HDA_SDO\", NATIVE, M2, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 19, NA, 0x4c18, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW35: MF_HDA_SYNC\", NATIVE, M2, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 21, NA, 0x4c28, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW18: UART1_CTS_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 11, NA, 0x4818, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW15: UART1_RTS_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 8, NA, 0x4800, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW16: UART1_RXD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 9, NA, 0x4808, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW20: UART1_TXD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 13, NA, 0x4828, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW22: UART2_CTS_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 15, NA, 0x4838, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW19: UART2_RTS_B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 12, NA, 0x4820, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW17: UART2_RXD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_NONE, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 10, NA, 0x4810, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW21: UART2_TXD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 14, NA, 0x4830, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW50: I2C4_SCL\", NATIVE, M3, NA, NA, NA,\n+\t\t NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 29, NA, 0x5028, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW46: I2C4_SDA\", NATIVE, M3, NA, NA, NA,\n+\t\t NA, NA, P_1K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 25, NA, 0x5008, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW49: I2C_NFC_SDA\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,\n+\t\t NA, 28, NA, 0x5020, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW52: I2C_NFC_SCL\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, INV_TX_ENABLE,\n+\t\t NA, 31, NA, 0x5038, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW77: GP_SSP_2_CLK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 50, NA, 0x5c10, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW81: GP_SSP_2_FS\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 54, NA, 0x5c30, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW79: GP_SSP_2_RXD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 52, NA, 0x5c20, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW82: GP_SSP_2_TXD\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, INV_TX_ENABLE,\n+\t\t NA, 55, NA, 0x5C38, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW90: PCIE_CLKREQ0B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 48, NA, 0x5c00, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW91: PCIE_CLKREQ1B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 49, NA, 0x5c08, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW93: PCIE_CLKREQ2B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 51, NA, 0x5c18, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW95: PCIE_CLKREQ3B\", NATIVE, M2, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 53, NA, 0x5c28, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW75: SATA_GP0\", GPIO, M1, GPO, HIGH, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 40, NA, 0x5800, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW76: SATA_GP1\", GPIO, M1, GPI, HIGH, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 41, NA, 0x5808, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW78: SATA_GP2\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 43, NA, 0x5818, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW80: SATA_GP3\", GPIO, M2, GPI, LOW, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 45, NA, 0x5828, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW77: SATA_LEDN\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, ENABLE, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 42, NA, 0x5810, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW79: MF_SMB_ALERTB\", NATIVE, M1, NA, NA,\n+\t\t NA, NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 44, NA, 0x5820, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW81: MF_SMB_CLK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 46, NA, 0x5830, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW82: MF_SMB_DATA\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 47, NA, 0x5838, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW90: PCIE_CLKREQ0B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA,\n+\t\t NA, 48, NA, 0x5c00, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW91: PCIE_CLKREQ1B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA,\n+\t\t NA, 49, NA, 0x5c08, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW93: PCIE_CLKREQ2B\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA,\n+\t\t NA, 51, NA, 0x5c18, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW95: PCIE_CLKREQ3B\", NATIVE, M2, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA,\n+\t\t NA, 53, NA, 0x5c28, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW75: SATA_GP0\", GPIO, M1, GPO, HIGH, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA,\n+\t\t NA, 40, NA, 0x5800, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW76: SATA_GP1\", GPIO, M1, GPI, HIGH, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA,\n+\t\t NA, 41, NA, 0x5808, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW78: SATA_GP2\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, ENABLE, NA, NA, NA, NA,\n+\t\t NA, 43, NA, 0x5818, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW80: SATA_GP3\", GPIO, M2, GPI, LOW, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NA,\n+\t\t NA, 45, NA, 0x5828, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW77: SATA_LEDN\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, ENABLE, NA, NA, NA, NA,\n+\t\t NA, 42, NA, 0x5810, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW79: MF_SMB_ALERTB\", NATIVE, M1, NA, NA,\n+\t\t NA, NA, NA, P_20K_H, NA, NA, NA, NA, NA,\n+\t\t NA, 44, NA, 0x5820, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW81: MF_SMB_CLK\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NA,\n+\t\t NA, 46, NA, 0x5830, SOUTHWEST),\n+\tGPIO_PAD_CONF(\"SW82: MF_SMB_DATA\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, P_20K_H, NA, NA, NA, NA, NA,\n+\t\t NA, 47, NA, 0x5838, SOUTHWEST),\n+\n+\t/* end of the table */\n+\tGPIO_PAD_CONF(\"GPIO PAD TABLE END\", NATIVE, M1, NA, NA, NA,\n+\t\t NA, NA, NA, NA, NA, NA, NA, NO_INVERSION,\n+\t\t NA, 0, NA, 0, TERMINATOR),\n+};\n+\n+void update_fsp_gpio_configs(const struct gpio_family **family,\n+\t\t\t const struct gpio_pad **pad)\n+{\n+\t*family = gpio_family;\n+\t*pad = gpio_pad;\n+}\ndiff --git a/board/intel/cherryhill/start.S b/board/intel/cherryhill/start.S\nnew file mode 100644\nindex 0000000..11af9de\n--- /dev/null\n+++ b/board/intel/cherryhill/start.S\n@@ -0,0 +1,9 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+.globl early_board_init\n+early_board_init:\n+\tjmp\tearly_board_init_ret\ndiff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig\nnew file mode 100644\nindex 0000000..a2017ac\n--- /dev/null\n+++ b/configs/cherryhill_defconfig\n@@ -0,0 +1,36 @@\n+CONFIG_X86=y\n+CONFIG_VENDOR_INTEL=y\n+CONFIG_DEFAULT_DEVICE_TREE=\"cherryhill\"\n+CONFIG_TARGET_CHERRYHILL=y\n+CONFIG_DEBUG_UART=y\n+CONFIG_SMP=y\n+CONFIG_GENERATE_MP_TABLE=y\n+CONFIG_SYS_CONSOLE_INFO_QUIET=y\n+CONFIG_HUSH_PARSER=y\n+CONFIG_CMD_CPU=y\n+# CONFIG_CMD_IMLS is not set\n+# CONFIG_CMD_FLASH is not set\n+CONFIG_CMD_MMC=y\n+CONFIG_CMD_SF=y\n+CONFIG_CMD_SPI=y\n+CONFIG_CMD_USB=y\n+# CONFIG_CMD_SETEXPR is not set\n+CONFIG_CMD_DHCP=y\n+# CONFIG_CMD_NFS is not set\n+CONFIG_CMD_PING=y\n+CONFIG_CMD_TIME=y\n+CONFIG_CMD_EXT2=y\n+CONFIG_CMD_EXT4=y\n+CONFIG_CMD_EXT4_WRITE=y\n+CONFIG_CMD_FAT=y\n+CONFIG_CMD_FS_GENERIC=y\n+CONFIG_ISO_PARTITION=y\n+CONFIG_EFI_PARTITION=y\n+CONFIG_REGMAP=y\n+CONFIG_SYSCON=y\n+CONFIG_CPU=y\n+CONFIG_RTL8169=y\n+CONFIG_DEBUG_UART_BASE=0x3f8\n+CONFIG_DEBUG_UART_CLOCK=1843200\n+CONFIG_USB_STORAGE=y\n+CONFIG_USB_KEYBOARD=y\ndiff --git a/doc/README.x86 b/doc/README.x86\nindex c542a69..c96a22c 100644\n--- a/doc/README.x86\n+++ b/doc/README.x86\n@@ -26,6 +26,7 @@ In this case, known as bare mode, from the fact that it runs on the\n are supported:\n \n - Bayley Bay CRB\n+ - Cherry Hill CRB\n - Congatec QEVAL 2.0 & conga-QA3/E3845\n - Cougar Canyon 2 CRB\n - Crown Bay CRB\n@@ -332,6 +333,35 @@ the default value 0xfffc0000.\n \n ---\n \n+Intel Cherry Hill specific instructions for bare mode:\n+\n+This uses Intel FSP for Braswell platform. Download it from Intel FSP website,\n+put the .fd file to the board directory and rename it to fsp.bin.\n+\n+Extract descriptor.bin and me.bin from the original BIOS on the board using\n+ifdtool and put them to the board directory as well.\n+\n+Note the FSP package for Braswell does not ship a traditional legacy VGA BIOS\n+image for the integrated graphics device. Instead a new binary called Video\n+BIOS Table (VBT) is shipped. Put it to the board directory and rename it to\n+vbt.bin if you want graphics support in U-Boot.\n+\n+Now you can build U-Boot and obtain u-boot.rom\n+\n+$ make cherryhill_defconfig\n+$ make all\n+\n+An important note for programming u-boot.rom to the on-board SPI flash is that\n+you need make sure the SPI flash's 'quad enable' bit in its status register\n+matches the settings in the descriptor.bin, otherwise the board won't boot.\n+\n+For the on-board SPI flash MX25U6435F, this can be done by writing 0x40 to the\n+status register by DediProg in: Config > Modify Status Register > Write Status\n+Register(s) > Register1 Value(Hex). This is is a one-time change. Once set, it\n+persists in SPI flash part regardless of the u-boot.rom image burned.\n+\n+---\n+\n Intel Galileo instructions for bare mode:\n \n Only one binary blob is needed for Remote Management Unit (RMU) within Intel\ndiff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h\nnew file mode 100644\nindex 0000000..14da9ca\n--- /dev/null\n+++ b/include/configs/cherryhill.h\n@@ -0,0 +1,22 @@\n+/*\n+ * Copyright (C) 2017, Bin Meng <bmeng.cn@gmail.com>\n+ *\n+ * SPDX-License-Identifier:\tGPL-2.0+\n+ */\n+\n+#ifndef __CONFIG_H\n+#define __CONFIG_H\n+\n+#include <configs/x86-common.h>\n+\n+#define CONFIG_SYS_MONITOR_LEN\t\t(2 << 20)\n+\n+#define CONFIG_STD_DEVICES_SETTINGS\t\"stdin=usbkbd,serial\\0\" \\\n+\t\t\t\t\t\"stdout=vidconsole,serial\\0\" \\\n+\t\t\t\t\t\"stderr=vidconsole,serial\\0\"\n+\n+/* Environment configuration */\n+#define CONFIG_ENV_SECT_SIZE\t\t0x10000\n+#define CONFIG_ENV_OFFSET\t\t0x005f0000\n+\n+#endif\t/* __CONFIG_H */\n", "prefixes": [ "U-Boot", "13/13" ] }