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GET /api/1.2/patches/2235146/?format=api
{ "id": 2235146, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235146/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508162013.2751001-3-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508162013.2751001-3-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-05-08T16:20:11", "name": "[2/4] hw/arm/integratorcp: Use LOG_UNIMP rather than hw_error()", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "3559b8c5d1e9f214d8ce9e88f6dafeb6019299a5", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.2/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508162013.2751001-3-peter.maydell@linaro.org/mbox/", "series": [ { "id": 503418, "url": "http://patchwork.ozlabs.org/api/1.2/series/503418/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503418", "date": "2026-05-08T16:20:09", "name": "hw: Fix some minor arm buglets", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503418/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235146/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235146/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=Vt9FRWif;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBvWW74PYz1yCg\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 09 May 2026 02:21:27 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wLNw7-0001Mc-Np; Fri, 08 May 2026 12:20:23 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wLNw6-0001Lh-Ix\n for qemu-devel@nongnu.org; Fri, 08 May 2026 12:20:22 -0400", "from mail-wr1-x434.google.com ([2a00:1450:4864:20::434])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wLNw4-0000xO-QG\n for qemu-devel@nongnu.org; Fri, 08 May 2026 12:20:22 -0400", "by mail-wr1-x434.google.com with SMTP id\n ffacd0b85a97d-43d7645adbdso1299855f8f.1\n for <qemu-devel@nongnu.org>; Fri, 08 May 2026 09:20:20 -0700 (PDT)", "from lanath.. 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We've never\nimplemented this obscure bit of functionality, and instead call\nhw_error() if the guest does try to raise an interrupt this way.\n\nReplace the hw_error() call with the more modern way to note\nunimplemented QEMU behaviour, a LOG_UNIMP log.\n\nResolves: https://gitlab.com/qemu-project/qemu/-/work_items/3406\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/arm/integratorcp.c | 16 +++++++++++-----\n 1 file changed, 11 insertions(+), 5 deletions(-)", "diff": "diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c\nindex 164af03f7b..c25bbf3c82 100644\n--- a/hw/arm/integratorcp.c\n+++ b/hw/arm/integratorcp.c\n@@ -23,7 +23,6 @@\n #include \"qemu/log.h\"\n #include \"qemu/error-report.h\"\n #include \"hw/char/pl011.h\"\n-#include \"hw/core/hw-error.h\"\n #include \"hw/core/irq.h\"\n #include \"hw/sd/sd.h\"\n #include \"qom/object.h\"\n@@ -178,10 +177,17 @@ static void integratorcm_set_ctrl(IntegratorCMState *s, uint32_t value)\n \n static void integratorcm_update(IntegratorCMState *s)\n {\n- /* ??? The CPU irq/fiq is raised when either the core module or base PIC\n- are active. */\n- if (s->int_level & (s->irq_enabled | s->fiq_enabled))\n- hw_error(\"Core module interrupt\\n\");\n+ /*\n+ * ??? The CPU irq/fiq is raised when either the core module or base PIC\n+ * are active. To implement this we would need to run these signals\n+ * through an OR gate with the PIC outputs. In practice guests don't\n+ * use this, which is intended for an external debugger.\n+ */\n+ if (s->int_level & (s->irq_enabled | s->fiq_enabled)) {\n+ qemu_log_mask(LOG_UNIMP,\n+ \"%s: raising IRQ/FIQ via core module registers is not implemented\\n\",\n+ __func__);\n+ }\n }\n \n static void integratorcm_write(void *opaque, hwaddr offset,\n", "prefixes": [ "2/4" ] }