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GET /api/1.2/patches/2235144/?format=api
{ "id": 2235144, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235144/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508162013.2751001-5-peter.maydell@linaro.org/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508162013.2751001-5-peter.maydell@linaro.org>", "list_archive_url": null, "date": "2026-05-08T16:20:13", "name": "[4/4] hw/display/exynos4210_fimd: Assume display surface is 32bpp", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "96edf8c11eb7237edffd7a7f46b0ac18f899029c", "submitter": { "id": 5111, "url": "http://patchwork.ozlabs.org/api/1.2/people/5111/?format=api", "name": "Peter Maydell", "email": "peter.maydell@linaro.org" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508162013.2751001-5-peter.maydell@linaro.org/mbox/", "series": [ { "id": 503418, "url": "http://patchwork.ozlabs.org/api/1.2/series/503418/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503418", "date": "2026-05-08T16:20:09", "name": "hw: Fix some minor arm buglets", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503418/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235144/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235144/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=G3Pe80YZ;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBvVq5Nhyz1yKm\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 09 May 2026 02:20:50 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wLNwA-0001O2-JM; Fri, 08 May 2026 12:20:26 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wLNw7-0001MY-I4\n for qemu-devel@nongnu.org; Fri, 08 May 2026 12:20:23 -0400", "from mail-wr1-x432.google.com ([2a00:1450:4864:20::432])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <peter.maydell@linaro.org>)\n id 1wLNw5-0000y1-NA\n for qemu-devel@nongnu.org; Fri, 08 May 2026 12:20:23 -0400", "by mail-wr1-x432.google.com with SMTP id\n ffacd0b85a97d-449d6c68ed8so1797659f8f.0\n for <qemu-devel@nongnu.org>; Fri, 08 May 2026 09:20:21 -0700 (PDT)", "from lanath.. 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This old display device still has code\nassuming it might be something else. Remove the code that made\nput_pixel_toqemu a function pointer indirection, and use\nput_to_qemufb_pixel32() directly.\n\nThis removes the last hw_error() in this file.\n\nSigned-off-by: Peter Maydell <peter.maydell@linaro.org>\n---\n hw/display/exynos4210_fimd.c | 62 ++----------------------------------\n 1 file changed, 2 insertions(+), 60 deletions(-)", "diff": "diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c\nindex 0c9e42ec52..daed85e22c 100644\n--- a/hw/display/exynos4210_fimd.c\n+++ b/hw/display/exynos4210_fimd.c\n@@ -24,7 +24,6 @@\n \n #include \"qemu/osdep.h\"\n #include \"hw/core/qdev-properties.h\"\n-#include \"hw/core/hw-error.h\"\n #include \"hw/core/irq.h\"\n #include \"hw/core/sysbus.h\"\n #include \"exec/cpu-common.h\"\n@@ -867,37 +866,6 @@ static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src,\n }\n \n /* Write RGB to QEMU's GraphicConsole framebuffer */\n-\n-static int put_to_qemufb_pixel8(const rgba p, uint8_t *d)\n-{\n- uint32_t pixel = rgb_to_pixel8(p.r, p.g, p.b);\n- *(uint8_t *)d = pixel;\n- return 1;\n-}\n-\n-static int put_to_qemufb_pixel15(const rgba p, uint8_t *d)\n-{\n- uint32_t pixel = rgb_to_pixel15(p.r, p.g, p.b);\n- *(uint16_t *)d = pixel;\n- return 2;\n-}\n-\n-static int put_to_qemufb_pixel16(const rgba p, uint8_t *d)\n-{\n- uint32_t pixel = rgb_to_pixel16(p.r, p.g, p.b);\n- *(uint16_t *)d = pixel;\n- return 2;\n-}\n-\n-static int put_to_qemufb_pixel24(const rgba p, uint8_t *d)\n-{\n- uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);\n- *(uint8_t *)d++ = (pixel >> 0) & 0xFF;\n- *(uint8_t *)d++ = (pixel >> 8) & 0xFF;\n- *(uint8_t *)d++ = (pixel >> 16) & 0xFF;\n- return 3;\n-}\n-\n static int put_to_qemufb_pixel32(const rgba p, uint8_t *d)\n {\n uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);\n@@ -905,32 +873,6 @@ static int put_to_qemufb_pixel32(const rgba p, uint8_t *d)\n return 4;\n }\n \n-/* Routine to copy pixel from internal buffer to QEMU buffer */\n-static int (*put_pixel_toqemu)(const rgba p, uint8_t *pixel);\n-static inline void fimd_update_putpix_qemu(int bpp)\n-{\n- switch (bpp) {\n- case 8:\n- put_pixel_toqemu = put_to_qemufb_pixel8;\n- break;\n- case 15:\n- put_pixel_toqemu = put_to_qemufb_pixel15;\n- break;\n- case 16:\n- put_pixel_toqemu = put_to_qemufb_pixel16;\n- break;\n- case 24:\n- put_pixel_toqemu = put_to_qemufb_pixel24;\n- break;\n- case 32:\n- put_pixel_toqemu = put_to_qemufb_pixel32;\n- break;\n- default:\n- hw_error(\"exynos4210.fimd: unsupported BPP (%d)\", bpp);\n- break;\n- }\n-}\n-\n /* Routine to copy a line from internal frame buffer to QEMU display */\n static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst)\n {\n@@ -938,7 +880,7 @@ static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst)\n \n do {\n src += get_pixel_ifb(src, &p);\n- dst += put_pixel_toqemu(p, dst);\n+ dst += put_to_qemufb_pixel32(p, dst);\n } while (--width);\n }\n \n@@ -1336,7 +1278,7 @@ static bool exynos4210_fimd_update(void *opaque)\n int bpp;\n \n bpp = surface_bits_per_pixel(surface);\n- fimd_update_putpix_qemu(bpp);\n+ assert(bpp == 32);\n bpp = (bpp + 1) >> 3;\n d = surface_data(surface);\n for (line = first_line; line <= last_line; line++) {\n", "prefixes": [ "4/4" ] }