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GET /api/1.2/patches/2235090/?format=api
{ "id": 2235090, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2235090/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-5-bcbec96357d9@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508-mips-octeon-missing-insns-v2-v3-5-bcbec96357d9@gmail.com>", "list_archive_url": null, "date": "2026-05-08T15:12:05", "name": "[v3,05/32] target/mips: split Octeon SEQ/SNE decode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "edd45de2235cf1562e863e95b23fefb35899640e", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/1.2/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260508-mips-octeon-missing-insns-v2-v3-5-bcbec96357d9@gmail.com/mbox/", "series": [ { "id": 503407, "url": "http://patchwork.ozlabs.org/api/1.2/series/503407/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=503407", "date": "2026-05-08T15:12:00", "name": "target/mips: add missing Octeon user-mode support", "version": 3, "mbox": "http://patchwork.ozlabs.org/series/503407/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2235090/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2235090/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=UQ61OB4X;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)" ], "Received": [ "from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBt2D5ZQbz1yMB\n\tfor <incoming@patchwork.ozlabs.org>; Sat, 09 May 2026 01:14:28 +1000 (AEST)", "from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from <qemu-devel-bounces@nongnu.org>)\n\tid 1wLMtG-0002gW-L1; Fri, 08 May 2026 11:13:24 -0400", "from eggs.gnu.org ([2001:470:142:3::10])\n by lists1p.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wLMt1-0002c4-1g\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:08 -0400", "from mail-oa1-x2a.google.com ([2001:4860:4864:20::2a])\n by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128)\n (Exim 4.90_1) (envelope-from <james.hilliard1@gmail.com>)\n id 1wLMsz-0001cb-Ae\n for qemu-devel@nongnu.org; Fri, 08 May 2026 11:13:06 -0400", "by mail-oa1-x2a.google.com with SMTP id\n 586e51a60fabf-415b23dd6e5so918896fac.3\n for <qemu-devel@nongnu.org>; Fri, 08 May 2026 08:13:04 -0700 (PDT)", "from\n 1.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.0.ip6.arpa\n (71-218-113-237.hlrn.qwest.net. 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charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "\n <20260508-mips-octeon-missing-insns-v2-v3-5-bcbec96357d9@gmail.com>", "References": "\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>", "In-Reply-To": "\n <20260508-mips-octeon-missing-insns-v2-v3-0-bcbec96357d9@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Laurent Vivier <laurent@vivier.eu>, =?utf-8?q?Philippe_Mathieu-Daud?=\n\t=?utf-8?q?=C3=A9?= <philmd@linaro.org>,\n Aurelien Jarno <aurelien@aurel32.net>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Huacai Chen <chenhuacai@kernel.org>,\n James Hilliard <james.hilliard1@gmail.com>, Helge Deller <deller@gmx.de>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>,\n Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "Received-SPF": "pass client-ip=2001:4860:4864:20::2a;\n envelope-from=james.hilliard1@gmail.com; helo=mail-oa1-x2a.google.com", "X-Spam_score_int": "-17", "X-Spam_score": "-1.8", "X-Spam_bar": "-", "X-Spam_report": "(-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Decode the equality and inequality forms as explicit SEQ/SNE and\nSEQI/SNEI instructions rather than using shared generated SEQNE/SEQNEI\nentries.\n\nThe explicit decoder names match the architectural mnemonics, which makes\nthe translator entry points and trace/debug output easier to correlate\nwith the instruction set.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\nChanges v1 -> v2:\n - Split the SEQ/SNE decode cleanup out of the Octeon arithmetic\n instruction patch. (suggested by Philippe Mathieu-Daudé)\n\nChanges v2 -> v3:\n - Remove the decoded ne field now that the instructions are split.\n - Reuse @r3 for SEQ/SNE and pass the TCG condition into a shared\n translator helper. (suggested by Richard Henderson)\n---\n target/mips/tcg/octeon.decode | 7 +++--\n target/mips/tcg/octeon_translate.c | 52 ++++++++++++++++++++------------------\n 2 files changed, 32 insertions(+), 27 deletions(-)", "diff": "diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex 102a05860d..a2bfd0751d 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -30,6 +30,7 @@ BBIT 11 set:1 . 10 rs:5 ..... offset:s16 p=%bbit_p\n # SNEI rt, rs, immediate\n \n @r3 ...... rs:5 rt:5 rd:5 ..... ......\n+&cmpi rs rt imm\n %bitfield_p 0:1 6:5\n @bitfield ...... rs:5 rt:5 lenm1:5 ..... ..... . p=%bitfield_p\n \n@@ -38,8 +39,10 @@ DMUL 011100 ..... ..... ..... 00000 000011 @r3\n EXTS 011100 ..... ..... ..... ..... 11101 . @bitfield\n CINS 011100 ..... ..... ..... ..... 11001 . @bitfield\n POP 011100 rs:5 00000 rd:5 00000 10110 dw:1\n-SEQNE 011100 rs:5 rt:5 rd:5 00000 10101 ne:1\n-SEQNEI 011100 rs:5 rt:5 imm:s10 10111 ne:1\n+SEQ 011100 ..... ..... ..... 00000 101010 @r3\n+SNE 011100 ..... ..... ..... 00000 101011 @r3\n+SEQI 011100 rs:5 rt:5 imm:s10 101110 &cmpi\n+SNEI 011100 rs:5 rt:5 imm:s10 101111 &cmpi\n \n &lx base index rd\n @lx ...... base:5 index:5 rd:5 ...... ..... &lx\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex 4dd7626835..e69dd56c8e 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -121,52 +121,54 @@ static bool trans_POP(DisasContext *ctx, arg_POP *a)\n return true;\n }\n \n-static bool trans_SEQNE(DisasContext *ctx, arg_SEQNE *a)\n+static bool do_seqne(DisasContext *ctx, const arg_decode_ext_octeon1 *a,\n+ TCGCond cond)\n {\n TCGv_i64 t0, t1;\n \n- if (a->rd == 0) {\n- /* nop */\n- return true;\n- }\n-\n t0 = tcg_temp_new_i64();\n t1 = tcg_temp_new_i64();\n \n gen_load_gpr(t0, a->rs);\n gen_load_gpr(t1, a->rt);\n \n- if (a->ne) {\n- tcg_gen_setcond_i64(TCG_COND_NE, cpu_gpr[a->rd], t1, t0);\n- } else {\n- tcg_gen_setcond_i64(TCG_COND_EQ, cpu_gpr[a->rd], t1, t0);\n- }\n+ tcg_gen_setcond_i64(cond, t0, t1, t0);\n+ gen_store_gpr(t0, a->rd);\n return true;\n }\n \n-static bool trans_SEQNEI(DisasContext *ctx, arg_SEQNEI *a)\n+static bool trans_SEQ(DisasContext *ctx, arg_SEQ *a)\n {\n- TCGv_i64 t0;\n+ return do_seqne(ctx, a, TCG_COND_EQ);\n+}\n \n- if (a->rt == 0) {\n- /* nop */\n- return true;\n- }\n+static bool trans_SNE(DisasContext *ctx, arg_SNE *a)\n+{\n+ return do_seqne(ctx, a, TCG_COND_NE);\n+}\n \n- t0 = tcg_temp_new_i64();\n+static bool do_seqnei(DisasContext *ctx, const arg_cmpi *a, TCGCond cond)\n+{\n+ TCGv_i64 t0;\n \n+ t0 = tcg_temp_new_i64();\n gen_load_gpr(t0, a->rs);\n \n- /* Sign-extend to 64 bit value */\n- target_ulong imm = a->imm;\n- if (a->ne) {\n- tcg_gen_setcondi_i64(TCG_COND_NE, cpu_gpr[a->rt], t0, imm);\n- } else {\n- tcg_gen_setcondi_i64(TCG_COND_EQ, cpu_gpr[a->rt], t0, imm);\n- }\n+ tcg_gen_setcondi_i64(cond, t0, t0, a->imm);\n+ gen_store_gpr(t0, a->rt);\n return true;\n }\n \n+static bool trans_SEQI(DisasContext *ctx, arg_SEQI *a)\n+{\n+ return do_seqnei(ctx, a, TCG_COND_EQ);\n+}\n+\n+static bool trans_SNEI(DisasContext *ctx, arg_SNEI *a)\n+{\n+ return do_seqnei(ctx, a, TCG_COND_NE);\n+}\n+\n static bool trans_lx(DisasContext *ctx, arg_lx *a, MemOp mop)\n {\n gen_lx(ctx, a->rd, a->base, a->index, mop);\n", "prefixes": [ "v3", "05/32" ] }