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GET /api/1.2/patches/2234715/?format=api
{ "id": 2234715, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2234715/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508-hawi-pcie-v1-1-0c910906f7e5@oss.qualcomm.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260508-hawi-pcie-v1-1-0c910906f7e5@oss.qualcomm.com>", "list_archive_url": null, "date": "2026-05-08T01:02:14", "name": "[1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe Controller", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "7ee1238c32b664e9090736074cf153be01d76740", "submitter": { "id": 93362, "url": "http://patchwork.ozlabs.org/api/1.2/people/93362/?format=api", "name": "Matthew Leung", "email": "matthew.leung@oss.qualcomm.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260508-hawi-pcie-v1-1-0c910906f7e5@oss.qualcomm.com/mbox/", "series": [ { "id": 503303, "url": "http://patchwork.ozlabs.org/api/1.2/series/503303/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=503303", "date": "2026-05-08T01:02:13", "name": "PCI: qcom: Add PCIe support for upcoming Hawi SoC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/503303/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2234715/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2234715/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-54144-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=qualcomm.com header.i=@qualcomm.com header.a=rsa-sha256\n header.s=qcppdkim1 header.b=Dld8PACq;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.a=rsa-sha256 header.s=google header.b=ZvzKoQjh;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-54144-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)", "smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=qualcomm.com header.i=@qualcomm.com\n header.b=\"Dld8PACq\";\n\tdkim=pass (2048-bit key) header.d=oss.qualcomm.com header.i=@oss.qualcomm.com\n header.b=\"ZvzKoQjh\"", "smtp.subspace.kernel.org;\n arc=none smtp.client-ip=205.220.180.131", "smtp.subspace.kernel.org;\n dmarc=pass (p=reject dis=none) header.from=oss.qualcomm.com", "smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=oss.qualcomm.com" ], "Received": [ "from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBW7g0j7Jz1yCg\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 08 May 2026 11:02:55 +1000 (AEST)", "from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 952B930315F7\n\tfor <incoming@patchwork.ozlabs.org>; Fri, 8 May 2026 01:02:35 +0000 (UTC)", "from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 3E9BC225413;\n\tFri, 8 May 2026 01:02:34 +0000 (UTC)", "from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com\n [205.220.180.131])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BC981DFDA1\n\tfor <linux-pci@vger.kernel.org>; Fri, 8 May 2026 01:02:32 +0000 (UTC)", "from pps.filterd (m0279871.ppops.net [127.0.0.1])\n\tby mx0a-0031df01.pphosted.com (8.18.1.11/8.18.1.11) with ESMTP id\n 647MDuKQ1424462\n\tfor <linux-pci@vger.kernel.org>; Fri, 8 May 2026 01:02:31 GMT", "from mail-dy1-f199.google.com (mail-dy1-f199.google.com\n [74.125.82.199])\n\tby mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 4e0pqfup26-1\n\t(version=TLSv1.3 cipher=TLS_AES_128_GCM_SHA256 bits=128 verify=NOT)\n\tfor <linux-pci@vger.kernel.org>; Fri, 08 May 2026 01:02:31 +0000 (GMT)", "by mail-dy1-f199.google.com with SMTP id\n 5a478bee46e88-2c0f6593ef5so557368eec.1\n for <linux-pci@vger.kernel.org>; Thu, 07 May 2026 18:02:31 -0700 (PDT)", "from [169.254.0.3] (Global_NAT1.qualcomm.com. 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"From": "Matthew Leung <matthew.leung@oss.qualcomm.com>", "Date": "Fri, 08 May 2026 01:02:14 +0000", "Subject": "[PATCH 1/2] dt-bindings: PCI: qcom: Document the Hawi PCIe\n Controller", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Type": "text/plain; charset=\"utf-8\"", "Content-Transfer-Encoding": "7bit", "Message-Id": "<20260508-hawi-pcie-v1-1-0c910906f7e5@oss.qualcomm.com>", "References": "<20260508-hawi-pcie-v1-0-0c910906f7e5@oss.qualcomm.com>", "In-Reply-To": "<20260508-hawi-pcie-v1-0-0c910906f7e5@oss.qualcomm.com>", "To": "Bjorn Helgaas <bhelgaas@google.com>,\n Lorenzo Pieralisi <lpieralisi@kernel.org>, =?utf-8?q?Krzysztof_Wilczy=C5=84?=\n\t=?utf-8?q?ski?= <kwilczynski@kernel.org>,\n Manivannan Sadhasivam <mani@kernel.org>, Rob Herring <robh@kernel.org>,\n Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>,\n Bjorn Andersson <andersson@kernel.org>", "Cc": "linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,\n devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,\n Matthew Leung <matthew.leung@oss.qualcomm.com>", "X-Mailer": "b4 0.15.2", "X-Developer-Signature": "v=1; a=ed25519-sha256; t=1778202147; l=6962;\n i=matthew.leung@oss.qualcomm.com; s=20260428; h=from:subject:message-id;\n bh=iFwIHq7PnPhS1l/+UKbWINN7tuQP1Ai/kBITF6YukuA=;\n b=yUXMpaVvjIge5apBthE7ZOvm59w/9GnABJ9NbMQ+g15rusIJtakRlooKfuOI5euclxj666CQB\n HzbNp3zVaaCCtvJRqDaCDIV+KIGi8oTB8ahNDoPBGdwTKPdv8NNmhsP", "X-Developer-Key": "i=matthew.leung@oss.qualcomm.com; a=ed25519;\n pk=aT25ggJo5PMHLN9N+TsZ3s/BVU++kEYuiFebPWe21+o=", "X-Authority-Analysis": "v=2.4 cv=TJB1jVla c=1 sm=1 tr=0 ts=69fd3627 cx=c_pps\n a=cFYjgdjTJScbgFmBucgdfQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17\n a=IkcTkHD0fZMA:10 a=NGcC8JguVDcA:10 a=s4-Qcg_JpJYA:10\n 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engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.51,FMLib:17.12.100.49\n definitions=2026-05-07_02,2026-05-06_01,2025-10-01_01", "X-Proofpoint-Spam-Details": "rule=outbound_notspam policy=outbound score=0\n clxscore=1015 lowpriorityscore=0 malwarescore=0 impostorscore=0 bulkscore=0\n phishscore=0 priorityscore=1501 adultscore=0 spamscore=0 suspectscore=0\n classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0\n reason=mlx scancount=1 engine=8.22.0-2604200000 definitions=main-2605080007" }, "content": "Add a dedicated schema for the PCIe controllers found on the Hawi\nplatform.\n\nSigned-off-by: Matthew Leung <matthew.leung@oss.qualcomm.com>\n---\n .../devicetree/bindings/pci/qcom,hawi-pcie.yaml | 188 +++++++++++++++++++++\n 1 file changed, 188 insertions(+)", "diff": "diff --git a/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml\nnew file mode 100644\nindex 000000000000..154bc88e5969\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pci/qcom,hawi-pcie.yaml\n@@ -0,0 +1,188 @@\n+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pci/qcom,hawi-pcie.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: Qualcomm Hawi PCI Express Root Complex\n+\n+maintainers:\n+ - Bjorn Andersson <andersson@kernel.org>\n+ - Manivannan Sadhasivam <mani@kernel.org>\n+\n+description:\n+ Qualcomm Hawi SoC (and compatible) PCIe root complex controller is based on\n+ the Synopsys DesignWare PCIe IP.\n+\n+properties:\n+ compatible:\n+ const: qcom,hawi-pcie\n+\n+ reg:\n+ minItems: 5\n+ maxItems: 6\n+\n+ reg-names:\n+ minItems: 5\n+ items:\n+ - const: parf # Qualcomm specific registers\n+ - const: dbi # DesignWare PCIe registers\n+ - const: elbi # External local bus interface registers\n+ - const: atu # ATU address space\n+ - const: config # PCIe configuration space\n+ - const: mhi # MHI registers\n+\n+ clocks:\n+ maxItems: 7\n+\n+ clock-names:\n+ minItems: 6\n+ items:\n+ - const: aux # Auxiliary clock\n+ - const: cfg # Configuration clock\n+ - const: bus_master # Master AXI clock\n+ - const: bus_slave # Slave AXI clock\n+ - const: slave_q2a # Slave Q2A clock\n+ - const: noc_aggr # Aggre NoC PCIe AXI clock\n+ - const: cnoc_sf_axi # Config NoC PCIe0 AXI clock\n+\n+ interrupts:\n+ minItems: 8\n+ maxItems: 9\n+\n+ interrupt-names:\n+ minItems: 8\n+ items:\n+ - const: msi0\n+ - const: msi1\n+ - const: msi2\n+ - const: msi3\n+ - const: msi4\n+ - const: msi5\n+ - const: msi6\n+ - const: msi7\n+ - const: global\n+\n+ resets:\n+ minItems: 1\n+ maxItems: 2\n+\n+ reset-names:\n+ minItems: 1\n+ items:\n+ - const: pci # PCIe core reset\n+ - const: link_down # PCIe link down reset\n+\n+required:\n+ - power-domains\n+ - resets\n+ - reset-names\n+\n+allOf:\n+ - $ref: qcom,pcie-common.yaml#\n+\n+unevaluatedProperties: false\n+\n+examples:\n+ - |\n+ #include <dt-bindings/clock/qcom,hawi-gcc.h>\n+ #include <dt-bindings/gpio/gpio.h>\n+ #include <dt-bindings/interconnect/qcom,icc.h>\n+ #include <dt-bindings/interconnect/qcom,hawi-rpmh.h>\n+ #include <dt-bindings/interrupt-controller/arm-gic.h>\n+\n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pcie@1c00000 {\n+ compatible = \"qcom,hawi-pcie\";\n+ reg = <0 0x01c00000 0 0x3000>,\n+ <0 0x40000000 0 0xf1d>,\n+ <0 0x40000f20 0 0xa8>,\n+ <0 0x40001000 0 0x1000>,\n+ <0 0x40100000 0 0x100000>;\n+ reg-names = \"parf\", \"dbi\", \"elbi\", \"atu\", \"config\";\n+ ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>,\n+ <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x3d00000>;\n+\n+ bus-range = <0x00 0xff>;\n+ device_type = \"pci\";\n+ linux,pci-domain = <0>;\n+ num-lanes = <2>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+\n+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>,\n+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>,\n+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,\n+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>,\n+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,\n+ <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,\n+ <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>;\n+ clock-names = \"aux\",\n+ \"cfg\",\n+ \"bus_master\",\n+ \"bus_slave\",\n+ \"slave_q2a\",\n+ \"noc_aggr\",\n+ \"cnoc_sf_axi\";\n+\n+ dma-coherent;\n+\n+ interrupts = <GIC_ESPI 205 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_ESPI 206 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_ESPI 207 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_ESPI 208 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_ESPI 209 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_ESPI 210 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_ESPI 211 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_ESPI 212 IRQ_TYPE_LEVEL_HIGH>,\n+ <GIC_ESPI 204 IRQ_TYPE_LEVEL_HIGH>;\n+ interrupt-names = \"msi0\", \"msi1\", \"msi2\", \"msi3\",\n+ \"msi4\", \"msi5\", \"msi6\", \"msi7\", \"global\";\n+ #interrupt-cells = <1>;\n+ interrupt-map-mask = <0 0 0 0x7>;\n+ interrupt-map = <0 0 0 1 &intc 0 0 GIC_ESPI 213 IRQ_TYPE_LEVEL_HIGH>, /* int_a */\n+ <0 0 0 2 &intc 0 0 GIC_ESPI 214 IRQ_TYPE_LEVEL_HIGH>, /* int_b */\n+ <0 0 0 3 &intc 0 0 GIC_ESPI 215 IRQ_TYPE_LEVEL_HIGH>, /* int_c */\n+ <0 0 0 4 &intc 0 0 GIC_ESPI 216 IRQ_TYPE_LEVEL_HIGH>; /* int_d */\n+\n+ interconnects = <&pcie_anoc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS\n+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>,\n+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY\n+ &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>;\n+ interconnect-names = \"pcie-mem\", \"cpu-pcie\";\n+\n+ iommu-map = <0x0 &apps_smmu 0x1000 0x1>,\n+ <0x100 &apps_smmu 0x1001 0x1>;\n+\n+ pinctrl-0 = <&pcie0_default_state>;\n+ pinctrl-names = \"default\";\n+\n+ power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>;\n+\n+ resets = <&gcc GCC_PCIE_0_BCR>,\n+ <&gcc GCC_PCIE_0_LINK_DOWN_BCR>;\n+ reset-names = \"pci\", \"link_down\";\n+\n+ msi-map = <0x0 &gic_its 0x1000 0x1>,\n+ <0x100 &gic_its 0x1001 0x1>;\n+ msi-map-mask = <0xff00>;\n+\n+ pcie@0 {\n+ device_type = \"pci\";\n+ reg = <0x0 0x0 0x0 0x0 0x0>;\n+ bus-range = <0x01 0xff>;\n+\n+ #address-cells = <3>;\n+ #size-cells = <2>;\n+ ranges;\n+\n+ phys = <&pcie0_phy>;\n+ wake-gpios = <&tlmm 104 GPIO_ACTIVE_HIGH>;\n+ reset-gpios = <&tlmm 102 GPIO_ACTIVE_LOW>;\n+ };\n+ };\n+ };\n", "prefixes": [ "1/2" ] }