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GET /api/1.2/patches/2233130/?format=api
{ "id": 2233130, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2233130/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260505173029.2718246-11-terry.bowman@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260505173029.2718246-11-terry.bowman@amd.com>", "list_archive_url": null, "date": "2026-05-05T17:30:28", "name": "[v17,10/11] PCI/CXL: Mask/Unmask CXL protocol errors", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "1f58bdba56f277af42d33a71540711d31162bf62", "submitter": { "id": 82124, "url": "http://patchwork.ozlabs.org/api/1.2/people/82124/?format=api", "name": "Bowman, Terry", "email": "Terry.Bowman@amd.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260505173029.2718246-11-terry.bowman@amd.com/mbox/", "series": [ { "id": 502875, "url": "http://patchwork.ozlabs.org/api/1.2/series/502875/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502875", "date": "2026-05-05T17:30:19", "name": "Enable CXL PCIe Port Protocol Error handling and logging", "version": 17, "mbox": "http://patchwork.ozlabs.org/series/502875/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2233130/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2233130/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-53774-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=OB288ZfI;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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helo=satlexmb07.amd.com; pr=C", "From": "Terry Bowman <terry.bowman@amd.com>", "To": "<dave@stgolabs.net>, <jic23@kernel.org>, <dave.jiang@intel.com>,\n\t<alison.schofield@intel.com>, <djbw@kernel.org>, <bhelgaas@google.com>,\n\t<shiju.jose@huawei.com>, <ming.li@zohomail.com>,\n\t<Smita.KoralahalliChannabasappa@amd.com>, <rrichter@amd.com>,\n\t<dan.carpenter@linaro.org>, <PradeepVineshReddy.Kodamati@amd.com>,\n\t<lukas@wunner.de>, <Benjamin.Cheatham@amd.com>,\n\t<sathyanarayanan.kuppuswamy@linux.intel.com>, <vishal.l.verma@intel.com>,\n\t<alucerop@amd.com>, <ira.weiny@intel.com>, <corbet@lwn.net>,\n\t<rafael@kernel.org>, <xueshuai@linux.alibaba.com>,\n\t<linux-cxl@vger.kernel.org>", "CC": "<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<linux-acpi@vger.kernel.org>, <linux-doc@vger.kernel.org>,\n\t<terry.bowman@amd.com>", "Subject": "[PATCH v17 10/11] PCI/CXL: Mask/Unmask CXL protocol errors", "Date": "Tue, 5 May 2026 12:30:28 -0500", "Message-ID": "<20260505173029.2718246-11-terry.bowman@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260505173029.2718246-1-terry.bowman@amd.com>", "References": "<20260505173029.2718246-1-terry.bowman@amd.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "7bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com\n (10.181.42.216)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM2PEPF00003FC3:EE_|DS0PR12MB8787:EE_", "X-MS-Office365-Filtering-Correlation-Id": "a10c4559-103b-466a-acd0-08deaacc511b", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|82310400026|36860700016|376014|7416014|921020|18002099003|22082099003|56012099003;", "X-Microsoft-Antispam-Message-Info": "\n\t7YXNvnHg0aVln920mk7sZpBs6sDKE0IiZq8EqagR3H8eyyJAoNSVknA2Ynj3cX7tkWuIAT32IOCNQCHjlYH4W1IRelgWknKiaesP72gj4ubwQnvyBHAK3jLQQwKbif2gNrQmCMRUhDEDfNJP539jAlXLa7OHM634Ff/avOLOHdTK3uaso3DmWnndPPBI1cfkibmwTbQDUyeyCIdPwaONVjo58CErbfSDpdl7WxEc5auzg5PJCN/2ytmxGFAM8KDg1ZQeuvRKgbWWLHtSxHWM8IqIg7VbnrnXJMVZo1Iv7oqe1yFrnaPFmbkHUqPoR6tzJDOk/aasioX+CDcss2E1jebQHtDNVbyqjA2UXarq4ahBilFbmk1U20rzQ0n0QQW0vYaUmh9JTx+qZBW4/PQVqU1bFBS5rGJBREYi55rZFGCOC9eWRQNC7s5glGOc2KbKZHPjIyAdR6K5K+r7o4bz+AC+yrAX4+USmtQrni1JHyFygGyin3O+yjxRl3pHdtaEA3oMV6iqPvGX6sUUeHDeXewGdnY134kvQ/7KjT0uPt/RinQPQZ3yjKlcR47Njda8uRCOAa+UAZdjffyvC23umRbslXJVnbJ78PqHBNriK0Np+i8S8SuI8zoElrIySRwDBDxfTOFHQQMTUr+0m+CTOIeGfvNobPq9ZI7kZ5cLsPO7hhhXNw912xQKvZkc42owykT/2yjs+2usepyCiKRJrpHihoAlrkZGQCZHL94ps9bIsLo4xZN0ZZ2K07pTEQcwvxGWdDFGsdyVl6Q4pHUiqg==", "X-Forefront-Antispam-Report": "\n\tCIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(82310400026)(36860700016)(376014)(7416014)(921020)(18002099003)(22082099003)(56012099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tlQTuERPp2TZi/xjGVId9GusYQ+TL14voFLr3yYVO/dBqE5WwLI4EiHQtBBJI2LBZN7fhxZUSihjmHe5g71j24xuBdgZYY7bVhYAo0s2k/ki0wU8sRtp7h/lpgMHwHmqRRj3FslButomQYjkkEu/oes20AXQwlE4yyWbi/78S7JW1772ohivvqkK4K8asMlD2XMqfGDyhfMi2L3wczryfjEPrY4JIu36958b1ZlnkNs5d1M4YMWVmqk3eW0lRqji4BD/LqWzdQ8Pg1mX7DNMsjKksVpg/p+HMuNGFeGJt4WUtdvfQjIYyv9pGEXBRNlB6/x3DWCbYhkiOcUH3b7DtrZP9sRrKpCaSmbKGrdNWzOLMZtwJeyNHzKzGVGFu25/BhY8RnViHtFHg1TLyTRk/nyWKnHG1rbOItnXF9Xp9mUba9JivlzdVBQ0x9vaAat99", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2026 17:32:44.3450\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n a10c4559-103b-466a-acd0-08deaacc511b", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDM2PEPF00003FC3.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "DS0PR12MB8787" }, "content": "CXL protocol errors are not enabled for all CXL devices after boot. They\nmust be enabled in order to process CXL protocol errors. Provide matching\nteardown helpers so the masks are restored when a CXL Port or Downstream\nPort goes away.\n\nAdd pci_aer_mask_internal_errors() as the symmetric counterpart to\npci_aer_unmask_internal_errors() and export both for the cxl_core module.\n\nIntroduce cxl_unmask_proto_interrupts() and cxl_mask_proto_interrupts()\nin cxl_core to wrap the PCI helpers with the dev_is_pci() and\npcie_aer_is_native() gating CXL needs. Both helpers tolerate a NULL\n@dev so teardown callers do not have to special-case it.\n\nWire cxl_unmask_proto_interrupts() into the success path of\ncxl_dport_map_ras() and devm_cxl_port_ras_setup() so the unmask only\nruns when the RAS register block was actually mapped. Pair each unmask\nwith a devm_add_action_or_reset() registration of\ncxl_mask_proto_interrupts() scoped to the cxl_port device. The mask is\nthen restored when the cxl_port device releases its devres. This\napplies to Endpoints, Upstream Switch Ports, Downstream Switch Ports,\nand Root Ports.\n\nCo-developed-by: Dan Williams <djbw@kernel.org>\nSigned-off-by: Dan Williams <djbw@kernel.org>\nSigned-off-by: Terry Bowman <terry.bowman@amd.com>\n\n---\n\nChanges in v16->v17:\n- Drop redundant cxl_mask_proto_interrupts() calls from unregister_port()\n and cxl_dport_remove(); the devres action registered alongside the unmask\n is the sole mask path.\n- Update title\n- Remove unnecessary check for aer_capabilities\n- Gate cxl_unmask_proto_interrupts() on pcie_aer_is_native()\n- Add pci_aer_mask_internal_errors() and cxl_mask_proto_interrupts()\n- Only unmask on successful cxl_map_component_regs()\n- NULL-check @dev in cxl_{un,}mask_proto_interrupts()\n- Drop static and declare in core/core.h\n\nChange in v15 -> v16:\n- None\n\nChange in v14 -> v15:\n- None\n\nChanges in v13->v14:\n- Update commit title's prefix (Bjorn)\n\nChanges in v12->v13:\n- Add dev and dev_is_pci() NULL checks in cxl_unmask_proto_interrupts() (Terry)\n- Add Dave Jiang's and Ben's review-by\n\nChanges in v11->v12:\n- None\n---\n drivers/cxl/core/core.h | 4 +++\n drivers/cxl/core/ras.c | 63 ++++++++++++++++++++++++++++++++++++++---\n drivers/pci/pcie/aer.c | 25 ++++++++++++++++\n include/linux/aer.h | 2 ++\n 4 files changed, 90 insertions(+), 4 deletions(-)", "diff": "diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h\nindex 2c7387506dfb..ff39985d363f 100644\n--- a/drivers/cxl/core/core.h\n+++ b/drivers/cxl/core/core.h\n@@ -190,6 +190,8 @@ void cxl_dport_map_rch_aer(struct cxl_dport *dport);\n void cxl_disable_rch_root_ints(struct cxl_dport *dport);\n void cxl_handle_rdport_errors(struct pci_dev *pdev);\n void devm_cxl_dport_ras_setup(struct cxl_dport *dport);\n+void cxl_unmask_proto_interrupts(struct device *dev);\n+void cxl_mask_proto_interrupts(struct device *dev);\n #else\n static inline int cxl_ras_init(void)\n {\n@@ -207,6 +209,8 @@ static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }\n static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }\n static inline void cxl_handle_rdport_errors(struct pci_dev *pdev) { }\n static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { }\n+static inline void cxl_unmask_proto_interrupts(struct device *dev) { }\n+static inline void cxl_mask_proto_interrupts(struct device *dev) { }\n #endif /* CONFIG_CXL_RAS */\n \n int cxl_gpf_port_setup(struct cxl_dport *dport);\ndiff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\nindex a98ce0f412ad..b45e2b539b5f 100644\n--- a/drivers/cxl/core/ras.c\n+++ b/drivers/cxl/core/ras.c\n@@ -66,16 +66,59 @@ static void cxl_cper_prot_err_work_fn(struct work_struct *work)\n }\n static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn);\n \n+void cxl_unmask_proto_interrupts(struct device *dev)\n+{\n+\tstruct pci_dev *pdev;\n+\n+\tif (!dev || !dev_is_pci(dev))\n+\t\treturn;\n+\n+\tpdev = to_pci_dev(dev);\n+\tif (!pcie_aer_is_native(pdev))\n+\t\treturn;\n+\n+\tpci_aer_unmask_internal_errors(pdev);\n+}\n+\n+void cxl_mask_proto_interrupts(struct device *dev)\n+{\n+\tstruct pci_dev *pdev;\n+\n+\tif (!dev || !dev_is_pci(dev))\n+\t\treturn;\n+\n+\tpdev = to_pci_dev(dev);\n+\tif (!pcie_aer_is_native(pdev))\n+\t\treturn;\n+\n+\tpci_aer_mask_internal_errors(pdev);\n+}\n+\n+static void cxl_mask_proto_irqs(void *dev)\n+{\n+\tcxl_mask_proto_interrupts(dev);\n+}\n+\n static void cxl_dport_map_ras(struct cxl_dport *dport)\n {\n \tstruct cxl_register_map *map = &dport->reg_map;\n \tstruct device *dev = dport->dport_dev;\n \n-\tif (!map->component_map.ras.valid)\n+\tif (!map->component_map.ras.valid) {\n \t\tdev_dbg(dev, \"RAS registers not found\\n\");\n-\telse if (cxl_map_component_regs(map, &dport->regs.component,\n-\t\t\t\t\tBIT(CXL_CM_CAP_CAP_ID_RAS)))\n+\t\treturn;\n+\t}\n+\n+\tif (cxl_map_component_regs(map, &dport->regs.component,\n+\t\t\t\t BIT(CXL_CM_CAP_CAP_ID_RAS))) {\n \t\tdev_dbg(dev, \"Failed to map RAS capability.\\n\");\n+\t\treturn;\n+\t}\n+\n+\tcxl_unmask_proto_interrupts(dev);\n+\tif (devm_add_action_or_reset(dport_to_host(dport),\n+\t\t\t\t cxl_mask_proto_irqs, dev))\n+\t\tdev_warn(dev, \"failed to register CXL proto-irq mask cleanup\\n\");\n }\n \n /**\n@@ -109,6 +152,7 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_rch_ras_setup, \"CXL\");\n void devm_cxl_port_ras_setup(struct cxl_port *port)\n {\n \tstruct cxl_register_map *map = &port->reg_map;\n+\tstruct device *dev;\n \n \tif (!map->component_map.ras.valid) {\n \t\tdev_dbg(&port->dev, \"RAS registers not found\\n\");\n@@ -117,8 +161,19 @@ void devm_cxl_port_ras_setup(struct cxl_port *port)\n \n \tmap->host = &port->dev;\n \tif (cxl_map_component_regs(map, &port->regs,\n-\t\t\t\t BIT(CXL_CM_CAP_CAP_ID_RAS)))\n+\t\t\t\t BIT(CXL_CM_CAP_CAP_ID_RAS))) {\n \t\tdev_dbg(&port->dev, \"Failed to map RAS capability\\n\");\n+\t\treturn;\n+\t}\n+\n+\tdev = is_cxl_endpoint(port) ? port->uport_dev->parent : port->uport_dev;\n+\tif (!dev_is_pci(dev))\n+\t\treturn;\n+\n+\tcxl_unmask_proto_interrupts(dev);\n+\tif (devm_add_action_or_reset(&port->dev, cxl_mask_proto_irqs, dev))\n+\t\tdev_warn(&port->dev,\n+\t\t\t \"Failed to register CXL proto-irq mask cleanup\\n\");\n }\n EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, \"CXL\");\n \ndiff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c\nindex b9c6c7b97217..eaa36fe0eb31 100644\n--- a/drivers/pci/pcie/aer.c\n+++ b/drivers/pci/pcie/aer.c\n@@ -1151,6 +1151,31 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev)\n */\n EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, \"cxl_core\");\n \n+/**\n+ * pci_aer_mask_internal_errors - mask internal errors\n+ * @dev: pointer to the pci_dev data structure\n+ *\n+ * Mask internal errors in the Uncorrectable and Correctable Error\n+ * Mask registers.\n+ *\n+ * Note: AER must be enabled and supported by the device which must be\n+ * checked in advance, e.g. with pcie_aer_is_native().\n+ */\n+void pci_aer_mask_internal_errors(struct pci_dev *dev)\n+{\n+\tint aer = dev->aer_cap;\n+\tu32 mask;\n+\n+\tpci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);\n+\tmask |= PCI_ERR_UNC_INTN;\n+\tpci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask);\n+\n+\tpci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);\n+\tmask |= PCI_ERR_COR_INTERNAL;\n+\tpci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);\n+}\n+EXPORT_SYMBOL_FOR_MODULES(pci_aer_mask_internal_errors, \"cxl_core\");\n+\n /**\n * pci_aer_handle_error - handle logging error into an event log\n * @dev: pointer to pci_dev data structure of error source device\ndiff --git a/include/linux/aer.h b/include/linux/aer.h\nindex 979ed2f9fd38..c52db62d4c7e 100644\n--- a/include/linux/aer.h\n+++ b/include/linux/aer.h\n@@ -71,6 +71,7 @@ int pci_aer_clear_nonfatal_status(struct pci_dev *dev);\n void pci_aer_clear_fatal_status(struct pci_dev *dev);\n int pcie_aer_is_native(struct pci_dev *dev);\n void pci_aer_unmask_internal_errors(struct pci_dev *dev);\n+void pci_aer_mask_internal_errors(struct pci_dev *dev);\n #else\n static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)\n {\n@@ -79,6 +80,7 @@ static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)\n static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }\n static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }\n static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { }\n+static inline void pci_aer_mask_internal_errors(struct pci_dev *dev) { }\n #endif\n \n #ifdef CONFIG_CXL_RAS\n", "prefixes": [ "v17", "10/11" ] }