[{"id":3686783,"web_url":"http://patchwork.ozlabs.org/comment/3686783/","msgid":"<20260506010107.48AF4C2BCB4@smtp.kernel.org>","list_archive_url":null,"date":"2026-05-06T01:01:06","subject":"Re: [PATCH v17 10/11] PCI/CXL: Mask/Unmask CXL protocol errors","submitter":{"id":93311,"url":"http://patchwork.ozlabs.org/api/people/93311/","name":null,"email":"sashiko-bot@kernel.org"},"content":"Thank you for your contribution! Sashiko AI review found 1 potential issue(s) to consider:\n- [High] Use-After-Free (UAF) in devres teardown callback `cxl_mask_proto_irqs` during device hot-removal.\n--\n\ncommit f060d6be86b55217cf830c823d56a91f3c54980c\nAuthor: Terry Bowman \n\nPCI/CXL: Mask/Unmask CXL protocol errors\n\nThis commit introduces helpers to mask and unmask CXL protocol errors and\nwires them into the success paths of cxl_dport_map_ras() and\ndevm_cxl_port_ras_setup(). Teardown is handled via devm actions tied to\nthe CXL port devices.\n\n> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\n> index a98ce0f412adb..b45e2b539b5fa 100644\n> --- a/drivers/cxl/core/ras.c\n> +++ b/drivers/cxl/core/ras.c\n[ ... ]\n> static void cxl_dport_map_ras(struct cxl_dport *dport)\n> {\n> \tstruct cxl_register_map *map = &dport->reg_map;\n> \tstruct device *dev = dport->dport_dev;\n> \n> -\tif (!map->component_map.ras.valid)\n> +\tif (!map->component_map.ras.valid) {\n> \t\tdev_dbg(dev, \"RAS registers not found\\n\");\n> -\telse if (cxl_map_component_regs(map, &dport->regs.component,\n> -\t\t\t\t\tBIT(CXL_CM_CAP_CAP_ID_RAS)))\n> +\t\treturn;\n> +\t}\n> +\n> +\tif (cxl_map_component_regs(map, &dport->regs.component,\n> +\t\t\t\t BIT(CXL_CM_CAP_CAP_ID_RAS))) {\n> \t\tdev_dbg(dev, \"Failed to map RAS capability.\\n\");\n> +\t\treturn;\n> +\t}\n> +\n> +\tcxl_unmask_proto_interrupts(dev);\n> +\tif (devm_add_action_or_reset(dport_to_host(dport),\n> +\t\t\t\t cxl_mask_proto_irqs, dev))\n> +\t\tdev_warn(dev, \"failed to register CXL proto-irq mask cleanup\\n\");\n> }\n\nCould this lead to a use-after-free regression during device hot-removal?\n\nThe devres action is registered to the host device (dport_to_host(dport)),\nwhich corresponds to the switch's upstream port. However, the data passed\nto the callback is dev (dport->dport_dev), which represents the downstream\nPCI device.\n\nDuring a hot-remove of a CXL switch, the PCI core recursively removes and\nfrees child devices before unbinding and removing the parent device.\n\nSince there doesn't appear to be a reference held on dport->dport_dev when\nsetting up this devres action, could the downstream PCI device be freed\nwhile the upstream port is still active?\n\nIf so, when the upstream port is finally unbound, its devres actions would\nexecute and call cxl_mask_proto_irqs(dev) with an already-freed downstream\ndevice pointer, resulting in a use-after-free.","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=ZJ6sg8pb;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1778029267;\n\tbh=oVwPWZ6uZeC/EJrd/PraiCTW4HOIaV/2x4PuFdZC9NQ=;\n\th=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date:From;\n\tb=ZJ6sg8pbpkUQXi/+nm1t38K2aYIU7t3c3VSagQezqBAohx4aZOURbXCeYTKnSADiU\n\t fT0I8Ppk18v7G8VLnHU7Zy54pHIjODcivacMQfszHgZXhwry/SlIK6N8IR7YEK/bzn\n\t 5+xQYb3plXLy/B6qEFi5Nr3cRtukvO7NJVBQNAv8x8yQrRcsmBrKxRDdK7HporuRlk\n\t Bxk/tjVmkoeNWEDECBazmWDDv9V8eh2EA6QL/gkCJYdU9MQkhE0RO4KwfO/T1wGALg\n\t TlX4WsbyYKZBEA2a7nhRBPqiVoHCbMuJa4RAObPR2LJhre4k5M/rgq1fKb/HgaGT1e\n\t Cy6NhGE4SKVxw==","From":"sashiko-bot@kernel.org","Subject":"Re: [PATCH v17 10/11] PCI/CXL: Mask/Unmask CXL protocol errors","Reply-To":"sashiko@lists.linux.dev","To":"\"Terry Bowman\" ","Cc":"linux-pci@vger.kernel.org","In-Reply-To":"<20260505173029.2718246-11-terry.bowman@amd.com>","References":"<20260505173029.2718246-11-terry.bowman@amd.com>","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"quoted-printable","Date":"Wed, 06 May 2026 01:01:06 +0000","Message-Id":"<20260506010107.48AF4C2BCB4@smtp.kernel.org>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""}},{"id":3687288,"web_url":"http://patchwork.ozlabs.org/comment/3687288/","msgid":"<38155e50-c0c0-4f51-9777-243f0dd049ca@intel.com>","list_archive_url":null,"date":"2026-05-06T18:00:57","subject":"Re: [PATCH v17 10/11] PCI/CXL: Mask/Unmask CXL protocol errors","submitter":{"id":13225,"url":"http://patchwork.ozlabs.org/api/people/13225/","name":"Dave Jiang","email":"dave.jiang@intel.com"},"content":"On 5/5/26 10:30 AM, Terry Bowman wrote:\n> CXL protocol errors are not enabled for all CXL devices after boot. They\n> must be enabled in order to process CXL protocol errors. Provide matching\n> teardown helpers so the masks are restored when a CXL Port or Downstream\n> Port goes away.\n> \n> Add pci_aer_mask_internal_errors() as the symmetric counterpart to\n> pci_aer_unmask_internal_errors() and export both for the cxl_core module.\n> \n> Introduce cxl_unmask_proto_interrupts() and cxl_mask_proto_interrupts()\n> in cxl_core to wrap the PCI helpers with the dev_is_pci() and\n> pcie_aer_is_native() gating CXL needs. Both helpers tolerate a NULL\n> @dev so teardown callers do not have to special-case it.\n> \n> Wire cxl_unmask_proto_interrupts() into the success path of\n> cxl_dport_map_ras() and devm_cxl_port_ras_setup() so the unmask only\n> runs when the RAS register block was actually mapped. Pair each unmask\n> with a devm_add_action_or_reset() registration of\n> cxl_mask_proto_interrupts() scoped to the cxl_port device. The mask is\n> then restored when the cxl_port device releases its devres. This\n> applies to Endpoints, Upstream Switch Ports, Downstream Switch Ports,\n> and Root Ports.\n> \n> Co-developed-by: Dan Williams \n> Signed-off-by: Dan Williams \n> Signed-off-by: Terry Bowman \n\nReviewed-by: Dave Jiang \n\nI do wonder if we should save the original mask values and write those back rather than blindly remask everything when we are done.\n\n\n> \n> ---\n> \n> Changes in v16->v17:\n> - Drop redundant cxl_mask_proto_interrupts() calls from unregister_port()\n> and cxl_dport_remove(); the devres action registered alongside the unmask\n> is the sole mask path.\n> - Update title\n> - Remove unnecessary check for aer_capabilities\n> - Gate cxl_unmask_proto_interrupts() on pcie_aer_is_native()\n> - Add pci_aer_mask_internal_errors() and cxl_mask_proto_interrupts()\n> - Only unmask on successful cxl_map_component_regs()\n> - NULL-check @dev in cxl_{un,}mask_proto_interrupts()\n> - Drop static and declare in core/core.h\n> \n> Change in v15 -> v16:\n> - None\n> \n> Change in v14 -> v15:\n> - None\n> \n> Changes in v13->v14:\n> - Update commit title's prefix (Bjorn)\n> \n> Changes in v12->v13:\n> - Add dev and dev_is_pci() NULL checks in cxl_unmask_proto_interrupts() (Terry)\n> - Add Dave Jiang's and Ben's review-by\n> \n> Changes in v11->v12:\n> - None\n> ---\n> drivers/cxl/core/core.h | 4 +++\n> drivers/cxl/core/ras.c | 63 ++++++++++++++++++++++++++++++++++++++---\n> drivers/pci/pcie/aer.c | 25 ++++++++++++++++\n> include/linux/aer.h | 2 ++\n> 4 files changed, 90 insertions(+), 4 deletions(-)\n> \n> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h\n> index 2c7387506dfb..ff39985d363f 100644\n> --- a/drivers/cxl/core/core.h\n> +++ b/drivers/cxl/core/core.h\n> @@ -190,6 +190,8 @@ void cxl_dport_map_rch_aer(struct cxl_dport *dport);\n> void cxl_disable_rch_root_ints(struct cxl_dport *dport);\n> void cxl_handle_rdport_errors(struct pci_dev *pdev);\n> void devm_cxl_dport_ras_setup(struct cxl_dport *dport);\n> +void cxl_unmask_proto_interrupts(struct device *dev);\n> +void cxl_mask_proto_interrupts(struct device *dev);\n> #else\n> static inline int cxl_ras_init(void)\n> {\n> @@ -207,6 +209,8 @@ static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }\n> static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }\n> static inline void cxl_handle_rdport_errors(struct pci_dev *pdev) { }\n> static inline void devm_cxl_dport_ras_setup(struct cxl_dport *dport) { }\n> +static inline void cxl_unmask_proto_interrupts(struct device *dev) { }\n> +static inline void cxl_mask_proto_interrupts(struct device *dev) { }\n> #endif /* CONFIG_CXL_RAS */\n> \n> int cxl_gpf_port_setup(struct cxl_dport *dport);\n> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\n> index a98ce0f412ad..b45e2b539b5f 100644\n> --- a/drivers/cxl/core/ras.c\n> +++ b/drivers/cxl/core/ras.c\n> @@ -66,16 +66,59 @@ static void cxl_cper_prot_err_work_fn(struct work_struct *work)\n> }\n> static DECLARE_WORK(cxl_cper_prot_err_work, cxl_cper_prot_err_work_fn);\n> \n> +void cxl_unmask_proto_interrupts(struct device *dev)\n> +{\n> +\tstruct pci_dev *pdev;\n> +\n> +\tif (!dev || !dev_is_pci(dev))\n> +\t\treturn;\n> +\n> +\tpdev = to_pci_dev(dev);\n> +\tif (!pcie_aer_is_native(pdev))\n> +\t\treturn;\n> +\n> +\tpci_aer_unmask_internal_errors(pdev);\n> +}\n> +\n> +void cxl_mask_proto_interrupts(struct device *dev)\n> +{\n> +\tstruct pci_dev *pdev;\n> +\n> +\tif (!dev || !dev_is_pci(dev))\n> +\t\treturn;\n> +\n> +\tpdev = to_pci_dev(dev);\n> +\tif (!pcie_aer_is_native(pdev))\n> +\t\treturn;\n> +\n> +\tpci_aer_mask_internal_errors(pdev);\n> +}\n> +\n> +static void cxl_mask_proto_irqs(void *dev)\n> +{\n> +\tcxl_mask_proto_interrupts(dev);\n> +}\n> +\n> static void cxl_dport_map_ras(struct cxl_dport *dport)\n> {\n> \tstruct cxl_register_map *map = &dport->reg_map;\n> \tstruct device *dev = dport->dport_dev;\n> \n> -\tif (!map->component_map.ras.valid)\n> +\tif (!map->component_map.ras.valid) {\n> \t\tdev_dbg(dev, \"RAS registers not found\\n\");\n> -\telse if (cxl_map_component_regs(map, &dport->regs.component,\n> -\t\t\t\t\tBIT(CXL_CM_CAP_CAP_ID_RAS)))\n> +\t\treturn;\n> +\t}\n> +\n> +\tif (cxl_map_component_regs(map, &dport->regs.component,\n> +\t\t\t\t BIT(CXL_CM_CAP_CAP_ID_RAS))) {\n> \t\tdev_dbg(dev, \"Failed to map RAS capability.\\n\");\n> +\t\treturn;\n> +\t}\n> +\n> +\tcxl_unmask_proto_interrupts(dev);\n> +\tif (devm_add_action_or_reset(dport_to_host(dport),\n> +\t\t\t\t cxl_mask_proto_irqs, dev))\n> +\t\tdev_warn(dev, \"failed to register CXL proto-irq mask cleanup\\n\");\n> }\n> \n> /**\n> @@ -109,6 +152,7 @@ EXPORT_SYMBOL_NS_GPL(devm_cxl_dport_rch_ras_setup, \"CXL\");\n> void devm_cxl_port_ras_setup(struct cxl_port *port)\n> {\n> \tstruct cxl_register_map *map = &port->reg_map;\n> +\tstruct device *dev;\n> \n> \tif (!map->component_map.ras.valid) {\n> \t\tdev_dbg(&port->dev, \"RAS registers not found\\n\");\n> @@ -117,8 +161,19 @@ void devm_cxl_port_ras_setup(struct cxl_port *port)\n> \n> \tmap->host = &port->dev;\n> \tif (cxl_map_component_regs(map, &port->regs,\n> -\t\t\t\t BIT(CXL_CM_CAP_CAP_ID_RAS)))\n> +\t\t\t\t BIT(CXL_CM_CAP_CAP_ID_RAS))) {\n> \t\tdev_dbg(&port->dev, \"Failed to map RAS capability\\n\");\n> +\t\treturn;\n> +\t}\n> +\n> +\tdev = is_cxl_endpoint(port) ? port->uport_dev->parent : port->uport_dev;\n> +\tif (!dev_is_pci(dev))\n> +\t\treturn;\n> +\n> +\tcxl_unmask_proto_interrupts(dev);\n> +\tif (devm_add_action_or_reset(&port->dev, cxl_mask_proto_irqs, dev))\n> +\t\tdev_warn(&port->dev,\n> +\t\t\t \"Failed to register CXL proto-irq mask cleanup\\n\");\n> }\n> EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, \"CXL\");\n> \n> diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c\n> index b9c6c7b97217..eaa36fe0eb31 100644\n> --- a/drivers/pci/pcie/aer.c\n> +++ b/drivers/pci/pcie/aer.c\n> @@ -1151,6 +1151,31 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev)\n> */\n> EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, \"cxl_core\");\n> \n> +/**\n> + * pci_aer_mask_internal_errors - mask internal errors\n> + * @dev: pointer to the pci_dev data structure\n> + *\n> + * Mask internal errors in the Uncorrectable and Correctable Error\n> + * Mask registers.\n> + *\n> + * Note: AER must be enabled and supported by the device which must be\n> + * checked in advance, e.g. with pcie_aer_is_native().\n> + */\n> +void pci_aer_mask_internal_errors(struct pci_dev *dev)\n> +{\n> +\tint aer = dev->aer_cap;\n> +\tu32 mask;\n> +\n> +\tpci_read_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, &mask);\n> +\tmask |= PCI_ERR_UNC_INTN;\n> +\tpci_write_config_dword(dev, aer + PCI_ERR_UNCOR_MASK, mask);\n> +\n> +\tpci_read_config_dword(dev, aer + PCI_ERR_COR_MASK, &mask);\n> +\tmask |= PCI_ERR_COR_INTERNAL;\n> +\tpci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask);\n> +}\n> +EXPORT_SYMBOL_FOR_MODULES(pci_aer_mask_internal_errors, \"cxl_core\");\n> +\n> /**\n> * pci_aer_handle_error - handle logging error into an event log\n> * @dev: pointer to pci_dev data structure of error source device\n> diff --git a/include/linux/aer.h b/include/linux/aer.h\n> index 979ed2f9fd38..c52db62d4c7e 100644\n> --- a/include/linux/aer.h\n> +++ b/include/linux/aer.h\n> @@ -71,6 +71,7 @@ int pci_aer_clear_nonfatal_status(struct pci_dev *dev);\n> void pci_aer_clear_fatal_status(struct pci_dev *dev);\n> int pcie_aer_is_native(struct pci_dev *dev);\n> void pci_aer_unmask_internal_errors(struct pci_dev *dev);\n> +void pci_aer_mask_internal_errors(struct pci_dev *dev);\n> #else\n> static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)\n> {\n> @@ -79,6 +80,7 @@ static inline int pci_aer_clear_nonfatal_status(struct pci_dev *dev)\n> static inline void pci_aer_clear_fatal_status(struct pci_dev *dev) { }\n> static inline int pcie_aer_is_native(struct pci_dev *dev) { return 0; }\n> static inline void pci_aer_unmask_internal_errors(struct pci_dev *dev) { }\n> +static inline void pci_aer_mask_internal_errors(struct pci_dev *dev) { }\n> #endif\n> \n> #ifdef CONFIG_CXL_RAS","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=IlvY0Vio;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; helo=tor.lore.kernel.org;\n envelope-from=linux-pci+bounces-53928-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com\n header.b=\"IlvY0Vio\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=192.198.163.11","smtp.subspace.kernel.org;\n dmarc=pass (p=none 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alison.schofield@intel.com, djbw@kernel.org, bhelgaas@google.com,\n shiju.jose@huawei.com, ming.li@zohomail.com,\n Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,\n dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com,\n lukas@wunner.de, Benjamin.Cheatham@amd.com,\n sathyanarayanan.kuppuswamy@linux.intel.com, vishal.l.verma@intel.com,\n alucerop@amd.com, ira.weiny@intel.com, corbet@lwn.net, rafael@kernel.org,\n xueshuai@linux.alibaba.com, linux-cxl@vger.kernel.org","Cc":"linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n linux-acpi@vger.kernel.org, linux-doc@vger.kernel.org","References":"<20260505173029.2718246-1-terry.bowman@amd.com>\n <20260505173029.2718246-11-terry.bowman@amd.com>","Content-Language":"en-US","From":"Dave Jiang ","In-Reply-To":"<20260505173029.2718246-11-terry.bowman@amd.com>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit"}},{"id":3687987,"web_url":"http://patchwork.ozlabs.org/comment/3687987/","msgid":"<20260507192922.451244f1@jic23-huawei>","list_archive_url":null,"date":"2026-05-07T18:29:22","subject":"Re: [PATCH v17 10/11] PCI/CXL: Mask/Unmask CXL protocol errors","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Tue, 5 May 2026 12:30:28 -0500\nTerry Bowman wrote:\n\n> CXL protocol errors are not enabled for all CXL devices after boot. They\n> must be enabled in order to process CXL protocol errors. Provide matching\n> teardown helpers so the masks are restored when a CXL Port or Downstream\n> Port goes away.\n> \n> Add pci_aer_mask_internal_errors() as the symmetric counterpart to\n> pci_aer_unmask_internal_errors() and export both for the cxl_core module.\n> \n> Introduce cxl_unmask_proto_interrupts() and cxl_mask_proto_interrupts()\n> in cxl_core to wrap the PCI helpers with the dev_is_pci() and\n> pcie_aer_is_native() gating CXL needs. Both helpers tolerate a NULL\n> @dev so teardown callers do not have to special-case it.\n> \n> Wire cxl_unmask_proto_interrupts() into the success path of\n> cxl_dport_map_ras() and devm_cxl_port_ras_setup() so the unmask only\n> runs when the RAS register block was actually mapped. Pair each unmask\n> with a devm_add_action_or_reset() registration of\n> cxl_mask_proto_interrupts() scoped to the cxl_port device. The mask is\n> then restored when the cxl_port device releases its devres. This\n> applies to Endpoints, Upstream Switch Ports, Downstream Switch Ports,\n> and Root Ports.\n> \n> Co-developed-by: Dan Williams \n> Signed-off-by: Dan Williams \n> Signed-off-by: Terry Bowman \n\nI'd have definitely preferred if the ras code generally reported\nerrors on setup and then we decided whether to taken any notice\nat the top of the stack, but that's existing code so not your problem.\n\nReviewed-by: Jonathan Cameron \n\nSubject to Dave's interesting suggestion...","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=WK6EcH4B;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-54117-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"WK6EcH4B\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBLQg4fLnz1yKd\n\tfor ; Fri, 08 May 2026 04:30:19 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id 651D43025D3D\n\tfor ; Thu, 7 May 2026 18:29:32 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 3736F45BD7C;\n\tThu, 7 May 2026 18:29:31 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id 058B53B7B7F;\n\tThu, 7 May 2026 18:29:30 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 7C50CC2BCB2;\n\tThu, 7 May 2026 18:29:25 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1778178571; cv=none;\n b=ZdTVb+jrvuaV8aht3MfiGTVXPVFSFUaE7PbIRAZg2mVmVxOrAhUhENmHcxCJBJajdZeZglezIO+RvAsgNvknZV0dq17nodQ36zCngv+PA7JGdTeUT6/+NH4Dr/z92u//+D9X2V2uqDmH+kKSTJHEt/QzwC98TO8NEfD3uiZ8LjE=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778178571; c=relaxed/simple;\n\tbh=Li5t44X8CLBTyXHBrX5yYHLu5aIsEaNbJr/x5ikzBlY=;\n\th=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=Bh8D/Iak3H7n2CEkyn+uHoQPa8+SEcfUdP1vMotxTZF9I1OTUZenlYyB6Y3zZFhJsAoaOhh7xY5l2M6M7vNWqK9hbDEoDXpix8vMwXYth95YmRnU4yPQAhLbaKvg6GVOxb/llVbqfKJhc0JzdcQ/MJE8vBrTQRTiXHk0fNnJRGQ=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=WK6EcH4B; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1778178570;\n\tbh=Li5t44X8CLBTyXHBrX5yYHLu5aIsEaNbJr/x5ikzBlY=;\n\th=Date:From:To:Cc:Subject:In-Reply-To:References:From;\n\tb=WK6EcH4BJ9IPRxezKa+gmItkU5zufMLjv57rFPQ5Z+jKdchzc+wIS7mO4fmT0C3F4\n\t 77/Skfz6S3hXj3Vwkzj3R7xjriRdOGGsFZeZb7meuSTEs/QpebcWS4fyFBbQlpuKwQ\n\t ZnTf4AW6RWoP90vWGxd4z1+mtakKzw5sM3fmxk8IdNTE7/+h4XEJxPKmMO54rnJTb/\n\t g70yV6j2YlWK/lfTQAFtiTwpd2gM4EW230PKLD9kEHPy5oGow6y/H4K2r4+wR01tDj\n\t /V3l4TY8qJ/hhitcx0ZQf7rholkxoED+Gv+ZNsHM9xflbYRwc6HKgqAdWvgkIf7adY\n\t RF2uC03fTOP+w==","Date":"Thu, 7 May 2026 19:29:22 +0100","From":"Jonathan Cameron ","To":"Terry Bowman ","Cc":", ,\n , , ,\n , ,\n , ,\n , ,\n , ,\n , ,\n , , ,\n , ,\n , ,\n , ,\n ","Subject":"Re: [PATCH v17 10/11] PCI/CXL: Mask/Unmask CXL protocol errors","Message-ID":"<20260507192922.451244f1@jic23-huawei>","In-Reply-To":"<20260505173029.2718246-11-terry.bowman@amd.com>","References":"<20260505173029.2718246-1-terry.bowman@amd.com>\n\t<20260505173029.2718246-11-terry.bowman@amd.com>","X-Mailer":"Claws Mail 4.4.0 (GTK 3.24.52; x86_64-pc-linux-gnu)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit"}}]