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GET /api/1.2/patches/2233129/?format=api
{ "id": 2233129, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2233129/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260505173029.2718246-10-terry.bowman@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260505173029.2718246-10-terry.bowman@amd.com>", "list_archive_url": null, "date": "2026-05-05T17:30:27", "name": "[v17,09/11] cxl: Update Endpoint AER uncorrectable handler", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "90eb0f797cb9acd4d8b5e7e22345bf52df3a13da", "submitter": { "id": 82124, "url": "http://patchwork.ozlabs.org/api/1.2/people/82124/?format=api", "name": "Bowman, Terry", "email": "Terry.Bowman@amd.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260505173029.2718246-10-terry.bowman@amd.com/mbox/", "series": [ { "id": 502875, "url": "http://patchwork.ozlabs.org/api/1.2/series/502875/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502875", "date": "2026-05-05T17:30:19", "name": "Enable CXL PCIe Port Protocol Error handling and logging", "version": 17, "mbox": "http://patchwork.ozlabs.org/series/502875/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2233129/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2233129/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-53773-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=k63gOZd2;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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helo=satlexmb07.amd.com; pr=C", "From": "Terry Bowman <terry.bowman@amd.com>", "To": "<dave@stgolabs.net>, <jic23@kernel.org>, <dave.jiang@intel.com>,\n\t<alison.schofield@intel.com>, <djbw@kernel.org>, <bhelgaas@google.com>,\n\t<shiju.jose@huawei.com>, <ming.li@zohomail.com>,\n\t<Smita.KoralahalliChannabasappa@amd.com>, <rrichter@amd.com>,\n\t<dan.carpenter@linaro.org>, <PradeepVineshReddy.Kodamati@amd.com>,\n\t<lukas@wunner.de>, <Benjamin.Cheatham@amd.com>,\n\t<sathyanarayanan.kuppuswamy@linux.intel.com>, <vishal.l.verma@intel.com>,\n\t<alucerop@amd.com>, <ira.weiny@intel.com>, <corbet@lwn.net>,\n\t<rafael@kernel.org>, <xueshuai@linux.alibaba.com>,\n\t<linux-cxl@vger.kernel.org>", "CC": "<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<linux-acpi@vger.kernel.org>, <linux-doc@vger.kernel.org>,\n\t<terry.bowman@amd.com>", "Subject": "[PATCH v17 09/11] cxl: Update Endpoint AER uncorrectable handler", "Date": "Tue, 5 May 2026 12:30:27 -0500", "Message-ID": "<20260505173029.2718246-10-terry.bowman@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260505173029.2718246-1-terry.bowman@amd.com>", "References": "<20260505173029.2718246-1-terry.bowman@amd.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "7bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com\n (10.181.42.216)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM2PEPF00003FC9:EE_|IA1PR12MB6356:EE_", "X-MS-Office365-Filtering-Correlation-Id": "97d476ff-9ee3-46cf-bca5-08deaacc4a54", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|376014|1800799024|7416014|82310400026|36860700016|18002099003|22082099003|56012099003|921020;", "X-Microsoft-Antispam-Message-Info": "\n\talRJNLyhcsdno9IO/q86/Yw/3WL52ONJjZTQBH45lFIEeDtrqR4JecFC4syzWfv3mQBQXaMjAyVnu2UjT4DW3HoIihqkFEJfx+FVGBuxY2MRMWGssEyiP72Zt/ToXzHBhmSm8qFMb39FLxx4SPcga1b3p37DgkTgI0oT7nmPQTl4f4LN1LXNssUgMKWHpV6zl0RllMQOnw3Xq/RqmttWv96+wfKgyh2qddRRUpBRcp9M9TUhwakGrijaimc5m0bZlH4BdoBllWeSx4mHmynGJpf1nySBx48sqqqGMmkiejBOviYyoYct4GqCMg7kN+hBIbSYTPEMt1EyzeRv38cGGKQkoQSuCs/gne9Hy7tmBD6lNu1fzMQiaQAOQKm1afOTWWMoFXar+Z0oTxF5iHWyrtG6xRtlsEe9K0IFoq2V7hVa6U1PEbmhjWKQ8f1E0UTcEb3djTrjjOPG8D9EorNtWeRbQVYEeYba9JHZVLjyri3iG+laN4sG38b+uspjmA0zt/NCGuHPhAQgSV8LqWLvckunLrc45bH5HakeaJVZZ9OqhgFSJ0P8E7wEi07qVD92tle4/WpFPdIGi5SjEFj6LQMM6lpc171uBOD5tB+EM6zMvlCJ4Z84AzArlOmwBBXro97E/gfVbItgYYBmuqogKglzp3G72zib41Pj+6Or473F7HYmAI1FrsfwoRDxQPp4XavoSGuY/3q6hWX8Kovh5DSr0qlxqSKu084IUudK1jhtqLTp1nWApSoOYi/nMuPqwUHBg2YiaFD9lkASb96zSw==", "X-Forefront-Antispam-Report": "\n\tCIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(376014)(1800799024)(7416014)(82310400026)(36860700016)(18002099003)(22082099003)(56012099003)(921020);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tanyT7u9Da+OX4WTsEQAe8qhHvZtOT1OMXrs1mdySW8vZrbmAUpG0ufV1pEd8XEwDFZKsFLaEy09DgDhC+eWL1W6PDsdIskvKqDMJKh7+QUB53scqUHXMGAzK6E+65lVI9Oh3Hx6igy3hRgKbZhUqZF4eovAtLL/T9CmD/RSPvNnuqAifYkicL6ZTd9SrDdDw116XJqu/DNjH9qJmmjATk03jMvN40ElqV0SAERx0LWg3pRJPS9l4dFCHoWIfAz4dzgZr1mKHmPrYvkev16gg777Giftjw/YSHOLcuNpF2FZab46yWnJJxgrxnzlhijPhEP2l2qtxEHD0s0tfHDcA50S7Gp3KkOB3kGmd2gcqeQqm4lhMKsk1w+cDSXT4oG5D+cw628WgihN7F3eVz7qSD09E1O/cQHnHRo6HvKCH4CAAXCGjR6jPpzJ9SVgULzTU", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2026 17:32:32.9466\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 97d476ff-9ee3-46cf-bca5-08deaacc4a54", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDM2PEPF00003FC9.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6356" }, "content": "The CXL cxl_core driver now implements protocol RAS support. PCI\nuncorrectable (UCE) protocol errors, however, continue to be reported via\nthe AER capability and must still be handled by a PCI error recovery callback.\nUCE handling is required to provide direction for recovery.\n\nReplace the existing cxl_error_detected() callback in cxl/pci.c with a new\ncxl_pci_error_detected() implementation that handles uncorrectable AER PCI\nprotocol errors.\n\nThe handler decides solely based on the pci_channel_state_t parameter and\ndoes not access PCIe AER capability registers from .error_detected, matching\nthe pattern used by other drivers including the NVMe and ixgbe drivers.\nCXL.cachemem-corrupting protocol errors are routed separately through the\nAER-CXL kfifo to cxl_handle_proto_error(), so cxl_pci does not need to\nsecond-guess the AER core's classification.\n\nclaude-opus-4.7 was used for research on PCI error state transitions and\nrequirements.\n\nAssisted-by: Claude:claude-opus-4.7\nSigned-off-by: Terry Bowman <terry.bowman@amd.com>\n\n---\n\nChanges in v16->v17:\n- Rename pci_error_handlers struct instance to cxl_pci_error_handlers to\n avoid shadowing the struct type tag.\n- Restore scoped_guard(device) and dev->driver check around AER read.\n- NULL-check find_cxl_port_by_dev() before deref of port->uport_dev.\n- Updated commit message. (Terry)\n- Add scope cleanup for port variable in cxl_pci_error_detected() (Terry)\n- Drop cxl_uncor_aer_present(), rely on AER state\n\nChanges in v15->v16:\n- Update commit message (DaveJ)\n- s/cxl_handle_aer()/cxl_uncor_aer_present()/g (Jonathan)\n- cxl_uncor_aer_present(): Leave original result calculation based on\n if a UCE is present and the provided state (Terry)\n- Add call to pci_print_aer(). AER fails to log because is upstream\n link (Terry)\n\nChanges in v14->v15:\n- Update commit message and title. Added Bjorn's ack.\n- Move CE and UCE handling logic here\n\nChanges in v13->v14:\n- Add Dave Jiang's review-by\n- Update commit message & headline (Bjorn)\n- Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to\n one line (Jonathan)\n- Remove cxl_walk_port() (Dan)\n- Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is\n sufficient (Dan)\n- Remove device_lock_if()\n- Combined CE and UCE here (Terry)\n\nChanges in v12->v13:\n- Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue\n patch (Terry)\n- Remove EP case in cxl_get_ras_base(), not used. (Terry)\n- Remove check for dport->dport_dev (Dave)\n- Remove whitespace (Terry)\n\nChanges in v11->v12:\n- Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and\n pci_to_cxl_dev()\n- Change cxl_error_detected() -> cxl_cor_error_detected()\n- Remove NULL variable assignments\n- Replace bus_find_device() with find_cxl_port_by_uport() for upstream\n port searches.\n\nChanges in v10->v11:\n- None\n---\n drivers/cxl/core/ras.c | 43 ++++++++++++++++--------------------------\n drivers/cxl/cxlpci.h | 8 ++++----\n drivers/cxl/pci.c | 6 +++---\n 3 files changed, 23 insertions(+), 34 deletions(-)", "diff": "diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\nindex 5cc4087c2807..a98ce0f412ad 100644\n--- a/drivers/cxl/core/ras.c\n+++ b/drivers/cxl/core/ras.c\n@@ -253,38 +253,27 @@ bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n \treturn true;\n }\n \n-pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n-\t\t\t\t pci_channel_state_t state)\n+pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,\n+\t\t\t\t\tpci_channel_state_t state)\n {\n-\tstruct cxl_dev_state *cxlds = pci_get_drvdata(pdev);\n-\tstruct cxl_memdev *cxlmd = cxlds->cxlmd;\n-\tstruct device *dev = &cxlmd->dev;\n-\tbool ue;\n+\tstruct cxl_dport *dport;\n+\tstruct cxl_port *port __free(put_cxl_port) =\n+\t\tfind_cxl_port_by_dev(&pdev->dev, &dport);\n+\tstruct cxl_memdev *cxlmd;\n+\tstruct device *dev;\n \n-\tscoped_guard(device, dev) {\n-\t\tif (!dev->driver) {\n-\t\t\tdev_warn(&pdev->dev,\n-\t\t\t\t \"%s: memdev disabled, abort error handling\\n\",\n-\t\t\t\t dev_name(dev));\n-\t\t\treturn PCI_ERS_RESULT_DISCONNECT;\n-\t\t}\n+\tif (!port)\n+\t\treturn PCI_ERS_RESULT_DISCONNECT;\n \n-\t\t/*\n-\t\t * A frozen channel indicates an impending reset which is fatal to\n-\t\t * CXL.mem operation, and will likely crash the system. On the off\n-\t\t * chance the situation is recoverable dump the status of the RAS\n-\t\t * capability registers and bounce the active state of the memdev.\n-\t\t */\n-\t\tue = cxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n-\t\t\t\t cxlmd->endpoint->regs.ras);\n-\t}\n+\tcxlmd = to_cxl_memdev(port->uport_dev);\n+\tdev = &cxlmd->dev;\n \n \tswitch (state) {\n \tcase pci_channel_io_normal:\n-\t\tif (ue) {\n-\t\t\tdevice_release_driver(dev);\n-\t\t\treturn PCI_ERS_RESULT_NEED_RESET;\n-\t\t}\n+\t\t/*\n+\t\t * Non-fatal CXL protocol errors are handled asynchronously\n+\t\t * by the AER-CXL kfifo worker (cxl_proto_err_work_fn).\n+\t\t */\n \t\treturn PCI_ERS_RESULT_CAN_RECOVER;\n \tcase pci_channel_io_frozen:\n \t\tdev_warn(&pdev->dev,\n@@ -299,7 +288,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n \t}\n \treturn PCI_ERS_RESULT_NEED_RESET;\n }\n-EXPORT_SYMBOL_NS_GPL(cxl_error_detected, \"CXL\");\n+EXPORT_SYMBOL_NS_GPL(cxl_pci_error_detected, \"CXL\");\n \n static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port,\n \t\t\t\t struct cxl_dport *dport, int severity)\ndiff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h\nindex 06c46adcf0f6..8aeb80a4e573 100644\n--- a/drivers/cxl/cxlpci.h\n+++ b/drivers/cxl/cxlpci.h\n@@ -89,13 +89,13 @@ struct cxl_dev_state;\n void read_cdat_data(struct cxl_port *port);\n \n #ifdef CONFIG_CXL_RAS\n-pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n-\t\t\t\t pci_channel_state_t state);\n+pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,\n+\t\t\t\t\tpci_channel_state_t state);\n void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport);\n void devm_cxl_port_ras_setup(struct cxl_port *port);\n #else\n-static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n-\t\t\t\t\t\t pci_channel_state_t state)\n+static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,\n+\t\t\t\t\t\t pci_channel_state_t state)\n {\n \treturn PCI_ERS_RESULT_NONE;\n }\ndiff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c\nindex 5eb64ced0de5..6459f94f8fa8 100644\n--- a/drivers/cxl/pci.c\n+++ b/drivers/cxl/pci.c\n@@ -1000,8 +1000,8 @@ static void cxl_reset_done(struct pci_dev *pdev)\n \t}\n }\n \n-static const struct pci_error_handlers cxl_error_handlers = {\n-\t.error_detected\t= cxl_error_detected,\n+static const struct pci_error_handlers cxl_pci_error_handlers = {\n+\t.error_detected\t= cxl_pci_error_detected,\n \t.slot_reset\t= cxl_slot_reset,\n \t.resume\t\t= cxl_error_resume,\n \t.reset_done\t= cxl_reset_done,\n@@ -1011,7 +1011,7 @@ static struct pci_driver cxl_pci_driver = {\n \t.name\t\t\t= KBUILD_MODNAME,\n \t.id_table\t\t= cxl_mem_pci_tbl,\n \t.probe\t\t\t= cxl_pci_probe,\n-\t.err_handler\t\t= &cxl_error_handlers,\n+\t.err_handler\t\t= &cxl_pci_error_handlers,\n \t.dev_groups\t\t= cxl_rcd_groups,\n \t.driver\t= {\n \t\t.probe_type\t= PROBE_PREFER_ASYNCHRONOUS,\n", "prefixes": [ "v17", "09/11" ] }