[{"id":3687279,"web_url":"http://patchwork.ozlabs.org/comment/3687279/","msgid":"<0cda6505-a217-4c75-b3cb-51a8c396793c@intel.com>","list_archive_url":null,"date":"2026-05-06T17:43:02","subject":"Re: [PATCH v17 09/11] cxl: Update Endpoint AER uncorrectable handler","submitter":{"id":13225,"url":"http://patchwork.ozlabs.org/api/people/13225/","name":"Dave Jiang","email":"dave.jiang@intel.com"},"content":"On 5/5/26 10:30 AM, Terry Bowman wrote:\n> The CXL cxl_core driver now implements protocol RAS support. PCI\n> uncorrectable (UCE) protocol errors, however, continue to be reported via\n> the AER capability and must still be handled by a PCI error recovery callback.\n> UCE handling is required to provide direction for recovery.\n> \n> Replace the existing cxl_error_detected() callback in cxl/pci.c with a new\n> cxl_pci_error_detected() implementation that handles uncorrectable AER PCI\n> protocol errors.\n> \n> The handler decides solely based on the pci_channel_state_t parameter and\n> does not access PCIe AER capability registers from .error_detected, matching\n> the pattern used by other drivers including the NVMe and ixgbe drivers.\n> CXL.cachemem-corrupting protocol errors are routed separately through the\n> AER-CXL kfifo to cxl_handle_proto_error(), so cxl_pci does not need to\n> second-guess the AER core's classification.\n> \n> claude-opus-4.7 was used for research on PCI error state transitions and\n> requirements.\n> \n> Assisted-by: Claude:claude-opus-4.7\n> Signed-off-by: Terry Bowman \n> \n> ---\n> \n> Changes in v16->v17:\n> - Rename pci_error_handlers struct instance to cxl_pci_error_handlers to\n> avoid shadowing the struct type tag.\n> - Restore scoped_guard(device) and dev->driver check around AER read.\n> - NULL-check find_cxl_port_by_dev() before deref of port->uport_dev.\n> - Updated commit message. (Terry)\n> - Add scope cleanup for port variable in cxl_pci_error_detected() (Terry)\n> - Drop cxl_uncor_aer_present(), rely on AER state\n> \n> Changes in v15->v16:\n> - Update commit message (DaveJ)\n> - s/cxl_handle_aer()/cxl_uncor_aer_present()/g (Jonathan)\n> - cxl_uncor_aer_present(): Leave original result calculation based on\n> if a UCE is present and the provided state (Terry)\n> - Add call to pci_print_aer(). AER fails to log because is upstream\n> link (Terry)\n> \n> Changes in v14->v15:\n> - Update commit message and title. Added Bjorn's ack.\n> - Move CE and UCE handling logic here\n> \n> Changes in v13->v14:\n> - Add Dave Jiang's review-by\n> - Update commit message & headline (Bjorn)\n> - Refactor cxl_port_error_detected()/cxl_port_cor_error_detected() to\n> one line (Jonathan)\n> - Remove cxl_walk_port() (Dan)\n> - Remove cxl_pci_drv_bound(). Check for 'is_cxl' parent port is\n> sufficient (Dan)\n> - Remove device_lock_if()\n> - Combined CE and UCE here (Terry)\n> \n> Changes in v12->v13:\n> - Move get_pci_cxl_host_dev() and cxl_handle_proto_error() to Dequeue\n> patch (Terry)\n> - Remove EP case in cxl_get_ras_base(), not used. (Terry)\n> - Remove check for dport->dport_dev (Dave)\n> - Remove whitespace (Terry)\n> \n> Changes in v11->v12:\n> - Add call to cxl_pci_drv_bound() in cxl_handle_proto_error() and\n> pci_to_cxl_dev()\n> - Change cxl_error_detected() -> cxl_cor_error_detected()\n> - Remove NULL variable assignments\n> - Replace bus_find_device() with find_cxl_port_by_uport() for upstream\n> port searches.\n> \n> Changes in v10->v11:\n> - None\n> ---\n> drivers/cxl/core/ras.c | 43 ++++++++++++++++--------------------------\n> drivers/cxl/cxlpci.h | 8 ++++----\n> drivers/cxl/pci.c | 6 +++---\n> 3 files changed, 23 insertions(+), 34 deletions(-)\n> \n> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\n> index 5cc4087c2807..a98ce0f412ad 100644\n> --- a/drivers/cxl/core/ras.c\n> +++ b/drivers/cxl/core/ras.c\n> @@ -253,38 +253,27 @@ bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n> \treturn true;\n> }\n> \n> -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n> -\t\t\t\t pci_channel_state_t state)\n> +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,\n> +\t\t\t\t\tpci_channel_state_t state)\n> {\n> -\tstruct cxl_dev_state *cxlds = pci_get_drvdata(pdev);\n> -\tstruct cxl_memdev *cxlmd = cxlds->cxlmd;\n> -\tstruct device *dev = &cxlmd->dev;\n> -\tbool ue;\n> +\tstruct cxl_dport *dport;\n> +\tstruct cxl_port *port __free(put_cxl_port) =\n> +\t\tfind_cxl_port_by_dev(&pdev->dev, &dport);\n\nMove this to right before 'port' is being checked. It's ok to do inline var declaration with __free().\n\nDJ\n\n> +\tstruct cxl_memdev *cxlmd;\n> +\tstruct device *dev;\n> \n> -\tscoped_guard(device, dev) {\n> -\t\tif (!dev->driver) {\n> -\t\t\tdev_warn(&pdev->dev,\n> -\t\t\t\t \"%s: memdev disabled, abort error handling\\n\",\n> -\t\t\t\t dev_name(dev));\n> -\t\t\treturn PCI_ERS_RESULT_DISCONNECT;\n> -\t\t}\n> +\tif (!port)\n> +\t\treturn PCI_ERS_RESULT_DISCONNECT;\n> \n> -\t\t/*\n> -\t\t * A frozen channel indicates an impending reset which is fatal to\n> -\t\t * CXL.mem operation, and will likely crash the system. On the off\n> -\t\t * chance the situation is recoverable dump the status of the RAS\n> -\t\t * capability registers and bounce the active state of the memdev.\n> -\t\t */\n> -\t\tue = cxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n> -\t\t\t\t cxlmd->endpoint->regs.ras);\n> -\t}\n> +\tcxlmd = to_cxl_memdev(port->uport_dev);\n> +\tdev = &cxlmd->dev;\n> \n> \tswitch (state) {\n> \tcase pci_channel_io_normal:\n> -\t\tif (ue) {\n> -\t\t\tdevice_release_driver(dev);\n> -\t\t\treturn PCI_ERS_RESULT_NEED_RESET;\n> -\t\t}\n> +\t\t/*\n> +\t\t * Non-fatal CXL protocol errors are handled asynchronously\n> +\t\t * by the AER-CXL kfifo worker (cxl_proto_err_work_fn).\n> +\t\t */\n> \t\treturn PCI_ERS_RESULT_CAN_RECOVER;\n> \tcase pci_channel_io_frozen:\n> \t\tdev_warn(&pdev->dev,\n> @@ -299,7 +288,7 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n> \t}\n> \treturn PCI_ERS_RESULT_NEED_RESET;\n> }\n> -EXPORT_SYMBOL_NS_GPL(cxl_error_detected, \"CXL\");\n> +EXPORT_SYMBOL_NS_GPL(cxl_pci_error_detected, \"CXL\");\n> \n> static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port,\n> \t\t\t\t struct cxl_dport *dport, int severity)\n> diff --git a/drivers/cxl/cxlpci.h b/drivers/cxl/cxlpci.h\n> index 06c46adcf0f6..8aeb80a4e573 100644\n> --- a/drivers/cxl/cxlpci.h\n> +++ b/drivers/cxl/cxlpci.h\n> @@ -89,13 +89,13 @@ struct cxl_dev_state;\n> void read_cdat_data(struct cxl_port *port);\n> \n> #ifdef CONFIG_CXL_RAS\n> -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n> -\t\t\t\t pci_channel_state_t state);\n> +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,\n> +\t\t\t\t\tpci_channel_state_t state);\n> void devm_cxl_dport_rch_ras_setup(struct cxl_dport *dport);\n> void devm_cxl_port_ras_setup(struct cxl_port *port);\n> #else\n> -static inline pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n> -\t\t\t\t\t\t pci_channel_state_t state)\n> +static inline pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,\n> +\t\t\t\t\t\t pci_channel_state_t state)\n> {\n> \treturn PCI_ERS_RESULT_NONE;\n> }\n> diff --git a/drivers/cxl/pci.c b/drivers/cxl/pci.c\n> index 5eb64ced0de5..6459f94f8fa8 100644\n> --- a/drivers/cxl/pci.c\n> +++ b/drivers/cxl/pci.c\n> @@ -1000,8 +1000,8 @@ static void cxl_reset_done(struct pci_dev *pdev)\n> \t}\n> }\n> \n> -static const struct pci_error_handlers cxl_error_handlers = {\n> -\t.error_detected\t= cxl_error_detected,\n> +static const struct pci_error_handlers cxl_pci_error_handlers = {\n> +\t.error_detected\t= cxl_pci_error_detected,\n> \t.slot_reset\t= cxl_slot_reset,\n> \t.resume\t\t= cxl_error_resume,\n> \t.reset_done\t= cxl_reset_done,\n> @@ -1011,7 +1011,7 @@ static struct pci_driver cxl_pci_driver = {\n> \t.name\t\t\t= KBUILD_MODNAME,\n> \t.id_table\t\t= cxl_mem_pci_tbl,\n> \t.probe\t\t\t= cxl_pci_probe,\n> -\t.err_handler\t\t= &cxl_error_handlers,\n> +\t.err_handler\t\t= &cxl_pci_error_handlers,\n> \t.dev_groups\t\t= cxl_rcd_groups,\n> \t.driver\t= {\n> \t\t.probe_type\t= PROBE_PREFER_ASYNCHRONOUS,","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=fg54+LwJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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charset=UTF-8","Content-Transfer-Encoding":"7bit"}},{"id":3687985,"web_url":"http://patchwork.ozlabs.org/comment/3687985/","msgid":"<20260507192513.7d982f95@jic23-huawei>","list_archive_url":null,"date":"2026-05-07T18:25:13","subject":"Re: [PATCH v17 09/11] cxl: Update Endpoint AER uncorrectable\n handler","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Wed, 6 May 2026 10:43:02 -0700\nDave Jiang wrote:\n\n> On 5/5/26 10:30 AM, Terry Bowman wrote:\n> > The CXL cxl_core driver now implements protocol RAS support. PCI\n> > uncorrectable (UCE) protocol errors, however, continue to be reported via\n> > the AER capability and must still be handled by a PCI error recovery callback.\n> > UCE handling is required to provide direction for recovery.\n> > \n> > Replace the existing cxl_error_detected() callback in cxl/pci.c with a new\n> > cxl_pci_error_detected() implementation that handles uncorrectable AER PCI\n> > protocol errors.\n> > \n> > The handler decides solely based on the pci_channel_state_t parameter and\n> > does not access PCIe AER capability registers from .error_detected, matching\n> > the pattern used by other drivers including the NVMe and ixgbe drivers.\n> > CXL.cachemem-corrupting protocol errors are routed separately through the\n> > AER-CXL kfifo to cxl_handle_proto_error(), so cxl_pci does not need to\n> > second-guess the AER core's classification.\n> > \n> > claude-opus-4.7 was used for research on PCI error state transitions and\n> > requirements.\n> > \n> > Assisted-by: Claude:claude-opus-4.7\n> > Signed-off-by: Terry Bowman \n...\n\n> > ---\n> > drivers/cxl/core/ras.c | 43 ++++++++++++++++--------------------------\n> > drivers/cxl/cxlpci.h | 8 ++++----\n> > drivers/cxl/pci.c | 6 +++---\n> > 3 files changed, 23 insertions(+), 34 deletions(-)\n> > \n> > diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\n> > index 5cc4087c2807..a98ce0f412ad 100644\n> > --- a/drivers/cxl/core/ras.c\n> > +++ b/drivers/cxl/core/ras.c\n> > @@ -253,38 +253,27 @@ bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n> > \treturn true;\n> > }\n> > \n> > -pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n> > -\t\t\t\t pci_channel_state_t state)\n> > +pci_ers_result_t cxl_pci_error_detected(struct pci_dev *pdev,\n> > +\t\t\t\t\tpci_channel_state_t state)\n> > {\n> > -\tstruct cxl_dev_state *cxlds = pci_get_drvdata(pdev);\n> > -\tstruct cxl_memdev *cxlmd = cxlds->cxlmd;\n> > -\tstruct device *dev = &cxlmd->dev;\n> > -\tbool ue;\n> > +\tstruct cxl_dport *dport;\n> > +\tstruct cxl_port *port __free(put_cxl_port) =\n> > +\t\tfind_cxl_port_by_dev(&pdev->dev, &dport); \n> \n> Move this to right before 'port' is being checked. It's ok to do inline var declaration with __free().\n\nWith that done LGTM\nReviewed-by: Jonathan Cameron ","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=uTeu+dPS;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-54115-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"uTeu+dPS\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBLLX2F6Bz1yCg\n\tfor ; Fri, 08 May 2026 04:26:44 +1000 (AEST)","from smtp.subspace.kernel.org (conduit.subspace.kernel.org\n [100.90.174.1])\n\tby sea.lore.kernel.org (Postfix) with ESMTP id A1C28301ECE8\n\tfor ; Thu, 7 May 2026 18:25:28 +0000 (UTC)","from localhost.localdomain (localhost.localdomain [127.0.0.1])\n\tby smtp.subspace.kernel.org (Postfix) with ESMTP id 1442D45348D;\n\tThu, 7 May 2026 18:25:28 +0000 (UTC)","from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org\n [10.30.226.201])\n\t(using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby smtp.subspace.kernel.org (Postfix) with ESMTPS id E219A2D8399;\n\tThu, 7 May 2026 18:25:27 +0000 (UTC)","by smtp.kernel.org (Postfix) with ESMTPSA id 43ABDC2BCB2;\n\tThu, 7 May 2026 18:25:17 +0000 (UTC)"],"ARC-Seal":"i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116;\n\tt=1778178328; cv=none;\n b=U+L/uZ7FGyP32JhLd41p6xqVnnX7GhARUtrjrjOqxvhlOpxZ2Xunxtpz4MbcOm1FjSlT/glJP1oDlshKebdGNneImQCzkltJkLS//ds6xIa7CO/AzqzXPskkBU21BUEYUYlwA7DO90dvQUMxzAsfkmdFaBJNvvnW7Y1THVQ1ZJA=","ARC-Message-Signature":"i=1; a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778178328; c=relaxed/simple;\n\tbh=hd/cCq7/D5ttvLfjExtlud7dBiVFd4gFuaPymfWpbhc=;\n\th=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=NLs82ERCaONHa9brxEeYbXXCIksYzvm2soCI5KVzz2o97O/qXWo+A4ja1P8YtjmVPv47ioGj8DXWPeKTClJLVSqUu2kvhwQFptVaPeffDdBMNYooFAiaa73jnFQO3pDY5ULiSc3Bd9CJnqmYRI6GltQS13DUWcw1AGJ3Yie3J4Q=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=uTeu+dPS; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1778178327;\n\tbh=hd/cCq7/D5ttvLfjExtlud7dBiVFd4gFuaPymfWpbhc=;\n\th=Date:From:To:Cc:Subject:In-Reply-To:References:From;\n\tb=uTeu+dPSnCw/Qa2uCuZPT6RTVgVMKjUcFqVNAXdrl/EDls2tgC4QxAkTZeHi5tUS1\n\t QXet+iYJNbwq6/9xUpEWREexFSzLkj620wmYRLOTJf68717kM9W13+fv02iDjvRxpe\n\t xl0/rvm2nWzKwPEdFlVG3SyeIQr/62EO0VNPFch+lPsnU+KJYxEx4Efgl1rXxDOnO6\n\t IUqv0S3cxFGwpiFYjwFg00k+wQsV0APpTwv0yOPqvpiSOIIIqTz5BsVNsk7W5A02Hy\n\t QdVYCJxHn3A5vqaHc+it68M26IV8/f1j6A/wLMIjmIaLHHaFAmJ3sj5JTOiPnQpvpq\n\t rx6sDiwLppuVA==","Date":"Thu, 7 May 2026 19:25:13 +0100","From":"Jonathan Cameron ","To":"Dave Jiang ","Cc":"Terry Bowman , dave@stgolabs.net,\n alison.schofield@intel.com, djbw@kernel.org, bhelgaas@google.com,\n shiju.jose@huawei.com, ming.li@zohomail.com,\n Smita.KoralahalliChannabasappa@amd.com, rrichter@amd.com,\n dan.carpenter@linaro.org, PradeepVineshReddy.Kodamati@amd.com,\n lukas@wunner.de, Benjamin.Cheatham@amd.com,\n sathyanarayanan.kuppuswamy@linux.intel.com, vishal.l.verma@intel.com,\n alucerop@amd.com, ira.weiny@intel.com, corbet@lwn.net, rafael@kernel.org,\n xueshuai@linux.alibaba.com, linux-cxl@vger.kernel.org,\n linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n linux-acpi@vger.kernel.org, linux-doc@vger.kernel.org","Subject":"Re: [PATCH v17 09/11] cxl: Update Endpoint AER uncorrectable\n handler","Message-ID":"<20260507192513.7d982f95@jic23-huawei>","In-Reply-To":"<0cda6505-a217-4c75-b3cb-51a8c396793c@intel.com>","References":"<20260505173029.2718246-1-terry.bowman@amd.com>\n\t<20260505173029.2718246-10-terry.bowman@amd.com>\n\t<0cda6505-a217-4c75-b3cb-51a8c396793c@intel.com>","X-Mailer":"Claws Mail 4.4.0 (GTK 3.24.52; x86_64-pc-linux-gnu)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit"}}]