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GET /api/1.2/patches/2233122/?format=api
{ "id": 2233122, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2233122/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260505173029.2718246-3-terry.bowman@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260505173029.2718246-3-terry.bowman@amd.com>", "list_archive_url": null, "date": "2026-05-05T17:30:20", "name": "[v17,02/11] cxl/ras: Unify Endpoint and Port AER trace events", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "61dca51db7826407ea2ce2d4e37ae41b98674624", "submitter": { "id": 82124, "url": "http://patchwork.ozlabs.org/api/1.2/people/82124/?format=api", "name": "Bowman, Terry", "email": "Terry.Bowman@amd.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260505173029.2718246-3-terry.bowman@amd.com/mbox/", "series": [ { "id": 502875, "url": "http://patchwork.ozlabs.org/api/1.2/series/502875/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502875", "date": "2026-05-05T17:30:19", "name": "Enable CXL PCIe Port Protocol Error handling and logging", "version": 17, "mbox": "http://patchwork.ozlabs.org/series/502875/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2233122/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2233122/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-53766-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=2dn3qjz6;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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helo=satlexmb07.amd.com; pr=C", "From": "Terry Bowman <terry.bowman@amd.com>", "To": "<dave@stgolabs.net>, <jic23@kernel.org>, <dave.jiang@intel.com>,\n\t<alison.schofield@intel.com>, <djbw@kernel.org>, <bhelgaas@google.com>,\n\t<shiju.jose@huawei.com>, <ming.li@zohomail.com>,\n\t<Smita.KoralahalliChannabasappa@amd.com>, <rrichter@amd.com>,\n\t<dan.carpenter@linaro.org>, <PradeepVineshReddy.Kodamati@amd.com>,\n\t<lukas@wunner.de>, <Benjamin.Cheatham@amd.com>,\n\t<sathyanarayanan.kuppuswamy@linux.intel.com>, <vishal.l.verma@intel.com>,\n\t<alucerop@amd.com>, <ira.weiny@intel.com>, <corbet@lwn.net>,\n\t<rafael@kernel.org>, <xueshuai@linux.alibaba.com>,\n\t<linux-cxl@vger.kernel.org>", "CC": "<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<linux-acpi@vger.kernel.org>, <linux-doc@vger.kernel.org>,\n\t<terry.bowman@amd.com>", "Subject": "[PATCH v17 02/11] cxl/ras: Unify Endpoint and Port AER trace events", "Date": "Tue, 5 May 2026 12:30:20 -0500", "Message-ID": "<20260505173029.2718246-3-terry.bowman@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260505173029.2718246-1-terry.bowman@amd.com>", "References": "<20260505173029.2718246-1-terry.bowman@amd.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "7bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com\n (10.181.42.216)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM2PEPF00003FC2:EE_|IA1PR12MB6163:EE_", "X-MS-Office365-Filtering-Correlation-Id": "cec53833-f5ae-4d30-02a9-08deaacc16f2", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|1800799024|7416014|82310400026|376014|36860700016|921020|56012099003|22082099003|18002099003;", "X-Microsoft-Antispam-Message-Info": "\n\tbCqNK6LC6KJr2pYyPrwsCu+0INH3mboA0k6enqVwS2igFM3yp9616gGPJj/xUN2CsLb+LxoLwY7k24ugPnx4BwkNqwdytIDXBA59dVeUyoMZGZetFncxyZcHjJ5ing0AUadIuao8xQgk3BVVZCazNIJtxHXHDfhe2K/4j7Ioy/HzFrnqS1C/OhzrrRXvO+vGJepFUScSOKRFaD3RsZmGpADIaPK7vFcgr77y/YxtARXCF292E7E7bOPa/0I/iJZj39mcc4hDq9H9T/XqY9MiEv1yVWDcJkaYkukSMUZhz9EHxip48OUfkzhxAvU2cOjmZiqt6gxbeDLFLgFr+eUkQRsBN/kuu6E4ZXiMAvXDl83TgViSE323AyKwBgYz+nMfB3ORQ981UVO/E9lUdhBnGJ7iZbQX7UePo8ZeoxXN9I+2neC9fBx/Ie6F0cCi5O6yxeXLjq4h/eV05ScTRZn1IEHwBaEjIUDN+v1XGwBf+mNiSsFKz19OPnUXoKnwAKIwPgNFzIiK1v92qkwdYugWOyMWLo2Qok+Qw4RZkrHNgijVrQUNIumi7aJDAcmSbiqYLaYo45BIQdk72gl+WyyhPer88ZoyQO4Rll6YiyIiY9fkYaGFk8CPYwuJSBFytl3kr2L8Xu+2UBXw+518z4Gp12V12j2TiYbtvZsBpfUDkggib53beyQ3tTMuQASVG70u7j5Tco4HWyvhfCVatESqSq8VWJzi1pTBSeqHb5O8Hb6+fSVHlLRqUOh8tZFL1abcLzeWQ8yZWJYO4XiQPifToU6Sp9AxMUVsQ4XFp+vxFsA=", "X-Forefront-Antispam-Report": "\n\tCIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(7416014)(82310400026)(376014)(36860700016)(921020)(56012099003)(22082099003)(18002099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\tBq1A+/lhOolrjuL1v2uzzAJp3F+vh9xvxVGBC3A2SDnhXf6gLwVb4hPB3mhYsWw6DrefBShoD1pLVIu6cRjJFBpvmnkyjO+53ex2qYtiCr9Njq4LvBZHyAORiZjJGd/Zfwqh1+m0MX8omCSFxt78wezc0Q5bTut6LyoLvxGPCAiYPzr5Y8L1tyFzWvZE8UvYTDTMkRInJSnPGKGLdWVDtIGJq8+mKSeeNMh32Q5TqKPZfEPtEF8YeVMmgaRHrTbcbcRyX564qaPtKEgYmMMmLdS27oqN1ZKslPXRhOK8WFuz4WmTSyGcMtbC09n5Jad7TOEGlc+aH9Lssy0jpt9i0ogS/qY+9UTNaCIKstN/qfOAaV18HXQO2j2M0IX41AkQhgp+N51Dho6Cl5AaMVVJYedflG/ew4r9YVn1Ee8InLbG1mAVvHMcZxw1JOgCm5cK", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2026 17:31:06.7391\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n cec53833-f5ae-4d30-02a9-08deaacc16f2", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDM2PEPF00003FC2.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA1PR12MB6163" }, "content": "From: Dan Williams <djbw@kernel.org>\n\nCXL protocol error logging uses two parallel sets of trace events. The\ncxl_port_aer_correctable_error() and cxl_port_aer_uncorrectable_error()\nevents are used by CPER for CXL Port devices. The cxl_aer_correctable_error()\nand cxl_aer_uncorrectable_error() events are used for CXL Endpoints. Update\nthe trace routines to use the latter for all CXL devices on both the CPER\nand native AER paths.\n\nGeneralize cxl_aer_correctable_error()/cxl_aer_uncorrectable_error to\ntake a struct device * and a u64 serial argument supplied by the caller.\ncxl_handle_ras() and cxl_handle_cor_ras() gain the new u64 serial parameter,\nsourced from pci_get_dsn().\n\nThe CPER path keeps its existing Port-vs-Endpoint dispatch and passes the\nnew arguments to the unified trace events. The CPER path will be folded\ntogether in a following patch.\n\nRemove the now-unused cxl_port_aer_correctable_error() and\ncxl_port_aer_uncorrectable_error().\n\n**WARNING: ABI BREAK**\nRename the trace event field \"memdev\" to \"device\" so all CXL device types\n(Ports and Endpoints) can be reported under a common field name. Note this\nis an ABI break for userspace tools that key off the old \"memdev\" field.\nSpecifically, rasdaemon's ras-cxl-handler.c looks up \"memdev\" and bails on\nNULL, so an unmodified rasdaemon will drop every CXL CE/UCE event once this\nkernel ships. A rasdaemon update is needed in a separate series.\n\nThe need for the field rename was discussed in v16 review [1].\n\nAlso, for CXL Upstream Switch Port (USP) and Endpoint (EP) fatal UCE,\nthe cxl_aer_uncorrectable_error trace event is not emitted. The AER core\nonly retrieves PCI_ERR_UNCOR_STATUS for Root Ports, RCECs, and Downstream\nPorts, or for non-fatal severities. PCI config reads to the source device\nare expected to fail otherwise, so the AER core never reads the status\nword, is_cxl_error() does not classify the event as CXL, and the AER path\nhandles it instead. In this case the AER handler consumes the event and\nlogs it as an AER error without calling the CXL RAS handlers or trace\nlogging.\n\nBefore this patch, Endpoint and Port devices emitted different events:\n\n # Endpoint (cxl_aer_*):\n cxl_aer_correctable_error: memdev=mem0 host=0000:0c:00.0 serial=0: status: 'CRC Threshold Hit'\n cxl_aer_uncorrectable_error: memdev=mem0 host=0000:0c:00.0 serial=0: status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n\n # Port (cxl_port_aer_*, no serial field):\n cxl_port_aer_correctable_error: device=0000:0c:00.0 host=pci0000:0c status='CRC Threshold Hit'\n cxl_port_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n\nAfter this patch, all CXL devices emit the unified cxl_aer_* events\nwith the same field layout:\n\n cxl_aer_correctable_error: device=0000:0c:00.0 host=pci0000:0c serial=0 status: 'CRC Threshold Hit'\n cxl_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c serial=0 status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n\n[1] https://lore.kernel.org/linux-cxl/69cb2d5ba3111_178904100b7@dwillia2-mobl4.notmuch/\n\nCo-developed-by: Terry Bowman <terry.bowman@amd.com>\nSigned-off-by: Terry Bowman <terry.bowman@amd.com>\nSigned-off-by: Dan Williams <djbw@kernel.org>\n\n---\n\nChanges in v16->v17:\n- Replace cxlds->serial with pci_get_dsn()\n- Change 'memdev' to 'device' (Dan)\n- Updated Commit message\n\nChanges in v15->v16:\n- Add Dan's review-by\n- Incorporate Dan's comment into commit message:\n\"Add the serial number at the end to preserve compatibility with\nlibtraceevent parsing of the parameters.\"\n\nChanges in v14->v15:\n- Update commit message.\n- Moved cxl_handle_ras/cxl_handle_cor_ras() changes to future patch (terry)\n\nChanges in v13->v14:\n- Update commit headline (Bjorn)\n\nChanges in v12->v13:\n- Added Dave Jiang's review-by\n\nChanges in v11 -> v12:\n- Correct parameters to call trace_cxl_aer_correctable_error()\n- Add reviewed-by for Jonathan and Shiju\n\nChanges in v10->v11:\n- Updated CE and UCE trace routines to maintain consistent TP_Struct ABI\nand unchanged TP_printk() logging.\n---\n drivers/cxl/core/core.h | 11 ++++--\n drivers/cxl/core/ras.c | 39 +++++++++++--------\n drivers/cxl/core/ras_rch.c | 6 ++-\n drivers/cxl/core/trace.h | 76 ++++++++------------------------------\n 4 files changed, 49 insertions(+), 83 deletions(-)", "diff": "diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h\nindex 82ca3a476708..132ac9c1ebf4 100644\n--- a/drivers/cxl/core/core.h\n+++ b/drivers/cxl/core/core.h\n@@ -183,8 +183,9 @@ static inline struct device *dport_to_host(struct cxl_dport *dport)\n #ifdef CONFIG_CXL_RAS\n int cxl_ras_init(void);\n void cxl_ras_exit(void);\n-bool cxl_handle_ras(struct device *dev, void __iomem *ras_base);\n-void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base);\n+bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base);\n+void cxl_handle_cor_ras(struct device *dev, u64 serial,\n+\t\t\tvoid __iomem *ras_base);\n void cxl_dport_map_rch_aer(struct cxl_dport *dport);\n void cxl_disable_rch_root_ints(struct cxl_dport *dport);\n void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds);\n@@ -195,11 +196,13 @@ static inline int cxl_ras_init(void)\n \treturn 0;\n }\n static inline void cxl_ras_exit(void) { }\n-static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n+static inline bool cxl_handle_ras(struct device *dev, u64 serial,\n+\t\t\t\t void __iomem *ras_base)\n {\n \treturn false;\n }\n-static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { }\n+static inline void cxl_handle_cor_ras(struct device *dev, u64 serial,\n+\t\t\t\t void __iomem *ras_base) { }\n static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }\n static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }\n static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { }\ndiff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\nindex 006c6ffc2f56..d7081caaf5d3 100644\n--- a/drivers/cxl/core/ras.c\n+++ b/drivers/cxl/core/ras.c\n@@ -13,7 +13,7 @@ static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev,\n {\n \tu32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n \n-\ttrace_cxl_port_aer_correctable_error(&pdev->dev, status);\n+\ttrace_cxl_aer_correctable_error(&pdev->dev, status, pci_get_dsn(pdev));\n }\n \n static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n@@ -28,20 +28,24 @@ static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n \telse\n \t\tfe = status;\n \n-\ttrace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe,\n-\t\t\t\t\t ras_cap.header_log);\n+\ttrace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe,\n+\t\t\t\t\t ras_cap.header_log,\n+\t\t\t\t\t pci_get_dsn(pdev));\n }\n \n-static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd,\n+static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev,\n+\t\t\t\t\t struct cxl_memdev *cxlmd,\n \t\t\t\t\t struct cxl_ras_capability_regs ras_cap)\n {\n \tu32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n \n-\ttrace_cxl_aer_correctable_error(cxlmd, status);\n+\ttrace_cxl_aer_correctable_error(&cxlmd->dev, status,\n+\t\t\t\t\tpci_get_dsn(pdev));\n }\n \n static void\n-cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,\n+cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev,\n+\t\t\t struct cxl_memdev *cxlmd,\n \t\t\t struct cxl_ras_capability_regs ras_cap)\n {\n \tu32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;\n@@ -53,8 +57,9 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,\n \telse\n \t\tfe = status;\n \n-\ttrace_cxl_aer_uncorrectable_error(cxlmd, status, fe,\n-\t\t\t\t\t ras_cap.header_log);\n+\ttrace_cxl_aer_uncorrectable_error(&cxlmd->dev, status, fe,\n+\t\t\t\t\t ras_cap.header_log,\n+\t\t\t\t\t pci_get_dsn(pdev));\n }\n \n static int match_memdev_by_parent(struct device *dev, const void *uport)\n@@ -101,9 +106,9 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n \n \tcxlmd = to_cxl_memdev(mem_dev);\n \tif (data->severity == AER_CORRECTABLE)\n-\t\tcxl_cper_trace_corr_prot_err(cxlmd, data->ras_cap);\n+\t\tcxl_cper_trace_corr_prot_err(pdev, cxlmd, data->ras_cap);\n \telse\n-\t\tcxl_cper_trace_uncorr_prot_err(cxlmd, data->ras_cap);\n+\t\tcxl_cper_trace_uncorr_prot_err(pdev, cxlmd, data->ras_cap);\n }\n EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err);\n \n@@ -183,7 +188,7 @@ void devm_cxl_port_ras_setup(struct cxl_port *port)\n }\n EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, \"CXL\");\n \n-void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)\n+void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n {\n \tvoid __iomem *addr;\n \tu32 status;\n@@ -195,7 +200,7 @@ void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)\n \tstatus = readl(addr);\n \tif (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {\n \t\twritel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);\n-\t\ttrace_cxl_aer_correctable_error(to_cxl_memdev(dev), status);\n+\t\ttrace_cxl_aer_correctable_error(dev, status, serial);\n \t}\n }\n \n@@ -220,7 +225,7 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)\n * Log the state of the RAS status registers and prepare them to log the\n * next error status. Return 1 if reset needed.\n */\n-bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n+bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n {\n \tu32 hl[CXL_HEADERLOG_SIZE_U32];\n \tvoid __iomem *addr;\n@@ -247,7 +252,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n \t}\n \n \theader_log_copy(ras_base, hl);\n-\ttrace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl);\n+\ttrace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial);\n \twritel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);\n \n \treturn true;\n@@ -270,7 +275,8 @@ void cxl_cor_error_detected(struct pci_dev *pdev)\n \t\tif (cxlds->rcd)\n \t\t\tcxl_handle_rdport_errors(cxlds);\n \n-\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);\n+\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n+\t\t\t\t cxlmd->endpoint->regs.ras);\n \t}\n }\n EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, \"CXL\");\n@@ -299,7 +305,8 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n \t\t * chance the situation is recoverable dump the status of the RAS\n \t\t * capability registers and bounce the active state of the memdev.\n \t\t */\n-\t\tue = cxl_handle_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);\n+\t\tue = cxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n+\t\t\t\t cxlmd->endpoint->regs.ras);\n \t}\n \n \tswitch (state) {\ndiff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c\nindex 0a8b3b9b6388..61835fbafc0f 100644\n--- a/drivers/cxl/core/ras_rch.c\n+++ b/drivers/cxl/core/ras_rch.c\n@@ -115,7 +115,9 @@ void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)\n \n \tpci_print_aer(pdev, severity, &aer_regs);\n \tif (severity == AER_CORRECTABLE)\n-\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras);\n+\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n+\t\t\t\t dport->regs.ras);\n \telse\n-\t\tcxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras);\n+\t\tcxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n+\t\t\t dport->regs.ras);\n }\ndiff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h\nindex a972e4ef1936..6f3957b3c3af 100644\n--- a/drivers/cxl/core/trace.h\n+++ b/drivers/cxl/core/trace.h\n@@ -48,49 +48,22 @@\n \t{ CXL_RAS_UC_IDE_RX_ERR, \"IDE Rx Error\" }\t\t\t \\\n )\n \n-TRACE_EVENT(cxl_port_aer_uncorrectable_error,\n-\tTP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),\n-\tTP_ARGS(dev, status, fe, hl),\n+TRACE_EVENT(cxl_aer_uncorrectable_error,\n+\tTP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl,\n+\t\t u64 serial),\n+\tTP_ARGS(dev, status, fe, hl, serial),\n \tTP_STRUCT__entry(\n \t\t__string(device, dev_name(dev))\n \t\t__string(host, dev_name(dev->parent))\n-\t\t__field(u32, status)\n-\t\t__field(u32, first_error)\n-\t\t__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)\n-\t),\n-\tTP_fast_assign(\n-\t\t__assign_str(device);\n-\t\t__assign_str(host);\n-\t\t__entry->status = status;\n-\t\t__entry->first_error = fe;\n-\t\t/*\n-\t\t * Embed the 512B headerlog data for user app retrieval and\n-\t\t * parsing, but no need to print this in the trace buffer.\n-\t\t */\n-\t\tmemcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n-\t),\n-\tTP_printk(\"device=%s host=%s status: '%s' first_error: '%s'\",\n-\t\t __get_str(device), __get_str(host),\n-\t\t show_uc_errs(__entry->status),\n-\t\t show_uc_errs(__entry->first_error)\n-\t)\n-);\n-\n-TRACE_EVENT(cxl_aer_uncorrectable_error,\n-\tTP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl),\n-\tTP_ARGS(cxlmd, status, fe, hl),\n-\tTP_STRUCT__entry(\n-\t\t__string(memdev, dev_name(&cxlmd->dev))\n-\t\t__string(host, dev_name(cxlmd->dev.parent))\n \t\t__field(u64, serial)\n \t\t__field(u32, status)\n \t\t__field(u32, first_error)\n \t\t__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)\n \t),\n \tTP_fast_assign(\n-\t\t__assign_str(memdev);\n+\t\t__assign_str(device);\n \t\t__assign_str(host);\n-\t\t__entry->serial = cxlmd->cxlds->serial;\n+\t\t__entry->serial = serial;\n \t\t__entry->status = status;\n \t\t__entry->first_error = fe;\n \t\t/*\n@@ -99,8 +72,8 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,\n \t\t */\n \t\tmemcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n \t),\n-\tTP_printk(\"memdev=%s host=%s serial=%lld: status: '%s' first_error: '%s'\",\n-\t\t __get_str(memdev), __get_str(host), __entry->serial,\n+\tTP_printk(\"device=%s host=%s serial=%lld status: '%s' first_error: '%s'\",\n+\t\t __get_str(device), __get_str(host), __entry->serial,\n \t\t show_uc_errs(__entry->status),\n \t\t show_uc_errs(__entry->first_error)\n \t)\n@@ -124,42 +97,23 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,\n \t{ CXL_RAS_CE_PHYS_LAYER_ERR, \"Received Error From Physical Layer\" }\t\\\n )\n \n-TRACE_EVENT(cxl_port_aer_correctable_error,\n-\tTP_PROTO(struct device *dev, u32 status),\n-\tTP_ARGS(dev, status),\n+TRACE_EVENT(cxl_aer_correctable_error,\n+\tTP_PROTO(const struct device *dev, u32 status, u64 serial),\n+\tTP_ARGS(dev, status, serial),\n \tTP_STRUCT__entry(\n \t\t__string(device, dev_name(dev))\n \t\t__string(host, dev_name(dev->parent))\n-\t\t__field(u32, status)\n-\t),\n-\tTP_fast_assign(\n-\t\t__assign_str(device);\n-\t\t__assign_str(host);\n-\t\t__entry->status = status;\n-\t),\n-\tTP_printk(\"device=%s host=%s status='%s'\",\n-\t\t __get_str(device), __get_str(host),\n-\t\t show_ce_errs(__entry->status)\n-\t)\n-);\n-\n-TRACE_EVENT(cxl_aer_correctable_error,\n-\tTP_PROTO(const struct cxl_memdev *cxlmd, u32 status),\n-\tTP_ARGS(cxlmd, status),\n-\tTP_STRUCT__entry(\n-\t\t__string(memdev, dev_name(&cxlmd->dev))\n-\t\t__string(host, dev_name(cxlmd->dev.parent))\n \t\t__field(u64, serial)\n \t\t__field(u32, status)\n \t),\n \tTP_fast_assign(\n-\t\t__assign_str(memdev);\n+\t\t__assign_str(device);\n \t\t__assign_str(host);\n-\t\t__entry->serial = cxlmd->cxlds->serial;\n+\t\t__entry->serial = serial;\n \t\t__entry->status = status;\n \t),\n-\tTP_printk(\"memdev=%s host=%s serial=%lld: status: '%s'\",\n-\t\t __get_str(memdev), __get_str(host), __entry->serial,\n+\tTP_printk(\"device=%s host=%s serial=%lld status: '%s'\",\n+\t\t __get_str(device), __get_str(host), __entry->serial,\n \t\t show_ce_errs(__entry->status)\n \t)\n );\n", "prefixes": [ "v17", "02/11" ] }