[{"id":3686701,"web_url":"http://patchwork.ozlabs.org/comment/3686701/","msgid":"<20260505210753.B9B8FC2BCB4@smtp.kernel.org>","list_archive_url":null,"date":"2026-05-05T21:07:53","subject":"Re: [PATCH v17 02/11] cxl/ras: Unify Endpoint and Port AER trace\n events","submitter":{"id":93311,"url":"http://patchwork.ozlabs.org/api/people/93311/","name":null,"email":"sashiko-bot@kernel.org"},"content":"Thank you for your contribution! Sashiko AI review found 4 potential issue(s) to consider:\n- [Critical] ABI breakage for user-space RAS monitoring tools.\n- [Critical] Massive kernel stack out-of-bounds read (Information Leak) in trace_cxl_aer_uncorrectable_error.\n- [High] Unconditional PCI configuration space reads via pci_get_dsn() on potentially frozen links.\n- [High] Out-of-bounds MMIO read in header_log_copy() causing potential system crash.\n--\n\ncommit 7ac043ff49acf52a4133043e3ef651a4e11ba73f\nAuthor: Dan Williams \n\ncxl/ras: Unify Endpoint and Port AER trace events\n\nThis commit unifies the trace events for CXL Endpoint and Port devices on\nboth the CPER and native AER paths. It generalizes the correctable and\nuncorrectable error events to use a common device and serial number format.\nIt also renames the memdev field to device to support all CXL device types.\n\nLink: https://lore.kernel.org/linux-cxl/69cb2d5ba3111_178904100b7@dwillia2-mobl4.notmuch/\n\n> **WARNING: ABI BREAK**\n> Rename the trace event field \"memdev\" to \"device\" so all CXL device types\n> (Ports and Endpoints) can be reported under a common field name. Note this\n> is an ABI break for userspace tools that key off the old \"memdev\" field.\n> Specifically, rasdaemon's ras-cxl-handler.c looks up \"memdev\" and bails on\n> NULL, so an unmodified rasdaemon will drop every CXL CE/UCE event once this\n> kernel ships. A rasdaemon update is needed in a separate series.\n\nDoes renaming this trace event field violate the stable ABI policy for\ntrace events?\n\nSince unmodified system monitoring utilities like rasdaemon will drop\nthese memory errors after this change, should a backward-compatible approach\nbe used, such as retaining the memdev field or adding a new event without\ndeleting the old one?\n\n> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\n> index 006c6ffc2f567..d7081caaf5d3f 100644\n> --- a/drivers/cxl/core/ras.c\n> +++ b/drivers/cxl/core/ras.c\n> @@ -28,20 +28,24 @@ static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n> \telse\n> \t\tfe = status;\n> \n> -\ttrace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe,\n> -\t\t\t\t\t ras_cap.header_log);\n> +\ttrace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe,\n> +\t\t\t\t\t ras_cap.header_log,\n> +\t\t\t\t\t pci_get_dsn(pdev));\n> }\n\nCan passing ras_cap.header_log here cause an out-of-bounds stack read?\n\nThe ras_cap.header_log field is an array of 16 u32 elements (64 bytes).\nHowever, inside the trace_cxl_aer_uncorrectable_error() fast assign block,\nit copies CXL_HEADERLOG_SIZE (512 bytes):\n\n\tTP_fast_assign(\n\t\t...\n\t\tmemcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n\t)\n\nWill this read 448 bytes past the end of the header_log array and leak\nadjacent uninitialized kernel stack data into the trace ring buffer, making\nit accessible to user-space?\n\nAlso, can calling pci_get_dsn() here cause issues if the PCIe link is in a\nfrozen state?\n\nSince pci_get_dsn() performs live PCI config space reads, executing it on a\ndisconnected or frozen device could result in system hangs, extended timeouts,\nor Unsupported Request completions.\n\nFurthermore, since pci_get_dsn() is passed as an argument to the trace\nwrapper, won't the config space read execute unconditionally on every\nerror even if tracing is disabled?\n\n[ ... ]\n\n> @@ -247,7 +252,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n> \t}\n> \n> \theader_log_copy(ras_base, hl);\n> -\ttrace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl);\n> +\ttrace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial);\n> \twritel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);\n\nCan the call to header_log_copy() just above this trace event cause an\nout-of-bounds MMIO read?\n\nThe header_log_copy() function iterates 128 times to read 512 bytes from\nthe MMIO address:\n\nstatic void header_log_copy(void __iomem *ras_base, u32 *log)\n{\n\t...\n\tint i, log_u32_size = CXL_HEADERLOG_SIZE / sizeof(u32);\n\n\taddr = ras_base + CXL_RAS_HEADER_LOG_OFFSET;\n\tlog_addr = log;\n\n\tfor (i = 0; i < log_u32_size; i++) {\n\t\t*log_addr = readl(addr);\n\t\t...\n}\n\nHowever, during component probe, the CXL RAS capability block is mapped\nwith a length of CXL_RAS_CAPABILITY_LENGTH, which is only 88 bytes.\n\nCould attempting to read 512 bytes from an 88-byte MMIO mapping send PCIe\nmemory reads to unintended device offsets, potentially triggering\nMaster Aborts, Unsupported Requests, or unhandled page faults?\n\n[ ... ]\n\n> @@ -299,7 +305,8 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n> \t\t * chance the situation is recoverable dump the status of the RAS\n> \t\t * capability registers and bounce the active state of the memdev.\n> \t\t */\n> -\t\tue = cxl_handle_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);\n> +\t\tue = cxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n> +\t\t\t\t cxlmd->endpoint->regs.ras);\n> \t}\n\nIn cxl_error_detected(), if the PCIe link is in a frozen state, will the\ncall to pci_get_dsn() fail?\n\nBecause pci_get_dsn() performs live PCI config space reads, calling it\nwhen the channel state is pci_channel_io_frozen could cause system hangs\nor Unsupported Request completions.\n\nWill this vulnerability persist even if subsequent patches in the series\n(like \"cxl: Update Endpoint AER uncorrectable handler\") refactor the error\nflow into a workqueue, since the pci_get_dsn() call remains on the\nfatal error path?","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=q1k08Uy6;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1778015273;\n\tbh=Mu5QqxyqVGswjgV1q0Kxf4rbENVMtQfqfy3dr4PFfUc=;\n\th=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date:From;\n\tb=q1k08Uy6PnaulxxSgI5Jjsrq8tiK52wYGSuO51FV7x8VJ6q7+ZRet4n6n8pDDf8lI\n\t nMUiqalG5eKsB68qj9ZI8Fgg4GZjJ595WihDA9PCUobobPDL6bv/h4PEdE6bxm+PoE\n\t wczCUvClfvWJ7mvGBJhRSvUhLZ3srpFgpYlhvUN99kwoDIvImKXVjHgt8cojaBx5q+\n\t lw31pjS3/Tao34So19feGKblT7F+PhKrzCosicSVYzilwrHzs6Deu2SpMZtZg+wjyc\n\t YDkjjw8h5RCzSuCiokS5M3LpW2jl7FC6444rWp0k7TuQYn3wmd+QvnKWyIk2jOqbFI\n\t heEnMxjj+Cffw==","From":"sashiko-bot@kernel.org","Subject":"Re: [PATCH v17 02/11] cxl/ras: Unify Endpoint and Port AER trace\n events","Reply-To":"sashiko@lists.linux.dev","To":"\"Terry Bowman\" ","Cc":"linux-pci@vger.kernel.org","In-Reply-To":"<20260505173029.2718246-3-terry.bowman@amd.com>","References":"<20260505173029.2718246-3-terry.bowman@amd.com>","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"quoted-printable","Date":"Tue, 05 May 2026 21:07:53 +0000","Message-Id":"<20260505210753.B9B8FC2BCB4@smtp.kernel.org>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""}},{"id":3686729,"web_url":"http://patchwork.ozlabs.org/comment/3686729/","msgid":"<618748f8-ad14-42ea-8694-0c1bc5b95c54@intel.com>","list_archive_url":null,"date":"2026-05-05T21:46:55","subject":"Re: [PATCH v17 02/11] cxl/ras: Unify Endpoint and Port AER trace\n events","submitter":{"id":13225,"url":"http://patchwork.ozlabs.org/api/people/13225/","name":"Dave Jiang","email":"dave.jiang@intel.com"},"content":"On 5/5/26 10:30 AM, Terry Bowman wrote:\n> From: Dan Williams \n> \n> CXL protocol error logging uses two parallel sets of trace events. The\n> cxl_port_aer_correctable_error() and cxl_port_aer_uncorrectable_error()\n> events are used by CPER for CXL Port devices. The cxl_aer_correctable_error()\n> and cxl_aer_uncorrectable_error() events are used for CXL Endpoints. Update\n> the trace routines to use the latter for all CXL devices on both the CPER\n> and native AER paths.\n> \n> Generalize cxl_aer_correctable_error()/cxl_aer_uncorrectable_error to\n> take a struct device * and a u64 serial argument supplied by the caller.\n> cxl_handle_ras() and cxl_handle_cor_ras() gain the new u64 serial parameter,\n> sourced from pci_get_dsn().\n> \n> The CPER path keeps its existing Port-vs-Endpoint dispatch and passes the\n> new arguments to the unified trace events. The CPER path will be folded\n> together in a following patch.\n> \n> Remove the now-unused cxl_port_aer_correctable_error() and\n> cxl_port_aer_uncorrectable_error().\n> \n> **WARNING: ABI BREAK**\n> Rename the trace event field \"memdev\" to \"device\" so all CXL device types\n> (Ports and Endpoints) can be reported under a common field name. Note this\n> is an ABI break for userspace tools that key off the old \"memdev\" field.\n> Specifically, rasdaemon's ras-cxl-handler.c looks up \"memdev\" and bails on\n> NULL, so an unmodified rasdaemon will drop every CXL CE/UCE event once this\n> kernel ships. A rasdaemon update is needed in a separate series.\n> \n> The need for the field rename was discussed in v16 review [1].\n> \n> Also, for CXL Upstream Switch Port (USP) and Endpoint (EP) fatal UCE,\n> the cxl_aer_uncorrectable_error trace event is not emitted. The AER core\n> only retrieves PCI_ERR_UNCOR_STATUS for Root Ports, RCECs, and Downstream\n> Ports, or for non-fatal severities. PCI config reads to the source device\n> are expected to fail otherwise, so the AER core never reads the status\n> word, is_cxl_error() does not classify the event as CXL, and the AER path\n> handles it instead. In this case the AER handler consumes the event and\n> logs it as an AER error without calling the CXL RAS handlers or trace\n> logging.\n> \n> Before this patch, Endpoint and Port devices emitted different events:\n> \n> # Endpoint (cxl_aer_*):\n> cxl_aer_correctable_error: memdev=mem0 host=0000:0c:00.0 serial=0: status: 'CRC Threshold Hit'\n> cxl_aer_uncorrectable_error: memdev=mem0 host=0000:0c:00.0 serial=0: status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n> \n> # Port (cxl_port_aer_*, no serial field):\n> cxl_port_aer_correctable_error: device=0000:0c:00.0 host=pci0000:0c status='CRC Threshold Hit'\n> cxl_port_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n> \n> After this patch, all CXL devices emit the unified cxl_aer_* events\n> with the same field layout:\n> \n> cxl_aer_correctable_error: device=0000:0c:00.0 host=pci0000:0c serial=0 status: 'CRC Threshold Hit'\n> cxl_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c serial=0 status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n> \n> [1] https://lore.kernel.org/linux-cxl/69cb2d5ba3111_178904100b7@dwillia2-mobl4.notmuch/\n> \n> Co-developed-by: Terry Bowman \n> Signed-off-by: Terry Bowman \n> Signed-off-by: Dan Williams \n\nReviewed-by: Dave Jiang \n\n\n> \n> ---\n> \n> Changes in v16->v17:\n> - Replace cxlds->serial with pci_get_dsn()\n> - Change 'memdev' to 'device' (Dan)\n> - Updated Commit message\n> \n> Changes in v15->v16:\n> - Add Dan's review-by\n> - Incorporate Dan's comment into commit message:\n> \"Add the serial number at the end to preserve compatibility with\n> libtraceevent parsing of the parameters.\"\n> \n> Changes in v14->v15:\n> - Update commit message.\n> - Moved cxl_handle_ras/cxl_handle_cor_ras() changes to future patch (terry)\n> \n> Changes in v13->v14:\n> - Update commit headline (Bjorn)\n> \n> Changes in v12->v13:\n> - Added Dave Jiang's review-by\n> \n> Changes in v11 -> v12:\n> - Correct parameters to call trace_cxl_aer_correctable_error()\n> - Add reviewed-by for Jonathan and Shiju\n> \n> Changes in v10->v11:\n> - Updated CE and UCE trace routines to maintain consistent TP_Struct ABI\n> and unchanged TP_printk() logging.\n> ---\n> drivers/cxl/core/core.h | 11 ++++--\n> drivers/cxl/core/ras.c | 39 +++++++++++--------\n> drivers/cxl/core/ras_rch.c | 6 ++-\n> drivers/cxl/core/trace.h | 76 ++++++++------------------------------\n> 4 files changed, 49 insertions(+), 83 deletions(-)\n> \n> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h\n> index 82ca3a476708..132ac9c1ebf4 100644\n> --- a/drivers/cxl/core/core.h\n> +++ b/drivers/cxl/core/core.h\n> @@ -183,8 +183,9 @@ static inline struct device *dport_to_host(struct cxl_dport *dport)\n> #ifdef CONFIG_CXL_RAS\n> int cxl_ras_init(void);\n> void cxl_ras_exit(void);\n> -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base);\n> -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base);\n> +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base);\n> +void cxl_handle_cor_ras(struct device *dev, u64 serial,\n> +\t\t\tvoid __iomem *ras_base);\n> void cxl_dport_map_rch_aer(struct cxl_dport *dport);\n> void cxl_disable_rch_root_ints(struct cxl_dport *dport);\n> void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds);\n> @@ -195,11 +196,13 @@ static inline int cxl_ras_init(void)\n> \treturn 0;\n> }\n> static inline void cxl_ras_exit(void) { }\n> -static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n> +static inline bool cxl_handle_ras(struct device *dev, u64 serial,\n> +\t\t\t\t void __iomem *ras_base)\n> {\n> \treturn false;\n> }\n> -static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { }\n> +static inline void cxl_handle_cor_ras(struct device *dev, u64 serial,\n> +\t\t\t\t void __iomem *ras_base) { }\n> static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }\n> static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }\n> static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { }\n> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\n> index 006c6ffc2f56..d7081caaf5d3 100644\n> --- a/drivers/cxl/core/ras.c\n> +++ b/drivers/cxl/core/ras.c\n> @@ -13,7 +13,7 @@ static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev,\n> {\n> \tu32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n> \n> -\ttrace_cxl_port_aer_correctable_error(&pdev->dev, status);\n> +\ttrace_cxl_aer_correctable_error(&pdev->dev, status, pci_get_dsn(pdev));\n> }\n> \n> static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n> @@ -28,20 +28,24 @@ static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n> \telse\n> \t\tfe = status;\n> \n> -\ttrace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe,\n> -\t\t\t\t\t ras_cap.header_log);\n> +\ttrace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe,\n> +\t\t\t\t\t ras_cap.header_log,\n> +\t\t\t\t\t pci_get_dsn(pdev));\n> }\n> \n> -static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd,\n> +static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev,\n> +\t\t\t\t\t struct cxl_memdev *cxlmd,\n> \t\t\t\t\t struct cxl_ras_capability_regs ras_cap)\n> {\n> \tu32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n> \n> -\ttrace_cxl_aer_correctable_error(cxlmd, status);\n> +\ttrace_cxl_aer_correctable_error(&cxlmd->dev, status,\n> +\t\t\t\t\tpci_get_dsn(pdev));\n> }\n> \n> static void\n> -cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,\n> +cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev,\n> +\t\t\t struct cxl_memdev *cxlmd,\n> \t\t\t struct cxl_ras_capability_regs ras_cap)\n> {\n> \tu32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;\n> @@ -53,8 +57,9 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,\n> \telse\n> \t\tfe = status;\n> \n> -\ttrace_cxl_aer_uncorrectable_error(cxlmd, status, fe,\n> -\t\t\t\t\t ras_cap.header_log);\n> +\ttrace_cxl_aer_uncorrectable_error(&cxlmd->dev, status, fe,\n> +\t\t\t\t\t ras_cap.header_log,\n> +\t\t\t\t\t pci_get_dsn(pdev));\n> }\n> \n> static int match_memdev_by_parent(struct device *dev, const void *uport)\n> @@ -101,9 +106,9 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n> \n> \tcxlmd = to_cxl_memdev(mem_dev);\n> \tif (data->severity == AER_CORRECTABLE)\n> -\t\tcxl_cper_trace_corr_prot_err(cxlmd, data->ras_cap);\n> +\t\tcxl_cper_trace_corr_prot_err(pdev, cxlmd, data->ras_cap);\n> \telse\n> -\t\tcxl_cper_trace_uncorr_prot_err(cxlmd, data->ras_cap);\n> +\t\tcxl_cper_trace_uncorr_prot_err(pdev, cxlmd, data->ras_cap);\n> }\n> EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err);\n> \n> @@ -183,7 +188,7 @@ void devm_cxl_port_ras_setup(struct cxl_port *port)\n> }\n> EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, \"CXL\");\n> \n> -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)\n> +void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n> {\n> \tvoid __iomem *addr;\n> \tu32 status;\n> @@ -195,7 +200,7 @@ void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)\n> \tstatus = readl(addr);\n> \tif (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {\n> \t\twritel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);\n> -\t\ttrace_cxl_aer_correctable_error(to_cxl_memdev(dev), status);\n> +\t\ttrace_cxl_aer_correctable_error(dev, status, serial);\n> \t}\n> }\n> \n> @@ -220,7 +225,7 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)\n> * Log the state of the RAS status registers and prepare them to log the\n> * next error status. Return 1 if reset needed.\n> */\n> -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n> +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n> {\n> \tu32 hl[CXL_HEADERLOG_SIZE_U32];\n> \tvoid __iomem *addr;\n> @@ -247,7 +252,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n> \t}\n> \n> \theader_log_copy(ras_base, hl);\n> -\ttrace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl);\n> +\ttrace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial);\n> \twritel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);\n> \n> \treturn true;\n> @@ -270,7 +275,8 @@ void cxl_cor_error_detected(struct pci_dev *pdev)\n> \t\tif (cxlds->rcd)\n> \t\t\tcxl_handle_rdport_errors(cxlds);\n> \n> -\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);\n> +\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n> +\t\t\t\t cxlmd->endpoint->regs.ras);\n> \t}\n> }\n> EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, \"CXL\");\n> @@ -299,7 +305,8 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n> \t\t * chance the situation is recoverable dump the status of the RAS\n> \t\t * capability registers and bounce the active state of the memdev.\n> \t\t */\n> -\t\tue = cxl_handle_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);\n> +\t\tue = cxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n> +\t\t\t\t cxlmd->endpoint->regs.ras);\n> \t}\n> \n> \tswitch (state) {\n> diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c\n> index 0a8b3b9b6388..61835fbafc0f 100644\n> --- a/drivers/cxl/core/ras_rch.c\n> +++ b/drivers/cxl/core/ras_rch.c\n> @@ -115,7 +115,9 @@ void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)\n> \n> \tpci_print_aer(pdev, severity, &aer_regs);\n> \tif (severity == AER_CORRECTABLE)\n> -\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras);\n> +\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n> +\t\t\t\t dport->regs.ras);\n> \telse\n> -\t\tcxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras);\n> +\t\tcxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n> +\t\t\t dport->regs.ras);\n> }\n> diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h\n> index a972e4ef1936..6f3957b3c3af 100644\n> --- a/drivers/cxl/core/trace.h\n> +++ b/drivers/cxl/core/trace.h\n> @@ -48,49 +48,22 @@\n> \t{ CXL_RAS_UC_IDE_RX_ERR, \"IDE Rx Error\" }\t\t\t \\\n> )\n> \n> -TRACE_EVENT(cxl_port_aer_uncorrectable_error,\n> -\tTP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),\n> -\tTP_ARGS(dev, status, fe, hl),\n> +TRACE_EVENT(cxl_aer_uncorrectable_error,\n> +\tTP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl,\n> +\t\t u64 serial),\n> +\tTP_ARGS(dev, status, fe, hl, serial),\n> \tTP_STRUCT__entry(\n> \t\t__string(device, dev_name(dev))\n> \t\t__string(host, dev_name(dev->parent))\n> -\t\t__field(u32, status)\n> -\t\t__field(u32, first_error)\n> -\t\t__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)\n> -\t),\n> -\tTP_fast_assign(\n> -\t\t__assign_str(device);\n> -\t\t__assign_str(host);\n> -\t\t__entry->status = status;\n> -\t\t__entry->first_error = fe;\n> -\t\t/*\n> -\t\t * Embed the 512B headerlog data for user app retrieval and\n> -\t\t * parsing, but no need to print this in the trace buffer.\n> -\t\t */\n> -\t\tmemcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n> -\t),\n> -\tTP_printk(\"device=%s host=%s status: '%s' first_error: '%s'\",\n> -\t\t __get_str(device), __get_str(host),\n> -\t\t show_uc_errs(__entry->status),\n> -\t\t show_uc_errs(__entry->first_error)\n> -\t)\n> -);\n> -\n> -TRACE_EVENT(cxl_aer_uncorrectable_error,\n> -\tTP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl),\n> -\tTP_ARGS(cxlmd, status, fe, hl),\n> -\tTP_STRUCT__entry(\n> -\t\t__string(memdev, dev_name(&cxlmd->dev))\n> -\t\t__string(host, dev_name(cxlmd->dev.parent))\n> \t\t__field(u64, serial)\n> \t\t__field(u32, status)\n> \t\t__field(u32, first_error)\n> \t\t__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)\n> \t),\n> \tTP_fast_assign(\n> -\t\t__assign_str(memdev);\n> +\t\t__assign_str(device);\n> \t\t__assign_str(host);\n> -\t\t__entry->serial = cxlmd->cxlds->serial;\n> +\t\t__entry->serial = serial;\n> \t\t__entry->status = status;\n> \t\t__entry->first_error = fe;\n> \t\t/*\n> @@ -99,8 +72,8 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,\n> \t\t */\n> \t\tmemcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n> \t),\n> -\tTP_printk(\"memdev=%s host=%s serial=%lld: status: '%s' first_error: '%s'\",\n> -\t\t __get_str(memdev), __get_str(host), __entry->serial,\n> +\tTP_printk(\"device=%s host=%s serial=%lld status: '%s' first_error: '%s'\",\n> +\t\t __get_str(device), __get_str(host), __entry->serial,\n> \t\t show_uc_errs(__entry->status),\n> \t\t show_uc_errs(__entry->first_error)\n> \t)\n> @@ -124,42 +97,23 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,\n> \t{ CXL_RAS_CE_PHYS_LAYER_ERR, \"Received Error From Physical Layer\" }\t\\\n> )\n> \n> -TRACE_EVENT(cxl_port_aer_correctable_error,\n> -\tTP_PROTO(struct device *dev, u32 status),\n> -\tTP_ARGS(dev, status),\n> +TRACE_EVENT(cxl_aer_correctable_error,\n> +\tTP_PROTO(const struct device *dev, u32 status, u64 serial),\n> +\tTP_ARGS(dev, status, serial),\n> \tTP_STRUCT__entry(\n> \t\t__string(device, dev_name(dev))\n> \t\t__string(host, dev_name(dev->parent))\n> -\t\t__field(u32, status)\n> -\t),\n> -\tTP_fast_assign(\n> -\t\t__assign_str(device);\n> -\t\t__assign_str(host);\n> -\t\t__entry->status = status;\n> -\t),\n> -\tTP_printk(\"device=%s host=%s status='%s'\",\n> -\t\t __get_str(device), __get_str(host),\n> -\t\t show_ce_errs(__entry->status)\n> -\t)\n> -);\n> -\n> -TRACE_EVENT(cxl_aer_correctable_error,\n> -\tTP_PROTO(const struct cxl_memdev *cxlmd, u32 status),\n> -\tTP_ARGS(cxlmd, status),\n> -\tTP_STRUCT__entry(\n> -\t\t__string(memdev, dev_name(&cxlmd->dev))\n> -\t\t__string(host, dev_name(cxlmd->dev.parent))\n> \t\t__field(u64, serial)\n> \t\t__field(u32, status)\n> \t),\n> \tTP_fast_assign(\n> -\t\t__assign_str(memdev);\n> +\t\t__assign_str(device);\n> \t\t__assign_str(host);\n> -\t\t__entry->serial = cxlmd->cxlds->serial;\n> +\t\t__entry->serial = serial;\n> \t\t__entry->status = status;\n> \t),\n> -\tTP_printk(\"memdev=%s host=%s serial=%lld: status: '%s'\",\n> -\t\t __get_str(memdev), __get_str(host), __entry->serial,\n> +\tTP_printk(\"device=%s host=%s serial=%lld status: '%s'\",\n> +\t\t __get_str(device), __get_str(host), __entry->serial,\n> \t\t show_ce_errs(__entry->status)\n> \t)\n> );","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=intel.com header.i=@intel.com header.a=rsa-sha256\n header.s=Intel header.b=dq0M4+7N;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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d=\"scan'208\";a=\"259599581\""],"X-ExtLoop1":"1","Message-ID":"<618748f8-ad14-42ea-8694-0c1bc5b95c54@intel.com>","Date":"Tue, 5 May 2026 14:46:55 -0700","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Subject":"Re: [PATCH v17 02/11] cxl/ras: Unify Endpoint and Port AER trace\n events","To":"Terry Bowman , dave@stgolabs.net, jic23@kernel.org,\n alison.schofield@intel.com, djbw@kernel.org, bhelgaas@google.com,\n ming.li@zohomail.com, Smita.KoralahalliChannabasappa@amd.com,\n rrichter@amd.com, PradeepVineshReddy.Kodamati@amd.com, lukas@wunner.de,\n Benjamin.Cheatham@amd.com, sathyanarayanan.kuppuswamy@linux.intel.com,\n vishal.l.verma@intel.com, alucerop@amd.com, ira.weiny@intel.com,\n corbet@lwn.net, rafael@kernel.org, xueshuai@linux.alibaba.com,\n linux-cxl@vger.kernel.org","Cc":"linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n linux-acpi@vger.kernel.org, linux-doc@vger.kernel.org","References":"<20260505173029.2718246-1-terry.bowman@amd.com>\n <20260505173029.2718246-3-terry.bowman@amd.com>","Content-Language":"en-US","From":"Dave Jiang ","In-Reply-To":"<20260505173029.2718246-3-terry.bowman@amd.com>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit"}},{"id":3687977,"web_url":"http://patchwork.ozlabs.org/comment/3687977/","msgid":"<20260507190836.70197e24@jic23-huawei>","list_archive_url":null,"date":"2026-05-07T18:08:36","subject":"Re: [PATCH v17 02/11] cxl/ras: Unify Endpoint and Port AER trace\n events","submitter":{"id":10151,"url":"http://patchwork.ozlabs.org/api/people/10151/","name":"Jonathan Cameron","email":"jic23@kernel.org"},"content":"On Tue, 5 May 2026 12:30:20 -0500\nTerry Bowman wrote:\n\n> From: Dan Williams \n\n+CC Mauro - rasdaemon related - see below.\n\n> \n> CXL protocol error logging uses two parallel sets of trace events. The\n> cxl_port_aer_correctable_error() and cxl_port_aer_uncorrectable_error()\n> events are used by CPER for CXL Port devices. The cxl_aer_correctable_error()\n> and cxl_aer_uncorrectable_error() events are used for CXL Endpoints. Update\n> the trace routines to use the latter for all CXL devices on both the CPER\n> and native AER paths.\n> \n> Generalize cxl_aer_correctable_error()/cxl_aer_uncorrectable_error to\n> take a struct device * and a u64 serial argument supplied by the caller.\n> cxl_handle_ras() and cxl_handle_cor_ras() gain the new u64 serial parameter,\n> sourced from pci_get_dsn().\n> \n> The CPER path keeps its existing Port-vs-Endpoint dispatch and passes the\n> new arguments to the unified trace events. The CPER path will be folded\n> together in a following patch.\n> \n> Remove the now-unused cxl_port_aer_correctable_error() and\n> cxl_port_aer_uncorrectable_error().\n> \n> **WARNING: ABI BREAK**\n> Rename the trace event field \"memdev\" to \"device\" so all CXL device types\n> (Ports and Endpoints) can be reported under a common field name. Note this\n> is an ABI break for userspace tools that key off the old \"memdev\" field.\n> Specifically, rasdaemon's ras-cxl-handler.c looks up \"memdev\" and bails on\n> NULL, so an unmodified rasdaemon will drop every CXL CE/UCE event once this\n> kernel ships. A rasdaemon update is needed in a separate series.\n> \n> The need for the field rename was discussed in v16 review [1].\n\nThis concerns me (sorry I wasn't paying attention to the v16 thread).\nIt is a userspace regression against code that is out in the wild and typically\nnot updated in sync with the kernel.\n\nIf you are suggesting breaking ras-daemon at the very least +CC the maintainer.\n\nTo get to a unified tracepoint add a new one that does what you want, but\nmaintain the existing ones as well. Userspace can then migrate and maybe\nin 5+ years time we can delete the non unified ones.\n\nNo actually comments on the code, just left it all here for Mauro,\n\nThanks,\n\nJonathan\n\n> \n> Also, for CXL Upstream Switch Port (USP) and Endpoint (EP) fatal UCE,\n> the cxl_aer_uncorrectable_error trace event is not emitted. The AER core\n> only retrieves PCI_ERR_UNCOR_STATUS for Root Ports, RCECs, and Downstream\n> Ports, or for non-fatal severities. PCI config reads to the source device\n> are expected to fail otherwise, so the AER core never reads the status\n> word, is_cxl_error() does not classify the event as CXL, and the AER path\n> handles it instead. In this case the AER handler consumes the event and\n> logs it as an AER error without calling the CXL RAS handlers or trace\n> logging.\n> \n> Before this patch, Endpoint and Port devices emitted different events:\n> \n> # Endpoint (cxl_aer_*):\n> cxl_aer_correctable_error: memdev=mem0 host=0000:0c:00.0 serial=0: status: 'CRC Threshold Hit'\n> cxl_aer_uncorrectable_error: memdev=mem0 host=0000:0c:00.0 serial=0: status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n> \n> # Port (cxl_port_aer_*, no serial field):\n> cxl_port_aer_correctable_error: device=0000:0c:00.0 host=pci0000:0c status='CRC Threshold Hit'\n> cxl_port_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n> \n> After this patch, all CXL devices emit the unified cxl_aer_* events\n> with the same field layout:\n> \n> cxl_aer_correctable_error: device=0000:0c:00.0 host=pci0000:0c serial=0 status: 'CRC Threshold Hit'\n> cxl_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c serial=0 status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n> \n> [1] https://lore.kernel.org/linux-cxl/69cb2d5ba3111_178904100b7@dwillia2-mobl4.notmuch/\n> \n> Co-developed-by: Terry Bowman \n> Signed-off-by: Terry Bowman \n> Signed-off-by: Dan Williams \n> \n> ---\n> \n> Changes in v16->v17:\n> - Replace cxlds->serial with pci_get_dsn()\n> - Change 'memdev' to 'device' (Dan)\n> - Updated Commit message\n> \n> Changes in v15->v16:\n> - Add Dan's review-by\n> - Incorporate Dan's comment into commit message:\n> \"Add the serial number at the end to preserve compatibility with\n> libtraceevent parsing of the parameters.\"\n> \n> Changes in v14->v15:\n> - Update commit message.\n> - Moved cxl_handle_ras/cxl_handle_cor_ras() changes to future patch (terry)\n> \n> Changes in v13->v14:\n> - Update commit headline (Bjorn)\n> \n> Changes in v12->v13:\n> - Added Dave Jiang's review-by\n> \n> Changes in v11 -> v12:\n> - Correct parameters to call trace_cxl_aer_correctable_error()\n> - Add reviewed-by for Jonathan and Shiju\n> \n> Changes in v10->v11:\n> - Updated CE and UCE trace routines to maintain consistent TP_Struct ABI\n> and unchanged TP_printk() logging.\n> ---\n> drivers/cxl/core/core.h | 11 ++++--\n> drivers/cxl/core/ras.c | 39 +++++++++++--------\n> drivers/cxl/core/ras_rch.c | 6 ++-\n> drivers/cxl/core/trace.h | 76 ++++++++------------------------------\n> 4 files changed, 49 insertions(+), 83 deletions(-)\n> \n> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h\n> index 82ca3a476708..132ac9c1ebf4 100644\n> --- a/drivers/cxl/core/core.h\n> +++ b/drivers/cxl/core/core.h\n> @@ -183,8 +183,9 @@ static inline struct device *dport_to_host(struct cxl_dport *dport)\n> #ifdef CONFIG_CXL_RAS\n> int cxl_ras_init(void);\n> void cxl_ras_exit(void);\n> -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base);\n> -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base);\n> +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base);\n> +void cxl_handle_cor_ras(struct device *dev, u64 serial,\n> +\t\t\tvoid __iomem *ras_base);\n> void cxl_dport_map_rch_aer(struct cxl_dport *dport);\n> void cxl_disable_rch_root_ints(struct cxl_dport *dport);\n> void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds);\n> @@ -195,11 +196,13 @@ static inline int cxl_ras_init(void)\n> \treturn 0;\n> }\n> static inline void cxl_ras_exit(void) { }\n> -static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n> +static inline bool cxl_handle_ras(struct device *dev, u64 serial,\n> +\t\t\t\t void __iomem *ras_base)\n> {\n> \treturn false;\n> }\n> -static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { }\n> +static inline void cxl_handle_cor_ras(struct device *dev, u64 serial,\n> +\t\t\t\t void __iomem *ras_base) { }\n> static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }\n> static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }\n> static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { }\n> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\n> index 006c6ffc2f56..d7081caaf5d3 100644\n> --- a/drivers/cxl/core/ras.c\n> +++ b/drivers/cxl/core/ras.c\n> @@ -13,7 +13,7 @@ static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev,\n> {\n> \tu32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n> \n> -\ttrace_cxl_port_aer_correctable_error(&pdev->dev, status);\n> +\ttrace_cxl_aer_correctable_error(&pdev->dev, status, pci_get_dsn(pdev));\n> }\n> \n> static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n> @@ -28,20 +28,24 @@ static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n> \telse\n> \t\tfe = status;\n> \n> -\ttrace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe,\n> -\t\t\t\t\t ras_cap.header_log);\n> +\ttrace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe,\n> +\t\t\t\t\t ras_cap.header_log,\n> +\t\t\t\t\t pci_get_dsn(pdev));\n> }\n> \n> -static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd,\n> +static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev,\n> +\t\t\t\t\t struct cxl_memdev *cxlmd,\n> \t\t\t\t\t struct cxl_ras_capability_regs ras_cap)\n> {\n> \tu32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n> \n> -\ttrace_cxl_aer_correctable_error(cxlmd, status);\n> +\ttrace_cxl_aer_correctable_error(&cxlmd->dev, status,\n> +\t\t\t\t\tpci_get_dsn(pdev));\n> }\n> \n> static void\n> -cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,\n> +cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev,\n> +\t\t\t struct cxl_memdev *cxlmd,\n> \t\t\t struct cxl_ras_capability_regs ras_cap)\n> {\n> \tu32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;\n> @@ -53,8 +57,9 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,\n> \telse\n> \t\tfe = status;\n> \n> -\ttrace_cxl_aer_uncorrectable_error(cxlmd, status, fe,\n> -\t\t\t\t\t ras_cap.header_log);\n> +\ttrace_cxl_aer_uncorrectable_error(&cxlmd->dev, status, fe,\n> +\t\t\t\t\t ras_cap.header_log,\n> +\t\t\t\t\t pci_get_dsn(pdev));\n> }\n> \n> static int match_memdev_by_parent(struct device *dev, const void *uport)\n> @@ -101,9 +106,9 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n> \n> \tcxlmd = to_cxl_memdev(mem_dev);\n> \tif (data->severity == AER_CORRECTABLE)\n> -\t\tcxl_cper_trace_corr_prot_err(cxlmd, data->ras_cap);\n> +\t\tcxl_cper_trace_corr_prot_err(pdev, cxlmd, data->ras_cap);\n> \telse\n> -\t\tcxl_cper_trace_uncorr_prot_err(cxlmd, data->ras_cap);\n> +\t\tcxl_cper_trace_uncorr_prot_err(pdev, cxlmd, data->ras_cap);\n> }\n> EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err);\n> \n> @@ -183,7 +188,7 @@ void devm_cxl_port_ras_setup(struct cxl_port *port)\n> }\n> EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, \"CXL\");\n> \n> -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)\n> +void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n> {\n> \tvoid __iomem *addr;\n> \tu32 status;\n> @@ -195,7 +200,7 @@ void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)\n> \tstatus = readl(addr);\n> \tif (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {\n> \t\twritel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);\n> -\t\ttrace_cxl_aer_correctable_error(to_cxl_memdev(dev), status);\n> +\t\ttrace_cxl_aer_correctable_error(dev, status, serial);\n> \t}\n> }\n> \n> @@ -220,7 +225,7 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)\n> * Log the state of the RAS status registers and prepare them to log the\n> * next error status. Return 1 if reset needed.\n> */\n> -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n> +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n> {\n> \tu32 hl[CXL_HEADERLOG_SIZE_U32];\n> \tvoid __iomem *addr;\n> @@ -247,7 +252,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n> \t}\n> \n> \theader_log_copy(ras_base, hl);\n> -\ttrace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl);\n> +\ttrace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial);\n> \twritel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);\n> \n> \treturn true;\n> @@ -270,7 +275,8 @@ void cxl_cor_error_detected(struct pci_dev *pdev)\n> \t\tif (cxlds->rcd)\n> \t\t\tcxl_handle_rdport_errors(cxlds);\n> \n> -\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);\n> +\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n> +\t\t\t\t cxlmd->endpoint->regs.ras);\n> \t}\n> }\n> EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, \"CXL\");\n> @@ -299,7 +305,8 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n> \t\t * chance the situation is recoverable dump the status of the RAS\n> \t\t * capability registers and bounce the active state of the memdev.\n> \t\t */\n> -\t\tue = cxl_handle_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);\n> +\t\tue = cxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n> +\t\t\t\t cxlmd->endpoint->regs.ras);\n> \t}\n> \n> \tswitch (state) {\n> diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c\n> index 0a8b3b9b6388..61835fbafc0f 100644\n> --- a/drivers/cxl/core/ras_rch.c\n> +++ b/drivers/cxl/core/ras_rch.c\n> @@ -115,7 +115,9 @@ void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)\n> \n> \tpci_print_aer(pdev, severity, &aer_regs);\n> \tif (severity == AER_CORRECTABLE)\n> -\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras);\n> +\t\tcxl_handle_cor_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n> +\t\t\t\t dport->regs.ras);\n> \telse\n> -\t\tcxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras);\n> +\t\tcxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n> +\t\t\t dport->regs.ras);\n> }\n> diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h\n> index a972e4ef1936..6f3957b3c3af 100644\n> --- a/drivers/cxl/core/trace.h\n> +++ b/drivers/cxl/core/trace.h\n> @@ -48,49 +48,22 @@\n> \t{ CXL_RAS_UC_IDE_RX_ERR, \"IDE Rx Error\" }\t\t\t \\\n> )\n> \n> -TRACE_EVENT(cxl_port_aer_uncorrectable_error,\n> -\tTP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),\n> -\tTP_ARGS(dev, status, fe, hl),\n> +TRACE_EVENT(cxl_aer_uncorrectable_error,\n> +\tTP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl,\n> +\t\t u64 serial),\n> +\tTP_ARGS(dev, status, fe, hl, serial),\n> \tTP_STRUCT__entry(\n> \t\t__string(device, dev_name(dev))\n> \t\t__string(host, dev_name(dev->parent))\n> -\t\t__field(u32, status)\n> -\t\t__field(u32, first_error)\n> -\t\t__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)\n> -\t),\n> -\tTP_fast_assign(\n> -\t\t__assign_str(device);\n> -\t\t__assign_str(host);\n> -\t\t__entry->status = status;\n> -\t\t__entry->first_error = fe;\n> -\t\t/*\n> -\t\t * Embed the 512B headerlog data for user app retrieval and\n> -\t\t * parsing, but no need to print this in the trace buffer.\n> -\t\t */\n> -\t\tmemcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n> -\t),\n> -\tTP_printk(\"device=%s host=%s status: '%s' first_error: '%s'\",\n> -\t\t __get_str(device), __get_str(host),\n> -\t\t show_uc_errs(__entry->status),\n> -\t\t show_uc_errs(__entry->first_error)\n> -\t)\n> -);\n> -\n> -TRACE_EVENT(cxl_aer_uncorrectable_error,\n> -\tTP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl),\n> -\tTP_ARGS(cxlmd, status, fe, hl),\n> -\tTP_STRUCT__entry(\n> -\t\t__string(memdev, dev_name(&cxlmd->dev))\n> -\t\t__string(host, dev_name(cxlmd->dev.parent))\n> \t\t__field(u64, serial)\n> \t\t__field(u32, status)\n> \t\t__field(u32, first_error)\n> \t\t__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)\n> \t),\n> \tTP_fast_assign(\n> -\t\t__assign_str(memdev);\n> +\t\t__assign_str(device);\n> \t\t__assign_str(host);\n> -\t\t__entry->serial = cxlmd->cxlds->serial;\n> +\t\t__entry->serial = serial;\n> \t\t__entry->status = status;\n> \t\t__entry->first_error = fe;\n> \t\t/*\n> @@ -99,8 +72,8 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,\n> \t\t */\n> \t\tmemcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n> \t),\n> -\tTP_printk(\"memdev=%s host=%s serial=%lld: status: '%s' first_error: '%s'\",\n> -\t\t __get_str(memdev), __get_str(host), __entry->serial,\n> +\tTP_printk(\"device=%s host=%s serial=%lld status: '%s' first_error: '%s'\",\n> +\t\t __get_str(device), __get_str(host), __entry->serial,\n> \t\t show_uc_errs(__entry->status),\n> \t\t show_uc_errs(__entry->first_error)\n> \t)\n> @@ -124,42 +97,23 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,\n> \t{ CXL_RAS_CE_PHYS_LAYER_ERR, \"Received Error From Physical Layer\" }\t\\\n> )\n> \n> -TRACE_EVENT(cxl_port_aer_correctable_error,\n> -\tTP_PROTO(struct device *dev, u32 status),\n> -\tTP_ARGS(dev, status),\n> +TRACE_EVENT(cxl_aer_correctable_error,\n> +\tTP_PROTO(const struct device *dev, u32 status, u64 serial),\n> +\tTP_ARGS(dev, status, serial),\n> \tTP_STRUCT__entry(\n> \t\t__string(device, dev_name(dev))\n> \t\t__string(host, dev_name(dev->parent))\n> -\t\t__field(u32, status)\n> -\t),\n> -\tTP_fast_assign(\n> -\t\t__assign_str(device);\n> -\t\t__assign_str(host);\n> -\t\t__entry->status = status;\n> -\t),\n> -\tTP_printk(\"device=%s host=%s status='%s'\",\n> -\t\t __get_str(device), __get_str(host),\n> -\t\t show_ce_errs(__entry->status)\n> -\t)\n> -);\n> -\n> -TRACE_EVENT(cxl_aer_correctable_error,\n> -\tTP_PROTO(const struct cxl_memdev *cxlmd, u32 status),\n> -\tTP_ARGS(cxlmd, status),\n> -\tTP_STRUCT__entry(\n> -\t\t__string(memdev, dev_name(&cxlmd->dev))\n> -\t\t__string(host, dev_name(cxlmd->dev.parent))\n> \t\t__field(u64, serial)\n> \t\t__field(u32, status)\n> \t),\n> \tTP_fast_assign(\n> -\t\t__assign_str(memdev);\n> +\t\t__assign_str(device);\n> \t\t__assign_str(host);\n> -\t\t__entry->serial = cxlmd->cxlds->serial;\n> +\t\t__entry->serial = serial;\n> \t\t__entry->status = status;\n> \t),\n> -\tTP_printk(\"memdev=%s host=%s serial=%lld: status: '%s'\",\n> -\t\t __get_str(memdev), __get_str(host), __entry->serial,\n> +\tTP_printk(\"device=%s host=%s serial=%lld status: '%s'\",\n> +\t\t __get_str(device), __get_str(host), __entry->serial,\n> \t\t show_ce_errs(__entry->status)\n> \t)\n> );","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=Yx1oTv3g;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) 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/MNdNw1kj5t35YxPavh3kToP7BHmR/lb/SyAOMdba8EII4BrXeYEyGmjuco7uu8/9S\n\t wFsWxsFeMMu44TuKxv822e6gQY2HKzcE9VaiiJHIJuYSw2M4D25m5tsiKzPJG41Qas\n\t vT2L5IBU/cenw==","Date":"Thu, 7 May 2026 19:08:36 +0100","From":"Jonathan Cameron ","To":"Terry Bowman ","Cc":", ,\n , , ,\n , ,\n , ,\n , ,\n , ,\n , ,\n , , ,\n , ,\n , ,\n , ,\n , Mauro Carvalho Chehab ","Subject":"Re: [PATCH v17 02/11] cxl/ras: Unify Endpoint and Port AER trace\n events","Message-ID":"<20260507190836.70197e24@jic23-huawei>","In-Reply-To":"<20260505173029.2718246-3-terry.bowman@amd.com>","References":"<20260505173029.2718246-1-terry.bowman@amd.com>\n\t<20260505173029.2718246-3-terry.bowman@amd.com>","X-Mailer":"Claws Mail 4.4.0 (GTK 3.24.52; x86_64-pc-linux-gnu)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit"}},{"id":3687990,"web_url":"http://patchwork.ozlabs.org/comment/3687990/","msgid":"<8913c666-a343-4717-8ab2-0b8546d1bdfb@amd.com>","list_archive_url":null,"date":"2026-05-07T18:33:45","subject":"Re: [PATCH v17 02/11] cxl/ras: Unify Endpoint and Port AER trace\n events","submitter":{"id":82124,"url":"http://patchwork.ozlabs.org/api/people/82124/","name":"Bowman, Terry","email":"Terry.Bowman@amd.com"},"content":"On 5/7/2026 1:08 PM, Jonathan Cameron wrote:\n> [Some people who received this message don't often get email from jic23@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]\n> \n> On Tue, 5 May 2026 12:30:20 -0500\n> Terry Bowman wrote:\n> \n>> From: Dan Williams \n> \n> +CC Mauro - rasdaemon related - see below.\n> \n>>\n>> CXL protocol error logging uses two parallel sets of trace events. The\n>> cxl_port_aer_correctable_error() and cxl_port_aer_uncorrectable_error()\n>> events are used by CPER for CXL Port devices. The cxl_aer_correctable_error()\n>> and cxl_aer_uncorrectable_error() events are used for CXL Endpoints. Update\n>> the trace routines to use the latter for all CXL devices on both the CPER\n>> and native AER paths.\n>>\n>> Generalize cxl_aer_correctable_error()/cxl_aer_uncorrectable_error to\n>> take a struct device * and a u64 serial argument supplied by the caller.\n>> cxl_handle_ras() and cxl_handle_cor_ras() gain the new u64 serial parameter,\n>> sourced from pci_get_dsn().\n>>\n>> The CPER path keeps its existing Port-vs-Endpoint dispatch and passes the\n>> new arguments to the unified trace events. The CPER path will be folded\n>> together in a following patch.\n>>\n>> Remove the now-unused cxl_port_aer_correctable_error() and\n>> cxl_port_aer_uncorrectable_error().\n>>\n>> **WARNING: ABI BREAK**\n>> Rename the trace event field \"memdev\" to \"device\" so all CXL device types\n>> (Ports and Endpoints) can be reported under a common field name. Note this\n>> is an ABI break for userspace tools that key off the old \"memdev\" field.\n>> Specifically, rasdaemon's ras-cxl-handler.c looks up \"memdev\" and bails on\n>> NULL, so an unmodified rasdaemon will drop every CXL CE/UCE event once this\n>> kernel ships. A rasdaemon update is needed in a separate series.\n>>\n>> The need for the field rename was discussed in v16 review [1].\n> \n> This concerns me (sorry I wasn't paying attention to the v16 thread).\n> It is a userspace regression against code that is out in the wild and typically\n> not updated in sync with the kernel.\n> \n> If you are suggesting breaking ras-daemon at the very least +CC the maintainer.\n> \n> To get to a unified tracepoint add a new one that does what you want, but\n> maintain the existing ones as well. Userspace can then migrate and maybe\n> in 5+ years time we can delete the non unified ones.\n> \n> No actually comments on the code, just left it all here for Mauro,\n> \n> Thanks,\n> \n> Jonathan\n> \n\nDan was clear about using a single set of CE and UE handlers for all CXL RAS \nprotocol errors. While I understand there may be concerns, please direct any \nobjections to Dan and clarify what changes are required to avoid this \nrepeatedly going back and forth.\n\n[1] https://lore.kernel.org/linux-cxl/69cb2d5ba3111_178904100b7@dwillia2-mobl4.notmuch/\n\n- Terry\n\n\n>>\n>> Also, for CXL Upstream Switch Port (USP) and Endpoint (EP) fatal UCE,\n>> the cxl_aer_uncorrectable_error trace event is not emitted. The AER core\n>> only retrieves PCI_ERR_UNCOR_STATUS for Root Ports, RCECs, and Downstream\n>> Ports, or for non-fatal severities. PCI config reads to the source device\n>> are expected to fail otherwise, so the AER core never reads the status\n>> word, is_cxl_error() does not classify the event as CXL, and the AER path\n>> handles it instead. In this case the AER handler consumes the event and\n>> logs it as an AER error without calling the CXL RAS handlers or trace\n>> logging.\n>>\n>> Before this patch, Endpoint and Port devices emitted different events:\n>>\n>> # Endpoint (cxl_aer_*):\n>> cxl_aer_correctable_error: memdev=mem0 host=0000:0c:00.0 serial=0: status: 'CRC Threshold Hit'\n>> cxl_aer_uncorrectable_error: memdev=mem0 host=0000:0c:00.0 serial=0: status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n>>\n>> # Port (cxl_port_aer_*, no serial field):\n>> cxl_port_aer_correctable_error: device=0000:0c:00.0 host=pci0000:0c status='CRC Threshold Hit'\n>> cxl_port_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n>>\n>> After this patch, all CXL devices emit the unified cxl_aer_* events\n>> with the same field layout:\n>>\n>> cxl_aer_correctable_error: device=0000:0c:00.0 host=pci0000:0c serial=0 status: 'CRC Threshold Hit'\n>> cxl_aer_uncorrectable_error: device=0000:0c:00.0 host=pci0000:0c serial=0 status: 'Cache Data ECC Error | Memory Data ECC Error' first_error: 'Cache Data ECC Error'\n>>\n>> [1] https://lore.kernel.org/linux-cxl/69cb2d5ba3111_178904100b7@dwillia2-mobl4.notmuch/\n>>\n>> Co-developed-by: Terry Bowman \n>> Signed-off-by: Terry Bowman \n>> Signed-off-by: Dan Williams \n>>\n>> ---\n>>\n>> Changes in v16->v17:\n>> - Replace cxlds->serial with pci_get_dsn()\n>> - Change 'memdev' to 'device' (Dan)\n>> - Updated Commit message\n>>\n>> Changes in v15->v16:\n>> - Add Dan's review-by\n>> - Incorporate Dan's comment into commit message:\n>> \"Add the serial number at the end to preserve compatibility with\n>> libtraceevent parsing of the parameters.\"\n>>\n>> Changes in v14->v15:\n>> - Update commit message.\n>> - Moved cxl_handle_ras/cxl_handle_cor_ras() changes to future patch (terry)\n>>\n>> Changes in v13->v14:\n>> - Update commit headline (Bjorn)\n>>\n>> Changes in v12->v13:\n>> - Added Dave Jiang's review-by\n>>\n>> Changes in v11 -> v12:\n>> - Correct parameters to call trace_cxl_aer_correctable_error()\n>> - Add reviewed-by for Jonathan and Shiju\n>>\n>> Changes in v10->v11:\n>> - Updated CE and UCE trace routines to maintain consistent TP_Struct ABI\n>> and unchanged TP_printk() logging.\n>> ---\n>> drivers/cxl/core/core.h | 11 ++++--\n>> drivers/cxl/core/ras.c | 39 +++++++++++--------\n>> drivers/cxl/core/ras_rch.c | 6 ++-\n>> drivers/cxl/core/trace.h | 76 ++++++++------------------------------\n>> 4 files changed, 49 insertions(+), 83 deletions(-)\n>>\n>> diff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h\n>> index 82ca3a476708..132ac9c1ebf4 100644\n>> --- a/drivers/cxl/core/core.h\n>> +++ b/drivers/cxl/core/core.h\n>> @@ -183,8 +183,9 @@ static inline struct device *dport_to_host(struct cxl_dport *dport)\n>> #ifdef CONFIG_CXL_RAS\n>> int cxl_ras_init(void);\n>> void cxl_ras_exit(void);\n>> -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base);\n>> -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base);\n>> +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base);\n>> +void cxl_handle_cor_ras(struct device *dev, u64 serial,\n>> + void __iomem *ras_base);\n>> void cxl_dport_map_rch_aer(struct cxl_dport *dport);\n>> void cxl_disable_rch_root_ints(struct cxl_dport *dport);\n>> void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds);\n>> @@ -195,11 +196,13 @@ static inline int cxl_ras_init(void)\n>> return 0;\n>> }\n>> static inline void cxl_ras_exit(void) { }\n>> -static inline bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n>> +static inline bool cxl_handle_ras(struct device *dev, u64 serial,\n>> + void __iomem *ras_base)\n>> {\n>> return false;\n>> }\n>> -static inline void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base) { }\n>> +static inline void cxl_handle_cor_ras(struct device *dev, u64 serial,\n>> + void __iomem *ras_base) { }\n>> static inline void cxl_dport_map_rch_aer(struct cxl_dport *dport) { }\n>> static inline void cxl_disable_rch_root_ints(struct cxl_dport *dport) { }\n>> static inline void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds) { }\n>> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\n>> index 006c6ffc2f56..d7081caaf5d3 100644\n>> --- a/drivers/cxl/core/ras.c\n>> +++ b/drivers/cxl/core/ras.c\n>> @@ -13,7 +13,7 @@ static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev,\n>> {\n>> u32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n>>\n>> - trace_cxl_port_aer_correctable_error(&pdev->dev, status);\n>> + trace_cxl_aer_correctable_error(&pdev->dev, status, pci_get_dsn(pdev));\n>> }\n>>\n>> static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n>> @@ -28,20 +28,24 @@ static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n>> else\n>> fe = status;\n>>\n>> - trace_cxl_port_aer_uncorrectable_error(&pdev->dev, status, fe,\n>> - ras_cap.header_log);\n>> + trace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe,\n>> + ras_cap.header_log,\n>> + pci_get_dsn(pdev));\n>> }\n>>\n>> -static void cxl_cper_trace_corr_prot_err(struct cxl_memdev *cxlmd,\n>> +static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev,\n>> + struct cxl_memdev *cxlmd,\n>> struct cxl_ras_capability_regs ras_cap)\n>> {\n>> u32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n>>\n>> - trace_cxl_aer_correctable_error(cxlmd, status);\n>> + trace_cxl_aer_correctable_error(&cxlmd->dev, status,\n>> + pci_get_dsn(pdev));\n>> }\n>>\n>> static void\n>> -cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,\n>> +cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev,\n>> + struct cxl_memdev *cxlmd,\n>> struct cxl_ras_capability_regs ras_cap)\n>> {\n>> u32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;\n>> @@ -53,8 +57,9 @@ cxl_cper_trace_uncorr_prot_err(struct cxl_memdev *cxlmd,\n>> else\n>> fe = status;\n>>\n>> - trace_cxl_aer_uncorrectable_error(cxlmd, status, fe,\n>> - ras_cap.header_log);\n>> + trace_cxl_aer_uncorrectable_error(&cxlmd->dev, status, fe,\n>> + ras_cap.header_log,\n>> + pci_get_dsn(pdev));\n>> }\n>>\n>> static int match_memdev_by_parent(struct device *dev, const void *uport)\n>> @@ -101,9 +106,9 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n>>\n>> cxlmd = to_cxl_memdev(mem_dev);\n>> if (data->severity == AER_CORRECTABLE)\n>> - cxl_cper_trace_corr_prot_err(cxlmd, data->ras_cap);\n>> + cxl_cper_trace_corr_prot_err(pdev, cxlmd, data->ras_cap);\n>> else\n>> - cxl_cper_trace_uncorr_prot_err(cxlmd, data->ras_cap);\n>> + cxl_cper_trace_uncorr_prot_err(pdev, cxlmd, data->ras_cap);\n>> }\n>> EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err);\n>>\n>> @@ -183,7 +188,7 @@ void devm_cxl_port_ras_setup(struct cxl_port *port)\n>> }\n>> EXPORT_SYMBOL_NS_GPL(devm_cxl_port_ras_setup, \"CXL\");\n>>\n>> -void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)\n>> +void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n>> {\n>> void __iomem *addr;\n>> u32 status;\n>> @@ -195,7 +200,7 @@ void cxl_handle_cor_ras(struct device *dev, void __iomem *ras_base)\n>> status = readl(addr);\n>> if (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {\n>> writel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);\n>> - trace_cxl_aer_correctable_error(to_cxl_memdev(dev), status);\n>> + trace_cxl_aer_correctable_error(dev, status, serial);\n>> }\n>> }\n>>\n>> @@ -220,7 +225,7 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)\n>> * Log the state of the RAS status registers and prepare them to log the\n>> * next error status. Return 1 if reset needed.\n>> */\n>> -bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n>> +bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n>> {\n>> u32 hl[CXL_HEADERLOG_SIZE_U32];\n>> void __iomem *addr;\n>> @@ -247,7 +252,7 @@ bool cxl_handle_ras(struct device *dev, void __iomem *ras_base)\n>> }\n>>\n>> header_log_copy(ras_base, hl);\n>> - trace_cxl_aer_uncorrectable_error(to_cxl_memdev(dev), status, fe, hl);\n>> + trace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial);\n>> writel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);\n>>\n>> return true;\n>> @@ -270,7 +275,8 @@ void cxl_cor_error_detected(struct pci_dev *pdev)\n>> if (cxlds->rcd)\n>> cxl_handle_rdport_errors(cxlds);\n>>\n>> - cxl_handle_cor_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);\n>> + cxl_handle_cor_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n>> + cxlmd->endpoint->regs.ras);\n>> }\n>> }\n>> EXPORT_SYMBOL_NS_GPL(cxl_cor_error_detected, \"CXL\");\n>> @@ -299,7 +305,8 @@ pci_ers_result_t cxl_error_detected(struct pci_dev *pdev,\n>> * chance the situation is recoverable dump the status of the RAS\n>> * capability registers and bounce the active state of the memdev.\n>> */\n>> - ue = cxl_handle_ras(&cxlds->cxlmd->dev, cxlmd->endpoint->regs.ras);\n>> + ue = cxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n>> + cxlmd->endpoint->regs.ras);\n>> }\n>>\n>> switch (state) {\n>> diff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c\n>> index 0a8b3b9b6388..61835fbafc0f 100644\n>> --- a/drivers/cxl/core/ras_rch.c\n>> +++ b/drivers/cxl/core/ras_rch.c\n>> @@ -115,7 +115,9 @@ void cxl_handle_rdport_errors(struct cxl_dev_state *cxlds)\n>>\n>> pci_print_aer(pdev, severity, &aer_regs);\n>> if (severity == AER_CORRECTABLE)\n>> - cxl_handle_cor_ras(&cxlds->cxlmd->dev, dport->regs.ras);\n>> + cxl_handle_cor_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n>> + dport->regs.ras);\n>> else\n>> - cxl_handle_ras(&cxlds->cxlmd->dev, dport->regs.ras);\n>> + cxl_handle_ras(&cxlds->cxlmd->dev, pci_get_dsn(pdev),\n>> + dport->regs.ras);\n>> }\n>> diff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h\n>> index a972e4ef1936..6f3957b3c3af 100644\n>> --- a/drivers/cxl/core/trace.h\n>> +++ b/drivers/cxl/core/trace.h\n>> @@ -48,49 +48,22 @@\n>> { CXL_RAS_UC_IDE_RX_ERR, \"IDE Rx Error\" } \\\n>> )\n>>\n>> -TRACE_EVENT(cxl_port_aer_uncorrectable_error,\n>> - TP_PROTO(struct device *dev, u32 status, u32 fe, u32 *hl),\n>> - TP_ARGS(dev, status, fe, hl),\n>> +TRACE_EVENT(cxl_aer_uncorrectable_error,\n>> + TP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl,\n>> + u64 serial),\n>> + TP_ARGS(dev, status, fe, hl, serial),\n>> TP_STRUCT__entry(\n>> __string(device, dev_name(dev))\n>> __string(host, dev_name(dev->parent))\n>> - __field(u32, status)\n>> - __field(u32, first_error)\n>> - __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)\n>> - ),\n>> - TP_fast_assign(\n>> - __assign_str(device);\n>> - __assign_str(host);\n>> - __entry->status = status;\n>> - __entry->first_error = fe;\n>> - /*\n>> - * Embed the 512B headerlog data for user app retrieval and\n>> - * parsing, but no need to print this in the trace buffer.\n>> - */\n>> - memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n>> - ),\n>> - TP_printk(\"device=%s host=%s status: '%s' first_error: '%s'\",\n>> - __get_str(device), __get_str(host),\n>> - show_uc_errs(__entry->status),\n>> - show_uc_errs(__entry->first_error)\n>> - )\n>> -);\n>> -\n>> -TRACE_EVENT(cxl_aer_uncorrectable_error,\n>> - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status, u32 fe, u32 *hl),\n>> - TP_ARGS(cxlmd, status, fe, hl),\n>> - TP_STRUCT__entry(\n>> - __string(memdev, dev_name(&cxlmd->dev))\n>> - __string(host, dev_name(cxlmd->dev.parent))\n>> __field(u64, serial)\n>> __field(u32, status)\n>> __field(u32, first_error)\n>> __array(u32, header_log, CXL_HEADERLOG_SIZE_U32)\n>> ),\n>> TP_fast_assign(\n>> - __assign_str(memdev);\n>> + __assign_str(device);\n>> __assign_str(host);\n>> - __entry->serial = cxlmd->cxlds->serial;\n>> + __entry->serial = serial;\n>> __entry->status = status;\n>> __entry->first_error = fe;\n>> /*\n>> @@ -99,8 +72,8 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,\n>> */\n>> memcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n>> ),\n>> - TP_printk(\"memdev=%s host=%s serial=%lld: status: '%s' first_error: '%s'\",\n>> - __get_str(memdev), __get_str(host), __entry->serial,\n>> + TP_printk(\"device=%s host=%s serial=%lld status: '%s' first_error: '%s'\",\n>> + __get_str(device), __get_str(host), __entry->serial,\n>> show_uc_errs(__entry->status),\n>> show_uc_errs(__entry->first_error)\n>> )\n>> @@ -124,42 +97,23 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,\n>> { CXL_RAS_CE_PHYS_LAYER_ERR, \"Received Error From Physical Layer\" } \\\n>> )\n>>\n>> -TRACE_EVENT(cxl_port_aer_correctable_error,\n>> - TP_PROTO(struct device *dev, u32 status),\n>> - TP_ARGS(dev, status),\n>> +TRACE_EVENT(cxl_aer_correctable_error,\n>> + TP_PROTO(const struct device *dev, u32 status, u64 serial),\n>> + TP_ARGS(dev, status, serial),\n>> TP_STRUCT__entry(\n>> __string(device, dev_name(dev))\n>> __string(host, dev_name(dev->parent))\n>> - __field(u32, status)\n>> - ),\n>> - TP_fast_assign(\n>> - __assign_str(device);\n>> - __assign_str(host);\n>> - __entry->status = status;\n>> - ),\n>> - TP_printk(\"device=%s host=%s status='%s'\",\n>> - __get_str(device), __get_str(host),\n>> - show_ce_errs(__entry->status)\n>> - )\n>> -);\n>> -\n>> -TRACE_EVENT(cxl_aer_correctable_error,\n>> - TP_PROTO(const struct cxl_memdev *cxlmd, u32 status),\n>> - TP_ARGS(cxlmd, status),\n>> - TP_STRUCT__entry(\n>> - __string(memdev, dev_name(&cxlmd->dev))\n>> - __string(host, dev_name(cxlmd->dev.parent))\n>> __field(u64, serial)\n>> __field(u32, status)\n>> ),\n>> TP_fast_assign(\n>> - __assign_str(memdev);\n>> + __assign_str(device);\n>> __assign_str(host);\n>> - __entry->serial = cxlmd->cxlds->serial;\n>> + __entry->serial = serial;\n>> __entry->status = status;\n>> ),\n>> - TP_printk(\"memdev=%s host=%s serial=%lld: status: '%s'\",\n>> - __get_str(memdev), __get_str(host), __entry->serial,\n>> + TP_printk(\"device=%s host=%s serial=%lld status: '%s'\",\n>> + __get_str(device), __get_str(host), __entry->serial,\n>> show_ce_errs(__entry->status)\n>> )\n>> );\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=Q6MN/bij;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n 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linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,\n linux-doc@vger.kernel.org, Mauro Carvalho Chehab ","References":"<20260505173029.2718246-1-terry.bowman@amd.com>\n <20260505173029.2718246-3-terry.bowman@amd.com>\n <20260507190836.70197e24@jic23-huawei>","Content-Language":"en-US","From":"\"Bowman, Terry\" ","In-Reply-To":"<20260507190836.70197e24@jic23-huawei>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit","X-ClientProxiedBy":"CH0PR08CA0014.namprd08.prod.outlook.com\n (2603:10b6:610:33::19) To CH8PR12MB9766.namprd12.prod.outlook.com\n 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Cameron","email":"jic23@kernel.org"},"content":"On Thu, 7 May 2026 13:33:45 -0500\n\"Bowman, Terry\" wrote:\n\n> On 5/7/2026 1:08 PM, Jonathan Cameron wrote:\n> > [Some people who received this message don't often get email from jic23@kernel.org. Learn why this is important at https://aka.ms/LearnAboutSenderIdentification ]\n> > \n> > On Tue, 5 May 2026 12:30:20 -0500\n> > Terry Bowman wrote:\n> > \n> >> From: Dan Williams \n> > \n> > +CC Mauro - rasdaemon related - see below.\n> > \n> >>\n> >> CXL protocol error logging uses two parallel sets of trace events. The\n> >> cxl_port_aer_correctable_error() and cxl_port_aer_uncorrectable_error()\n> >> events are used by CPER for CXL Port devices. The cxl_aer_correctable_error()\n> >> and cxl_aer_uncorrectable_error() events are used for CXL Endpoints. Update\n> >> the trace routines to use the latter for all CXL devices on both the CPER\n> >> and native AER paths.\n> >>\n> >> Generalize cxl_aer_correctable_error()/cxl_aer_uncorrectable_error to\n> >> take a struct device * and a u64 serial argument supplied by the caller.\n> >> cxl_handle_ras() and cxl_handle_cor_ras() gain the new u64 serial parameter,\n> >> sourced from pci_get_dsn().\n> >>\n> >> The CPER path keeps its existing Port-vs-Endpoint dispatch and passes the\n> >> new arguments to the unified trace events. The CPER path will be folded\n> >> together in a following patch.\n> >>\n> >> Remove the now-unused cxl_port_aer_correctable_error() and\n> >> cxl_port_aer_uncorrectable_error().\n> >>\n> >> **WARNING: ABI BREAK**\n> >> Rename the trace event field \"memdev\" to \"device\" so all CXL device types\n> >> (Ports and Endpoints) can be reported under a common field name. Note this\n> >> is an ABI break for userspace tools that key off the old \"memdev\" field.\n> >> Specifically, rasdaemon's ras-cxl-handler.c looks up \"memdev\" and bails on\n> >> NULL, so an unmodified rasdaemon will drop every CXL CE/UCE event once this\n> >> kernel ships. A rasdaemon update is needed in a separate series.\n> >>\n> >> The need for the field rename was discussed in v16 review [1]. \n> > \n> > This concerns me (sorry I wasn't paying attention to the v16 thread).\n> > It is a userspace regression against code that is out in the wild and typically\n> > not updated in sync with the kernel.\n> > \n> > If you are suggesting breaking ras-daemon at the very least +CC the maintainer.\n> > \n> > To get to a unified tracepoint add a new one that does what you want, but\n> > maintain the existing ones as well. Userspace can then migrate and maybe\n> > in 5+ years time we can delete the non unified ones.\n> > \n> > No actually comments on the code, just left it all here for Mauro,\n> > \n> > Thanks,\n> > \n> > Jonathan\n> > \n> \n> Dan was clear about using a single set of CE and UE handlers for all CXL RAS \n> protocol errors. While I understand there may be concerns, please direct any \n> objections to Dan and clarify what changes are required to avoid this \n> repeatedly going back and forth.\n> \n> [1] https://lore.kernel.org/linux-cxl/69cb2d5ba3111_178904100b7@dwillia2-mobl4.notmuch/\n\nSure - Dan's on this thread so I'm sure he'll see it sooner or later.\n\nPerhaps I'm missing something that makes this less critical than it appears.\n\nYou can have a single set of handlers, but at the point of spitting the actual\ntracepoints out we need to keep spitting the old ones (+ possibly a new unified\none if you want to one day get rid of the separation.) Bit fiddly but seems\nunlikely to be that bad. e.g. put a wrapper where you currently have\ntrace_cxl_aer_uncorrectable_error() and have that omit the new and old (based\non device type) tracepoints. Then when we eventually drop this after enough\nyears that we can be sure the new one is in use, the code cleanup is all in\none place.\n\nNote this issue isn't a \"maybe\" thing - we are talking userspace ABI breakage\nin an interface known to be in use in commonly used software that is not\ntypically updated in time with the kernel cadence. There have been arguments\nthat some trace points are not 'stable' but that definitely isn't the case for\nthe RAS ones which are the main interface from kernel to userspace tooling.\n\nIn theory you could make such a change and maybe get away with it (on basis\na regression only exists if anyone notices) but you'd need ALL the distros\non board that ship rasdaemon + if you really don't want to end up reverting\nyou'd have to work closely with the hyperscalers who might decide to throw a\n'regression + revert' request at the list which either means a scramble to\nput in place what I describe above, or this series being reverted. Note there\nare downstream forks of rasdaemon to content with as well.\n\nThat pain just isn't worth it.\n\nMauro, any idea if any distros scan for RAS tracepoints for compatibility breakage?\nThey probably should like they do of ioctls and similar but no idea if anyone\nactually does yet. If they do we'd get the revert request pretty quickly...\nIf not we get to wait for some one to hit it in a functional test \n- thankfully RAS paths are definitely in those test sets but they tend to\nrun later and hence when a revert / fix is more painful.\n\nJonathan","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=azCZp9bY;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c0a:e001:db::12fc:5321; helo=sea.lore.kernel.org;\n envelope-from=linux-pci+bounces-54252-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=\"azCZp9bY\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=10.30.226.201"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org\n [IPv6:2600:3c0a:e001:db::12fc:5321])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519 server-signature ECDSA (secp384r1) server-digest SHA384)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4gBrXG5wgbz1yCg\n\tfor ; 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a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1778249149; c=relaxed/simple;\n\tbh=fLSWRhFbte/FoGtd3CLl6kuuzR05q0bVJXMtb8/dZoQ=;\n\th=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References:\n\t MIME-Version:Content-Type;\n b=u4mwC2jKK5s9xksZqW/Rm/sHBdecUUOo7scYaJR/X92Sra8rJyxbl1RsA7HeSPqm3/iZ6uHjlkQUx/3R3fftGJ1s8isYjC0GWkWH0VhuepAcmt2LtRsJQ0LunbyMdEKLm2+5SUi+WY5oDTKtwvCiCiWyV7n+bn+7zeURUnYFIrs=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org\n header.b=azCZp9bY; arc=none smtp.client-ip=10.30.226.201","DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1778249148;\n\tbh=fLSWRhFbte/FoGtd3CLl6kuuzR05q0bVJXMtb8/dZoQ=;\n\th=Date:From:To:Cc:Subject:In-Reply-To:References:From;\n\tb=azCZp9bY7pIL0ZVlrNrdlWPTXcJv4fzF9Uk04rSH3jltcVSM+ccR6e/ow/l5kyVo3\n\t y468mDk1Zo30ojuwGUsq38OEQiyh+PP92U6wEgTcMRkAdObaeSb/c9NOYHTCID/5xv\n\t uAZL1s7VndRqTfTfIdVIxI3IEUD0O12zPgaQIuzxM6QDfrOoyYv22skmC4Cdy2/Ht2\n\t V6IhZOMrWMkeAMxfeu9RHeyWqkrHKkRI4dnFjh69j8LK3CEYPUfX8Q5GOaCBFMhkX2\n\t f2Ojgg6uXgvvBXMqB6ckowC8LrYsS9GqML1aTWS/KBd+sMEu68RegCFAfO+t7FwxHC\n\t 1cI4uq/BeT/wQ==","Date":"Fri, 8 May 2026 15:05:33 +0100","From":"Jonathan Cameron ","To":"\"Bowman, Terry\" ","Cc":"dave@stgolabs.net, dave.jiang@intel.com, alison.schofield@intel.com,\n djbw@kernel.org, bhelgaas@google.com, shiju.jose@huawei.com,\n ming.li@zohomail.com, Smita.KoralahalliChannabasappa@amd.com,\n rrichter@amd.com, dan.carpenter@linaro.org,\n PradeepVineshReddy.Kodamati@amd.com, lukas@wunner.de,\n Benjamin.Cheatham@amd.com, sathyanarayanan.kuppuswamy@linux.intel.com,\n vishal.l.verma@intel.com, alucerop@amd.com, ira.weiny@intel.com,\n corbet@lwn.net, rafael@kernel.org, xueshuai@linux.alibaba.com,\n linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org,\n linux-pci@vger.kernel.org, linux-acpi@vger.kernel.org,\n linux-doc@vger.kernel.org, Mauro Carvalho Chehab ","Subject":"Re: [PATCH v17 02/11] cxl/ras: Unify Endpoint and Port AER trace\n events","Message-ID":"<20260508150533.04e19cf9@jic23-huawei>","In-Reply-To":"<8913c666-a343-4717-8ab2-0b8546d1bdfb@amd.com>","References":"<20260505173029.2718246-1-terry.bowman@amd.com>\n\t<20260505173029.2718246-3-terry.bowman@amd.com>\n\t<20260507190836.70197e24@jic23-huawei>\n\t<8913c666-a343-4717-8ab2-0b8546d1bdfb@amd.com>","X-Mailer":"Claws Mail 4.4.0 (GTK 3.24.52; x86_64-pc-linux-gnu)","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; charset=US-ASCII","Content-Transfer-Encoding":"7bit"}},{"id":3688805,"web_url":"http://patchwork.ozlabs.org/comment/3688805/","msgid":"<69feaebd471c3_1b86a100b@djbw-dev.notmuch>","list_archive_url":null,"date":"2026-05-09T03:49:17","subject":"Re: [PATCH v17 02/11] cxl/ras: Unify Endpoint and Port AER trace\n events","submitter":{"id":93110,"url":"http://patchwork.ozlabs.org/api/people/93110/","name":"Dan Williams (nvidia)","email":"djbw@kernel.org"},"content":"Jonathan Cameron wrote:\n> On Thu, 7 May 2026 13:33:45 -0500\n> \"Bowman, Terry\" wrote:\n[..]\n> > > This concerns me (sorry I wasn't paying attention to the v16 thread).\n> > > It is a userspace regression against code that is out in the wild and typically\n> > > not updated in sync with the kernel.\n> > > \n> > > If you are suggesting breaking ras-daemon at the very least +CC the maintainer.\n\nSorry, that was not the intent, see below.\n\n> > > \n> > > To get to a unified tracepoint add a new one that does what you want, but\n> > > maintain the existing ones as well. Userspace can then migrate and maybe\n> > > in 5+ years time we can delete the non unified ones.\n> > > \n> > > No actually comments on the code, just left it all here for Mauro,\n> > > \n> > > Thanks,\n> > > \n> > > Jonathan\n> > > \n> > \n> > Dan was clear about using a single set of CE and UE handlers for all CXL RAS \n> > protocol errors. While I understand there may be concerns, please direct any \n> > objections to Dan and clarify what changes are required to avoid this \n> > repeatedly going back and forth.\n> > \n> > [1] https://lore.kernel.org/linux-cxl/69cb2d5ba3111_178904100b7@dwillia2-mobl4.notmuch/\n> \n> Sure - Dan's on this thread so I'm sure he'll see it sooner or later.\n> \n> Perhaps I'm missing something that makes this less critical than it appears.\n\nNo, it is breakage and a thinko on my part on the advice to Terry on the\nbackwards compatibility rules for tracepoints. At the time I was only\ntracking data type and order of the payload. I.e. string at same\nposition. However, the name of the argument is ABI.\n\nSomething like this incremental fixup I think gets this back on track.\nIt keeps legacy ABI support for \"memdev\" field in the payload. It\nincrementally lets updated userspace understand \"port\" and \"dport\"\nevents. It stops us from growing a new set of events just to update the\narguments. It enhances the CPER events to now handle switch ports in\naddition to endpoint ports.\n\nThe bulk of the change is passing @port and @dport to the CXL trace\nevents instead of a plain @dev.\n\n-- >8 --\ndiff --git a/drivers/cxl/core/core.h b/drivers/cxl/core/core.h\nindex ff39985d363f..ed3a56966369 100644\n--- a/drivers/cxl/core/core.h\n+++ b/drivers/cxl/core/core.h\n@@ -183,9 +183,10 @@ static inline struct device *dport_to_host(struct cxl_dport *dport)\n #ifdef CONFIG_CXL_RAS\n int cxl_ras_init(void);\n void cxl_ras_exit(void);\n-bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base);\n-void cxl_handle_cor_ras(struct device *dev, u64 serial,\n-\t\t\tvoid __iomem *ras_base);\n+bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, u64 serial,\n+\t\t void __iomem *ras_base);\n+void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport,\n+\t\t\tu64 serial, void __iomem *ras_base);\n void cxl_dport_map_rch_aer(struct cxl_dport *dport);\n void cxl_disable_rch_root_ints(struct cxl_dport *dport);\n void cxl_handle_rdport_errors(struct pci_dev *pdev);\ndiff --git a/drivers/cxl/core/trace.h b/drivers/cxl/core/trace.h\nindex 6f3957b3c3af..3857d2fc279d 100644\n--- a/drivers/cxl/core/trace.h\n+++ b/drivers/cxl/core/trace.h\n@@ -49,20 +49,24 @@\n )\n \n TRACE_EVENT(cxl_aer_uncorrectable_error,\n-\tTP_PROTO(const struct device *dev, u32 status, u32 fe, u32 *hl,\n-\t\t u64 serial),\n-\tTP_ARGS(dev, status, fe, hl, serial),\n+\tTP_PROTO(struct cxl_port *port, struct cxl_dport *dport, u32 status,\n+\t\t u32 fe, u32 *hl, u64 serial),\n+\tTP_ARGS(port, dport, status, fe, hl, serial),\n \tTP_STRUCT__entry(\n-\t\t__string(device, dev_name(dev))\n-\t\t__string(host, dev_name(dev->parent))\n+\t\t__string(memdev, cxl_trace_memdev_name(port))\n+\t\t__string(host, cxl_trace_host_name(port))\n \t\t__field(u64, serial)\n \t\t__field(u32, status)\n \t\t__field(u32, first_error)\n \t\t__array(u32, header_log, CXL_HEADERLOG_SIZE_U32)\n+\t\t__string(port, cxl_trace_port_name(port))\n+\t\t__string(dport, cxl_trace_dport_name(dport))\n \t),\n \tTP_fast_assign(\n-\t\t__assign_str(device);\n+\t\t__assign_str(memdev);\n \t\t__assign_str(host);\n+\t\t__assign_str(port);\n+\t\t__assign_str(dport);\n \t\t__entry->serial = serial;\n \t\t__entry->status = status;\n \t\t__entry->first_error = fe;\n@@ -72,8 +76,9 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,\n \t\t */\n \t\tmemcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n \t),\n-\tTP_printk(\"device=%s host=%s serial=%lld status: '%s' first_error: '%s'\",\n-\t\t __get_str(device), __get_str(host), __entry->serial,\n+\tTP_printk(\"memdev=%s port=%s dport=%s host=%s serial=%lld status: '%s' first_error: '%s'\",\n+\t\t __get_str(memdev), __get_str(port), __get_str(dport),\n+\t\t __get_str(host), __entry->serial,\n \t\t show_uc_errs(__entry->status),\n \t\t show_uc_errs(__entry->first_error)\n \t)\n@@ -98,22 +103,27 @@ TRACE_EVENT(cxl_aer_uncorrectable_error,\n )\n \n TRACE_EVENT(cxl_aer_correctable_error,\n-\tTP_PROTO(const struct device *dev, u32 status, u64 serial),\n-\tTP_ARGS(dev, status, serial),\n+\tTP_PROTO(struct cxl_port *port, struct cxl_dport *dport, u32 status, u64 serial),\n+\tTP_ARGS(port, dport, status, serial),\n \tTP_STRUCT__entry(\n-\t\t__string(device, dev_name(dev))\n-\t\t__string(host, dev_name(dev->parent))\n+\t\t__string(memdev, cxl_trace_memdev_name(port))\n+\t\t__string(host, cxl_trace_host_name(port))\n \t\t__field(u64, serial)\n \t\t__field(u32, status)\n+\t\t__string(port, cxl_trace_port_name(port))\n+\t\t__string(dport, cxl_trace_dport_name(dport))\n \t),\n \tTP_fast_assign(\n-\t\t__assign_str(device);\n+\t\t__assign_str(memdev);\n+\t\t__assign_str(port);\n+\t\t__assign_str(dport);\n \t\t__assign_str(host);\n \t\t__entry->serial = serial;\n \t\t__entry->status = status;\n \t),\n-\tTP_printk(\"device=%s host=%s serial=%lld status: '%s'\",\n-\t\t __get_str(device), __get_str(host), __entry->serial,\n+\tTP_printk(\"memdev=%s port=%s dport=%s host=%s serial=%lld status: '%s'\",\n+\t\t __get_str(memdev), __get_str(port), __get_str(dport),\n+\t\t __get_str(host), __entry->serial,\n \t\t show_ce_errs(__entry->status)\n \t)\n );\ndiff --git a/drivers/cxl/cxlmem.h b/drivers/cxl/cxlmem.h\nindex 776c50d1db51..83e161d48405 100644\n--- a/drivers/cxl/cxlmem.h\n+++ b/drivers/cxl/cxlmem.h\n@@ -101,6 +101,12 @@ static inline bool is_cxl_endpoint(struct cxl_port *port)\n \treturn is_cxl_memdev(port->uport_dev);\n }\n \n+/* trace-event helpers */\n+const char *cxl_trace_memdev_name(struct cxl_port *port);\n+const char *cxl_trace_host_name(struct cxl_port *port);\n+const char *cxl_trace_port_name(struct cxl_port *port);\n+const char *cxl_trace_dport_name(struct cxl_dport *dport);\n+\n struct cxl_memdev *__devm_cxl_add_memdev(struct cxl_dev_state *cxlds,\n \t\t\t\t\t const struct cxl_memdev_attach *attach);\n struct cxl_memdev *devm_cxl_add_memdev(struct cxl_dev_state *cxlds,\ndiff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\nindex b45e2b539b5f..33e78f155916 100644\n--- a/drivers/cxl/core/ras.c\n+++ b/drivers/cxl/core/ras.c\n@@ -8,16 +8,20 @@\n #include \n #include \"trace.h\"\n \n-static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev, u64 serial,\n-\t\t\t\t\t struct cxl_ras_capability_regs *ras_cap)\n+static void\n+cxl_cper_trace_corr_prot_err(struct cxl_port *port, struct cxl_dport *dport,\n+\t\t\t u64 serial,\n+\t\t\t struct cxl_ras_capability_regs *ras_cap)\n {\n \tu32 status = ras_cap->cor_status & ~ras_cap->cor_mask;\n \n-\ttrace_cxl_aer_correctable_error(&pdev->dev, status, serial);\n+\ttrace_cxl_aer_correctable_error(port, dport, status, serial);\n }\n \n-static void cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev, u64 serial,\n-\t\t\t\t\t struct cxl_ras_capability_regs *ras_cap)\n+static void\n+cxl_cper_trace_uncorr_prot_err(struct cxl_port *port, struct cxl_dport *dport,\n+\t\t\t u64 serial,\n+\t\t\t struct cxl_ras_capability_regs *ras_cap)\n {\n \tu32 status = ras_cap->uncor_status & ~ras_cap->uncor_mask;\n \tu32 fe;\n@@ -28,10 +32,12 @@ static void cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev, u64 serial,\n \telse\n \t\tfe = status;\n \n-\ttrace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe,\n+\ttrace_cxl_aer_uncorrectable_error(port, dport, status, fe,\n \t\t\t\t\t ras_cap->header_log, serial);\n }\n \n+static struct cxl_port *find_cxl_port_by_dev(struct device *dev, struct cxl_dport **dport);\n+\n void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n {\n \tunsigned int devfn = PCI_DEVFN(data->prot_err.agent_addr.device,\n@@ -40,19 +46,26 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n \t\tpci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment,\n \t\t\t\t\t data->prot_err.agent_addr.bus,\n \t\t\t\t\t devfn);\n+\tstruct cxl_dport *dport;\n \n \tif (!pdev)\n \t\treturn;\n \n-\tguard(device)(&pdev->dev);\n-\tif (!pdev->dev.driver)\n+\tstruct cxl_port *port __free(put_cxl_port) =\n+\t\tfind_cxl_port_by_dev(&pdev->dev, &dport);\n+\n+\tif (!port)\n+\t\treturn;\n+\n+\tguard(device)(&port->dev);\n+\tif (!port->dev.driver)\n \t\treturn;\n \n \tif (data->severity == AER_CORRECTABLE)\n-\t\tcxl_cper_trace_corr_prot_err(pdev, pci_get_dsn(pdev),\n+\t\tcxl_cper_trace_corr_prot_err(port, dport, pci_get_dsn(pdev),\n \t\t\t\t\t &data->ras_cap);\n \telse\n-\t\tcxl_cper_trace_uncorr_prot_err(pdev, pci_get_dsn(pdev),\n+\t\tcxl_cper_trace_uncorr_prot_err(port, dport, pci_get_dsn(pdev),\n \t\t\t\t\t &data->ras_cap);\n }\n EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err);\n@@ -222,13 +235,12 @@ static void __iomem *to_ras_base(struct cxl_port *port, struct cxl_dport *dport)\n \n static void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct cxl_dport *dport)\n {\n-\tstruct device *dev = &pdev->dev;\n \tbool ue;\n \n \tif (pci_dev_is_disconnected(pdev))\n \t\tpanic(\"CXL cachemem error: device disconnected during UE recovery\");\n \n-\tue = cxl_handle_ras(dev, pci_get_dsn(pdev),\n+\tue = cxl_handle_ras(port, dport, pci_get_dsn(pdev),\n \t\t\t to_ras_base(port, dport));\n \tif (ue)\n \t\tpanic(\"CXL cachemem error.\");\n@@ -238,7 +250,8 @@ static void cxl_do_recovery(struct pci_dev *pdev, struct cxl_port *port, struct\n \tpci_aer_clear_fatal_status(pdev);\n }\n \n-void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n+void cxl_handle_cor_ras(struct cxl_port *port, struct cxl_dport *dport,\n+\t\t\tu64 serial, void __iomem *ras_base)\n {\n \tvoid __iomem *addr;\n \tu32 status;\n@@ -250,7 +263,7 @@ void cxl_handle_cor_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n \tstatus = readl(addr);\n \tif (status & CXL_RAS_CORRECTABLE_STATUS_MASK) {\n \t\twritel(status & CXL_RAS_CORRECTABLE_STATUS_MASK, addr);\n-\t\ttrace_cxl_aer_correctable_error(dev, status, serial);\n+\t\ttrace_cxl_aer_correctable_error(port, dport, status, serial);\n \t}\n }\n \n@@ -275,7 +288,8 @@ static void header_log_copy(void __iomem *ras_base, u32 *log)\n * Log the state of the RAS status registers and prepare them to log the\n * next error status. Return 1 if reset needed.\n */\n-bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n+bool cxl_handle_ras(struct cxl_port *port, struct cxl_dport *dport, u64 serial,\n+\t\t void __iomem *ras_base)\n {\n \tu32 hl[CXL_HEADERLOG_SIZE_U32];\n \tvoid __iomem *addr;\n@@ -302,7 +316,7 @@ bool cxl_handle_ras(struct device *dev, u64 serial, void __iomem *ras_base)\n \t}\n \n \theader_log_copy(ras_base, hl);\n-\ttrace_cxl_aer_uncorrectable_error(dev, status, fe, hl, serial);\n+\ttrace_cxl_aer_uncorrectable_error(port, dport, status, fe, hl, serial);\n \twritel(status & CXL_RAS_UNCORRECTABLE_STATUS_MASK, addr);\n \n \treturn true;\n@@ -358,7 +372,7 @@ static void cxl_handle_proto_error(struct pci_dev *pdev, struct cxl_port *port,\n \t\tcxl_handle_rdport_errors(pdev);\n \n \tif (severity == AER_CORRECTABLE) {\n-\t\tcxl_handle_cor_ras(&pdev->dev, pci_get_dsn(pdev),\n+\t\tcxl_handle_cor_ras(port, dport, pci_get_dsn(pdev),\n \t\t\t\t to_ras_base(port, dport));\n \t\tpcie_clear_device_status(pdev);\n \t} else {\ndiff --git a/drivers/cxl/core/ras_rch.c b/drivers/cxl/core/ras_rch.c\nindex cbd02cabefbc..1bcd3c491aaa 100644\n--- a/drivers/cxl/core/ras_rch.c\n+++ b/drivers/cxl/core/ras_rch.c\n@@ -113,9 +113,8 @@ void cxl_handle_rdport_errors(struct pci_dev *pdev)\n \n \tpci_print_aer(pdev, severity, &aer_regs);\n \tif (severity == AER_CORRECTABLE)\n-\t\tcxl_handle_cor_ras(&pdev->dev, pci_get_dsn(pdev),\n+\t\tcxl_handle_cor_ras(port, dport, pci_get_dsn(pdev),\n \t\t\t\t dport->regs.ras);\n \telse\n-\t\tcxl_handle_ras(&pdev->dev, pci_get_dsn(pdev),\n-\t\t\t dport->regs.ras);\n+\t\tcxl_handle_ras(port, dport, pci_get_dsn(pdev), dport->regs.ras);\n }\ndiff --git a/drivers/cxl/core/trace.c b/drivers/cxl/core/trace.c\nindex 7f2a9dd0d0e3..df42d119c53d 100644\n--- a/drivers/cxl/core/trace.c\n+++ b/drivers/cxl/core/trace.c\n@@ -2,7 +2,42 @@\n /* Copyright(c) 2022 Intel Corporation. All rights reserved. */\n \n #include \n+#include \n #include \"core.h\"\n \n+const char *cxl_trace_memdev_name(struct cxl_port *port)\n+{\n+\tif (is_cxl_endpoint(port)) {\n+\t\tstruct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);\n+\n+\t\treturn dev_name(&cxlmd->dev);\n+\t}\n+\n+\treturn \"\";\n+}\n+\n+const char *cxl_trace_host_name(struct cxl_port *port)\n+{\n+\tif (is_cxl_endpoint(port)) {\n+\t\tstruct cxl_memdev *cxlmd = to_cxl_memdev(port->uport_dev);\n+\n+\t\treturn dev_name(cxlmd->dev.parent);\n+\t}\n+\n+\treturn dev_name(port->uport_dev);\n+}\n+\n+const char *cxl_trace_port_name(struct cxl_port *port)\n+{\n+\treturn dev_name(&port->dev);\n+}\n+\n+const char *cxl_trace_dport_name(struct cxl_dport *dport)\n+{\n+\tif (dport)\n+\t\treturn dev_name(dport->dport_dev);\n+\treturn \"\";\n+}\n+\n #define CREATE_TRACE_POINTS\n #include \"trace.h\"","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=uAGMGVdJ;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; 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