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GET /api/1.2/patches/2233121/?format=api
{ "id": 2233121, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2233121/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260505173029.2718246-4-terry.bowman@amd.com/", "project": { "id": 28, "url": "http://patchwork.ozlabs.org/api/1.2/projects/28/?format=api", "name": "Linux PCI development", "link_name": "linux-pci", "list_id": "linux-pci.vger.kernel.org", "list_email": "linux-pci@vger.kernel.org", "web_url": null, "scm_url": null, "webscm_url": null, "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260505173029.2718246-4-terry.bowman@amd.com>", "list_archive_url": null, "date": "2026-05-05T17:30:21", "name": "[v17,03/11] cxl: Use common CPER handling for all CXL devices", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "8eeebcf976b00a21674c9af317ca5090023d0302", "submitter": { "id": 82124, "url": "http://patchwork.ozlabs.org/api/1.2/people/82124/?format=api", "name": "Bowman, Terry", "email": "Terry.Bowman@amd.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-pci/patch/20260505173029.2718246-4-terry.bowman@amd.com/mbox/", "series": [ { "id": 502875, "url": "http://patchwork.ozlabs.org/api/1.2/series/502875/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-pci/list/?series=502875", "date": "2026-05-05T17:30:19", "name": "Enable CXL PCIe Port Protocol Error handling and logging", "version": 17, "mbox": "http://patchwork.ozlabs.org/series/502875/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2233121/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2233121/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-pci+bounces-53767-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-pci@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=amd.com header.i=@amd.com header.a=rsa-sha256\n header.s=selector1 header.b=SMAJxOXG;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c04:e001:36c::12fc:5321; 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helo=satlexmb07.amd.com; pr=C", "From": "Terry Bowman <terry.bowman@amd.com>", "To": "<dave@stgolabs.net>, <jic23@kernel.org>, <dave.jiang@intel.com>,\n\t<alison.schofield@intel.com>, <djbw@kernel.org>, <bhelgaas@google.com>,\n\t<shiju.jose@huawei.com>, <ming.li@zohomail.com>,\n\t<Smita.KoralahalliChannabasappa@amd.com>, <rrichter@amd.com>,\n\t<dan.carpenter@linaro.org>, <PradeepVineshReddy.Kodamati@amd.com>,\n\t<lukas@wunner.de>, <Benjamin.Cheatham@amd.com>,\n\t<sathyanarayanan.kuppuswamy@linux.intel.com>, <vishal.l.verma@intel.com>,\n\t<alucerop@amd.com>, <ira.weiny@intel.com>, <corbet@lwn.net>,\n\t<rafael@kernel.org>, <xueshuai@linux.alibaba.com>,\n\t<linux-cxl@vger.kernel.org>", "CC": "<linux-kernel@vger.kernel.org>, <linux-pci@vger.kernel.org>,\n\t<linux-acpi@vger.kernel.org>, <linux-doc@vger.kernel.org>,\n\t<terry.bowman@amd.com>", "Subject": "[PATCH v17 03/11] cxl: Use common CPER handling for all CXL devices", "Date": "Tue, 5 May 2026 12:30:21 -0500", "Message-ID": "<20260505173029.2718246-4-terry.bowman@amd.com>", "X-Mailer": "git-send-email 2.34.1", "In-Reply-To": "<20260505173029.2718246-1-terry.bowman@amd.com>", "References": "<20260505173029.2718246-1-terry.bowman@amd.com>", "Precedence": "bulk", "X-Mailing-List": "linux-pci@vger.kernel.org", "List-Id": "<linux-pci.vger.kernel.org>", "List-Subscribe": "<mailto:linux-pci+subscribe@vger.kernel.org>", "List-Unsubscribe": "<mailto:linux-pci+unsubscribe@vger.kernel.org>", "MIME-Version": "1.0", "Content-Transfer-Encoding": "7bit", "Content-Type": "text/plain", "X-ClientProxiedBy": "satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com\n (10.181.42.216)", "X-EOPAttributedMessage": "0", "X-MS-PublicTrafficType": "Email", "X-MS-TrafficTypeDiagnostic": "DM2PEPF00003FC9:EE_|IA0PR12MB8227:EE_", "X-MS-Office365-Filtering-Correlation-Id": "5f974037-25d9-43dd-27d3-08deaacc206f", "X-MS-Exchange-SenderADCheck": "1", "X-MS-Exchange-AntiSpam-Relay": "0", "X-Microsoft-Antispam": "\n\tBCL:0;ARA:13230040|36860700016|82310400026|1800799024|7416014|376014|921020|56012099003|18002099003|22082099003;", "X-Microsoft-Antispam-Message-Info": "\n\tr9qTtFtYu9tbJbcxUSlpHdSU8OyjDcDv0T661U7yH/t352qA0zaZdPweMeunOLIPpznDFXouI9RaoontexS/cu5UkvdbFnhVNQpLK9RTxvflxQmaGQqltEY7C6mYh/zkBchOZvNP6W+X1gs/r2OegVcLE2eAya4J1vmCVjP46ejf2eXswL90uLIN6ik69T1mKG2hjrb3XJLitQXqDF2GWO9VPjqAHl7lW9U2xNyKI32ohtztvdk2CpCCq+yNN7p6j8kKTDTZGtHmEhxtcDVugRUfoBE2FyyWxog4YoSHlcpgvkPXBnln8/6rjHnwY6Wyf4Dr+kfyW4eROPi/O18PO0pYl90r5ynSza2k+BSz+Hu6Dwc+Hi+KNTb35GXa6qqG5GHcVbuv/N3ULoTVkCNs2UZXVxw7GJ54wEJW6+GkDqfhAcJgU+fMKyF8uVDgt6gwPQCGfJaeB164iLNKxD6WLcS4bLVvZtD7m22iRT39dYw1gEqVXgZU+XvlUKeXBChDaNu/MLRZvWQaz8c2WdN0vzGpZvr2j2ThHUxlAEm7E3Su1p/NI/1/8qHEDHSMbV3KUQiPyhFRu5KYf9aCZygmYOj/Lqpf4YQgECQnO+tSf672Rj0nZkKQeFqSBJ1+ULF85/xz1RqzfYVraB+Ha2vMt0azG+1aLJnQZFVzcDNu48WGC2Pctxz3+ReHSEqDw0S8Nf4v1QJpNrJQlLo3YxrhFByktAN85CD6cbTV3qBDtS3eJTLVnk78uiEXEa7xx5cIieo411qwaZnXAx2pA64yAw==", "X-Forefront-Antispam-Report": "\n\tCIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb07.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(36860700016)(82310400026)(1800799024)(7416014)(376014)(921020)(56012099003)(18002099003)(22082099003);DIR:OUT;SFP:1101;", "X-MS-Exchange-AntiSpam-MessageData-ChunkCount": "1", "X-MS-Exchange-AntiSpam-MessageData-0": "\n\t2p7X9UHExeYcToeKRtcou3hQFxEHUURcmgF8+NfzAvsAwXItBQ5NU3F4WvuSqXlcr5Tq0BZRFDFVkm5XAWETgdJdY1LjG58tIPjN7rqk9ak/nD+s2SABV78psCuVsB590DOMX8Jib4un4CdSPeVFLWPouVegRQprrx7yzO7L31HsKI/x8lVU3JEHj5zWmFTdcfyVgswbkKt9533AvJZ3RpSER7eWcRMi08y7yg2+C/zwJS5V2eTnI4wpnmdG2CaDI9vRafl6ARmRhKzAKYrmsxfv1i7zTDtJ4nmh8R5Que72d/cD+SdwzL1wXQnyjB5TI/L8lLKK5NU2AqPF+4vcfMtYr7KrbZZrgoQ51G2vHGc2pnA2HyvCnLfOnYaU8jxG5aya0hozUe/gi6A9ZBpNCxxBTnKCkukmfNIWPLDSmY868cYUgGSmYYluS2u2Iyet", "X-OriginatorOrg": "amd.com", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "05 May 2026 17:31:22.6951\n (UTC)", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 5f974037-25d9-43dd-27d3-08deaacc206f", "X-MS-Exchange-CrossTenant-Id": "3dd8961f-e488-4e60-8e11-a82d994e183d", "X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp": "\n TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com]", "X-MS-Exchange-CrossTenant-AuthSource": "\n\tDM2PEPF00003FC9.namprd04.prod.outlook.com", "X-MS-Exchange-CrossTenant-AuthAs": "Anonymous", "X-MS-Exchange-CrossTenant-FromEntityHeader": "HybridOnPrem", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "IA0PR12MB8227" }, "content": "Fold the Port and Endpoint specific paths in cxl_cper_handle_prot_err()\ninto a single code path. Drop the PCI type dispatch block as both Port\nand Endpoint devices now go through the same code path.\n\nExtend the pdev->dev.driver != NULL gate to Port devices, which previously\nbypassed it. This check and the existing device lock will ensure the CXL\ndevice remains accessible while in scope.\n\nRecent trace event changes generalize the interface to take a\nstruct device * for all CXL devices. Update the Endpoint CPER path\nto pass &pdev->dev (the PCI device) instead of &cxlmd->dev (the\nmemdev). This makes the trace event's \"device=\" field show the PCI\nBDF for all CPER callers, replacing the prior \"device=memN\" output\nfor Endpoints. Userspace consumers correlating CPER trace events to\nmemdev names must map the PCI BDF back via /sys/bus/cxl/devices/.\n\nRemove the bus_find_device(&cxl_bus_type, ..., match_memdev_by_parent)\nlookup along with the match_memdev_by_parent() helper.\n\nSigned-off-by: Terry Bowman <terry.bowman@amd.com>\n\n---\n\nChanges in v16->v17:\n- New commit\n---\n drivers/cxl/core/ras.c | 81 +++++++-----------------------------------\n 1 file changed, 13 insertions(+), 68 deletions(-)", "diff": "diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\nindex d7081caaf5d3..56611da8357a 100644\n--- a/drivers/cxl/core/ras.c\n+++ b/drivers/cxl/core/ras.c\n@@ -8,65 +8,28 @@\n #include <cxlpci.h>\n #include \"trace.h\"\n \n-static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev,\n-\t\t\t\t\t struct cxl_ras_capability_regs ras_cap)\n+static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev, u64 serial,\n+\t\t\t\t\t struct cxl_ras_capability_regs *ras_cap)\n {\n-\tu32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n+\tu32 status = ras_cap->cor_status & ~ras_cap->cor_mask;\n \n-\ttrace_cxl_aer_correctable_error(&pdev->dev, status, pci_get_dsn(pdev));\n+\ttrace_cxl_aer_correctable_error(&pdev->dev, status, serial);\n }\n \n-static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n-\t\t\t\t\t\tstruct cxl_ras_capability_regs ras_cap)\n+static void cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev, u64 serial,\n+\t\t\t\t\t struct cxl_ras_capability_regs *ras_cap)\n {\n-\tu32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;\n+\tu32 status = ras_cap->uncor_status & ~ras_cap->uncor_mask;\n \tu32 fe;\n \n \tif (hweight32(status) > 1)\n \t\tfe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,\n-\t\t\t\t ras_cap.cap_control));\n+\t\t\t\t ras_cap->cap_control));\n \telse\n \t\tfe = status;\n \n \ttrace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe,\n-\t\t\t\t\t ras_cap.header_log,\n-\t\t\t\t\t pci_get_dsn(pdev));\n-}\n-\n-static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev,\n-\t\t\t\t\t struct cxl_memdev *cxlmd,\n-\t\t\t\t\t struct cxl_ras_capability_regs ras_cap)\n-{\n-\tu32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n-\n-\ttrace_cxl_aer_correctable_error(&cxlmd->dev, status,\n-\t\t\t\t\tpci_get_dsn(pdev));\n-}\n-\n-static void\n-cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev,\n-\t\t\t struct cxl_memdev *cxlmd,\n-\t\t\t struct cxl_ras_capability_regs ras_cap)\n-{\n-\tu32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;\n-\tu32 fe;\n-\n-\tif (hweight32(status) > 1)\n-\t\tfe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,\n-\t\t\t\t ras_cap.cap_control));\n-\telse\n-\t\tfe = status;\n-\n-\ttrace_cxl_aer_uncorrectable_error(&cxlmd->dev, status, fe,\n-\t\t\t\t\t ras_cap.header_log,\n-\t\t\t\t\t pci_get_dsn(pdev));\n-}\n-\n-static int match_memdev_by_parent(struct device *dev, const void *uport)\n-{\n-\tif (is_cxl_memdev(dev) && dev->parent == uport)\n-\t\treturn 1;\n-\treturn 0;\n+\t\t\t\t\t ras_cap->header_log, serial);\n }\n \n void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n@@ -77,38 +40,20 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n \t\tpci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment,\n \t\t\t\t\t data->prot_err.agent_addr.bus,\n \t\t\t\t\t devfn);\n-\tstruct cxl_memdev *cxlmd;\n-\tint port_type;\n \n \tif (!pdev)\n \t\treturn;\n \n-\tport_type = pci_pcie_type(pdev);\n-\tif (port_type == PCI_EXP_TYPE_ROOT_PORT ||\n-\t port_type == PCI_EXP_TYPE_DOWNSTREAM ||\n-\t port_type == PCI_EXP_TYPE_UPSTREAM) {\n-\t\tif (data->severity == AER_CORRECTABLE)\n-\t\t\tcxl_cper_trace_corr_port_prot_err(pdev, data->ras_cap);\n-\t\telse\n-\t\t\tcxl_cper_trace_uncorr_port_prot_err(pdev, data->ras_cap);\n-\n-\t\treturn;\n-\t}\n-\n \tguard(device)(&pdev->dev);\n \tif (!pdev->dev.driver)\n \t\treturn;\n \n-\tstruct device *mem_dev __free(put_device) = bus_find_device(\n-\t\t&cxl_bus_type, NULL, pdev, match_memdev_by_parent);\n-\tif (!mem_dev)\n-\t\treturn;\n-\n-\tcxlmd = to_cxl_memdev(mem_dev);\n \tif (data->severity == AER_CORRECTABLE)\n-\t\tcxl_cper_trace_corr_prot_err(pdev, cxlmd, data->ras_cap);\n+\t\tcxl_cper_trace_corr_prot_err(pdev, pci_get_dsn(pdev),\n+\t\t\t\t\t &data->ras_cap);\n \telse\n-\t\tcxl_cper_trace_uncorr_prot_err(pdev, cxlmd, data->ras_cap);\n+\t\tcxl_cper_trace_uncorr_prot_err(pdev, pci_get_dsn(pdev),\n+\t\t\t\t\t &data->ras_cap);\n }\n EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err);\n \n", "prefixes": [ "v17", "03/11" ] }