[{"id":3686716,"web_url":"http://patchwork.ozlabs.org/comment/3686716/","msgid":"<20260505213010.234D2C2BCB4@smtp.kernel.org>","list_archive_url":null,"date":"2026-05-05T21:30:09","subject":"Re: [PATCH v17 03/11] cxl: Use common CPER handling for all CXL\n devices","submitter":{"id":93311,"url":"http://patchwork.ozlabs.org/api/people/93311/","name":null,"email":"sashiko-bot@kernel.org"},"content":"Thank you for your contribution! Sashiko AI review found 3 potential issue(s) to consider:\n- [Critical] Stack out-of-bounds read of 448 bytes when copying the CXL header log to the trace event ring buffer, leaking kernel stack memory to userspace.\n- [High] Silent dropping of valid CPER hardware errors for unbound devices.\n- [Medium] Unnecessary device locking based on a flawed premise of object lifetime.\n--\n\ncommit fb7e6f8e6c582af55947d02985f007b61cfc1671\nAuthor: Terry Bowman \n\ncxl: Use common CPER handling for all CXL devices\n\nThis commit unifies the CPER error handling paths for CXL Port and Endpoint\ndevices by removing the PCI-type specific dispatch. It extends the driver\ncheck and device lock to Port devices, and replaces the memdev lookup with\ndirect use of the PCI device for trace events.\n\n> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\n> index d7081caaf5d3f..56611da8357a2 100644\n> --- a/drivers/cxl/core/ras.c\n> +++ b/drivers/cxl/core/ras.c\n\n[ ... ]\n\n> @@ -77,38 +40,20 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n> \t\tpci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment,\n> \t\t\t\t\t data->prot_err.agent_addr.bus,\n> \t\t\t\t\t devfn);\n> -\tstruct cxl_memdev *cxlmd;\n> -\tint port_type;\n> \n> \tif (!pdev)\n> \t\treturn;\n> \n> -\tport_type = pci_pcie_type(pdev);\n> -\tif (port_type == PCI_EXP_TYPE_ROOT_PORT ||\n> -\t port_type == PCI_EXP_TYPE_DOWNSTREAM ||\n> -\t port_type == PCI_EXP_TYPE_UPSTREAM) {\n> -\t\tif (data->severity == AER_CORRECTABLE)\n> -\t\t\tcxl_cper_trace_corr_port_prot_err(pdev, data->ras_cap);\n> -\t\telse\n> -\t\t\tcxl_cper_trace_uncorr_port_prot_err(pdev, data->ras_cap);\n> -\n> -\t\treturn;\n> -\t}\n> -\n> \tguard(device)(&pdev->dev);\n> \tif (!pdev->dev.driver)\n> \t\treturn;\n\nWill this silently drop valid CPER hardware errors for unbound Port devices?\n\nPreviously, the port device dispatch block correctly bypassed the driver check\nfor CXL ports. Since the code only logs the CPER data via tracepoints and\nreads the PCI config space for the DSN, is a bound driver actually required?\n\nAlso, is the device lock necessary here?\n\nThe commit message notes \"the existing device lock will ensure the CXL device\nremains accessible while in scope\". However, object lifetime and accessibility\nof pdev are already guaranteed by the reference count acquired via\npci_get_domain_bus_and_slot(), which is released safely by the\n__free(pci_dev_put) cleanup.\n\n> -\tstruct device *mem_dev __free(put_device) = bus_find_device(\n> -\t\t&cxl_bus_type, NULL, pdev, match_memdev_by_parent);\n> -\tif (!mem_dev)\n> -\t\treturn;\n> -\n> -\tcxlmd = to_cxl_memdev(mem_dev);\n> \tif (data->severity == AER_CORRECTABLE)\n> -\t\tcxl_cper_trace_corr_prot_err(pdev, cxlmd, data->ras_cap);\n> +\t\tcxl_cper_trace_corr_prot_err(pdev, pci_get_dsn(pdev),\n> +\t\t\t\t\t &data->ras_cap);\n> \telse\n> -\t\tcxl_cper_trace_uncorr_prot_err(pdev, cxlmd, data->ras_cap);\n> +\t\tcxl_cper_trace_uncorr_prot_err(pdev, pci_get_dsn(pdev),\n> +\t\t\t\t\t &data->ras_cap);\n\nCan this cause an out-of-bounds read of kernel stack memory?\n\nThe trace event cxl_aer_uncorrectable_error performs a memory copy of the\nheader log:\n\nmemcpy(__entry->header_log, hl, CXL_HEADERLOG_SIZE);\n\nCXL_HEADERLOG_SIZE is 512 bytes, but the hl pointer passed in via\nras_cap->header_log is only a 16-element u32 array (64 bytes) inside\nstruct cxl_ras_capability_regs.\n\nCould this copy 448 bytes of uninitialized stack memory past the array into\nthe userspace trace buffer?","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=kernel.org header.i=@kernel.org header.a=rsa-sha256\n header.s=k20201202 header.b=jWtPqsgL;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c09:e001:a7::12fc:5321; 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a=rsa-sha256; c=relaxed/simple; d=kernel.org;\n\ts=k20201202; t=1778016610;\n\tbh=Fjr0+pe6IKzwNvLCaCHDr61vsV9a45l5edQ0TvHz6PQ=;\n\th=From:Subject:Reply-To:To:Cc:In-Reply-To:References:Date:From;\n\tb=jWtPqsgL9XqaCwbbFd/wE/mhA7HU4335CpqVJ4Lp9mWF2SSPD9R9ECp22iWMfrvbC\n\t nWc1GBQL+Z+mgUYkkd1ukf32/tgqARF2TwIRUegfEaBsV+NrvbGuEERBk/n6vhQjsD\n\t 4+rrdTvRB29qNKG3i5qAiJ+PlJU8XYmKjNe3dNguTtYUQ7XHAFLa5HvV8rKcTkRwQJ\n\t ija2vW0I/P7zonwBFV+106DHBhbRQIjeejWv+t2cXWkU6SSj9KKGuFhM3PT4jKTy06\n\t gjjXufFnHEz7Z4eKcgMmzIFC/FVcN1r4n7isQG6RHPPN4KERwGXM8KPYFhq+vOWKwW\n\t xtv+AdEMSGtaw==","From":"sashiko-bot@kernel.org","Subject":"Re: [PATCH v17 03/11] cxl: Use common CPER handling for all CXL\n devices","Reply-To":"sashiko@lists.linux.dev","To":"\"Terry Bowman\" ","Cc":"linux-pci@vger.kernel.org","In-Reply-To":"<20260505173029.2718246-4-terry.bowman@amd.com>","References":"<20260505173029.2718246-4-terry.bowman@amd.com>","Content-Type":"text/plain; charset=utf-8","Content-Transfer-Encoding":"quoted-printable","Date":"Tue, 05 May 2026 21:30:09 +0000","Message-Id":"<20260505213010.234D2C2BCB4@smtp.kernel.org>","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":""}},{"id":3686737,"web_url":"http://patchwork.ozlabs.org/comment/3686737/","msgid":"","list_archive_url":null,"date":"2026-05-05T22:02:45","subject":"Re: [PATCH v17 03/11] cxl: Use common CPER handling for all CXL\n devices","submitter":{"id":13225,"url":"http://patchwork.ozlabs.org/api/people/13225/","name":"Dave Jiang","email":"dave.jiang@intel.com"},"content":"On 5/5/26 10:30 AM, Terry Bowman wrote:\n> Fold the Port and Endpoint specific paths in cxl_cper_handle_prot_err()\n> into a single code path. Drop the PCI type dispatch block as both Port\n> and Endpoint devices now go through the same code path.\n> \n> Extend the pdev->dev.driver != NULL gate to Port devices, which previously\n> bypassed it. This check and the existing device lock will ensure the CXL\n> device remains accessible while in scope.\n> \n> Recent trace event changes generalize the interface to take a\n> struct device * for all CXL devices. Update the Endpoint CPER path\n> to pass &pdev->dev (the PCI device) instead of &cxlmd->dev (the\n> memdev). This makes the trace event's \"device=\" field show the PCI\n> BDF for all CPER callers, replacing the prior \"device=memN\" output\n> for Endpoints. Userspace consumers correlating CPER trace events to\n> memdev names must map the PCI BDF back via /sys/bus/cxl/devices/.\n> \n> Remove the bus_find_device(&cxl_bus_type, ..., match_memdev_by_parent)\n> lookup along with the match_memdev_by_parent() helper.\n> \n> Signed-off-by: Terry Bowman \n\nReviewed-by: Dave Jiang \n\n\n> \n> ---\n> \n> Changes in v16->v17:\n> - New commit\n> ---\n> drivers/cxl/core/ras.c | 81 +++++++-----------------------------------\n> 1 file changed, 13 insertions(+), 68 deletions(-)\n> \n> diff --git a/drivers/cxl/core/ras.c b/drivers/cxl/core/ras.c\n> index d7081caaf5d3..56611da8357a 100644\n> --- a/drivers/cxl/core/ras.c\n> +++ b/drivers/cxl/core/ras.c\n> @@ -8,65 +8,28 @@\n> #include \n> #include \"trace.h\"\n> \n> -static void cxl_cper_trace_corr_port_prot_err(struct pci_dev *pdev,\n> -\t\t\t\t\t struct cxl_ras_capability_regs ras_cap)\n> +static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev, u64 serial,\n> +\t\t\t\t\t struct cxl_ras_capability_regs *ras_cap)\n> {\n> -\tu32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n> +\tu32 status = ras_cap->cor_status & ~ras_cap->cor_mask;\n> \n> -\ttrace_cxl_aer_correctable_error(&pdev->dev, status, pci_get_dsn(pdev));\n> +\ttrace_cxl_aer_correctable_error(&pdev->dev, status, serial);\n> }\n> \n> -static void cxl_cper_trace_uncorr_port_prot_err(struct pci_dev *pdev,\n> -\t\t\t\t\t\tstruct cxl_ras_capability_regs ras_cap)\n> +static void cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev, u64 serial,\n> +\t\t\t\t\t struct cxl_ras_capability_regs *ras_cap)\n> {\n> -\tu32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;\n> +\tu32 status = ras_cap->uncor_status & ~ras_cap->uncor_mask;\n> \tu32 fe;\n> \n> \tif (hweight32(status) > 1)\n> \t\tfe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,\n> -\t\t\t\t ras_cap.cap_control));\n> +\t\t\t\t ras_cap->cap_control));\n> \telse\n> \t\tfe = status;\n> \n> \ttrace_cxl_aer_uncorrectable_error(&pdev->dev, status, fe,\n> -\t\t\t\t\t ras_cap.header_log,\n> -\t\t\t\t\t pci_get_dsn(pdev));\n> -}\n> -\n> -static void cxl_cper_trace_corr_prot_err(struct pci_dev *pdev,\n> -\t\t\t\t\t struct cxl_memdev *cxlmd,\n> -\t\t\t\t\t struct cxl_ras_capability_regs ras_cap)\n> -{\n> -\tu32 status = ras_cap.cor_status & ~ras_cap.cor_mask;\n> -\n> -\ttrace_cxl_aer_correctable_error(&cxlmd->dev, status,\n> -\t\t\t\t\tpci_get_dsn(pdev));\n> -}\n> -\n> -static void\n> -cxl_cper_trace_uncorr_prot_err(struct pci_dev *pdev,\n> -\t\t\t struct cxl_memdev *cxlmd,\n> -\t\t\t struct cxl_ras_capability_regs ras_cap)\n> -{\n> -\tu32 status = ras_cap.uncor_status & ~ras_cap.uncor_mask;\n> -\tu32 fe;\n> -\n> -\tif (hweight32(status) > 1)\n> -\t\tfe = BIT(FIELD_GET(CXL_RAS_CAP_CONTROL_FE_MASK,\n> -\t\t\t\t ras_cap.cap_control));\n> -\telse\n> -\t\tfe = status;\n> -\n> -\ttrace_cxl_aer_uncorrectable_error(&cxlmd->dev, status, fe,\n> -\t\t\t\t\t ras_cap.header_log,\n> -\t\t\t\t\t pci_get_dsn(pdev));\n> -}\n> -\n> -static int match_memdev_by_parent(struct device *dev, const void *uport)\n> -{\n> -\tif (is_cxl_memdev(dev) && dev->parent == uport)\n> -\t\treturn 1;\n> -\treturn 0;\n> +\t\t\t\t\t ras_cap->header_log, serial);\n> }\n> \n> void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n> @@ -77,38 +40,20 @@ void cxl_cper_handle_prot_err(struct cxl_cper_prot_err_work_data *data)\n> \t\tpci_get_domain_bus_and_slot(data->prot_err.agent_addr.segment,\n> \t\t\t\t\t data->prot_err.agent_addr.bus,\n> \t\t\t\t\t devfn);\n> -\tstruct cxl_memdev *cxlmd;\n> -\tint port_type;\n> \n> \tif (!pdev)\n> \t\treturn;\n> \n> -\tport_type = pci_pcie_type(pdev);\n> -\tif (port_type == PCI_EXP_TYPE_ROOT_PORT ||\n> -\t port_type == PCI_EXP_TYPE_DOWNSTREAM ||\n> -\t port_type == PCI_EXP_TYPE_UPSTREAM) {\n> -\t\tif (data->severity == AER_CORRECTABLE)\n> -\t\t\tcxl_cper_trace_corr_port_prot_err(pdev, data->ras_cap);\n> -\t\telse\n> -\t\t\tcxl_cper_trace_uncorr_port_prot_err(pdev, data->ras_cap);\n> -\n> -\t\treturn;\n> -\t}\n> -\n> \tguard(device)(&pdev->dev);\n> \tif (!pdev->dev.driver)\n> \t\treturn;\n> \n> -\tstruct device *mem_dev __free(put_device) = bus_find_device(\n> -\t\t&cxl_bus_type, NULL, pdev, match_memdev_by_parent);\n> -\tif (!mem_dev)\n> -\t\treturn;\n> -\n> -\tcxlmd = to_cxl_memdev(mem_dev);\n> \tif (data->severity == AER_CORRECTABLE)\n> -\t\tcxl_cper_trace_corr_prot_err(pdev, cxlmd, data->ras_cap);\n> +\t\tcxl_cper_trace_corr_prot_err(pdev, pci_get_dsn(pdev),\n> +\t\t\t\t\t &data->ras_cap);\n> \telse\n> -\t\tcxl_cper_trace_uncorr_prot_err(pdev, cxlmd, data->ras_cap);\n> +\t\tcxl_cper_trace_uncorr_prot_err(pdev, pci_get_dsn(pdev),\n> +\t\t\t\t\t &data->ras_cap);\n> }\n> EXPORT_SYMBOL_GPL(cxl_cper_handle_prot_err);\n>","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-pci@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) 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d=\"scan'208\";a=\"90010215\"","E=Sophos;i=\"6.23,218,1770624000\";\n d=\"scan'208\";a=\"232814098\""],"X-ExtLoop1":"1","Message-ID":"","Date":"Tue, 5 May 2026 15:02:45 -0700","Precedence":"bulk","X-Mailing-List":"linux-pci@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","User-Agent":"Mozilla Thunderbird","Subject":"Re: [PATCH v17 03/11] cxl: Use common CPER handling for all CXL\n devices","To":"Terry Bowman , dave@stgolabs.net, jic23@kernel.org,\n alison.schofield@intel.com, djbw@kernel.org, bhelgaas@google.com,\n ming.li@zohomail.com, Smita.KoralahalliChannabasappa@amd.com,\n rrichter@amd.com, PradeepVineshReddy.Kodamati@amd.com, lukas@wunner.de,\n Benjamin.Cheatham@amd.com, sathyanarayanan.kuppuswamy@linux.intel.com,\n vishal.l.verma@intel.com, alucerop@amd.com, ira.weiny@intel.com,\n corbet@lwn.net, rafael@kernel.org, xueshuai@linux.alibaba.com,\n linux-cxl@vger.kernel.org","Cc":"linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,\n linux-acpi@vger.kernel.org, linux-doc@vger.kernel.org","References":"<20260505173029.2718246-1-terry.bowman@amd.com>\n <20260505173029.2718246-4-terry.bowman@amd.com>","Content-Language":"en-US","From":"Dave Jiang ","In-Reply-To":"<20260505173029.2718246-4-terry.bowman@amd.com>","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"7bit"}}]