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GET /api/1.2/patches/2231943/?format=api
{ "id": 2231943, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2231943/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260501155421.3329862-10-elder@riscstar.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.2/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260501155421.3329862-10-elder@riscstar.com>", "list_archive_url": null, "date": "2026-05-01T15:54:17", "name": "[net-next,09/12] gpio: tc956x: add TC956x/QPS615 support", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "b5752b3289ee5adf2eb1d1555cb1307e51bebbec", "submitter": { "id": 89551, "url": "http://patchwork.ozlabs.org/api/1.2/people/89551/?format=api", "name": "Alex Elder", "email": "elder@riscstar.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260501155421.3329862-10-elder@riscstar.com/mbox/", "series": [ { "id": 502478, "url": "http://patchwork.ozlabs.org/api/1.2/series/502478/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502478", "date": "2026-05-01T15:54:09", "name": "net: enable TC956x support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502478/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231943/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231943/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-35961-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=riscstar-com.20251104.gappssmtp.com\n header.i=@riscstar-com.20251104.gappssmtp.com header.a=rsa-sha256\n header.s=20251104 header.b=sKonh8Us;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.232.135.74; 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TC956x includes a GPIO block that\ncan be accessed, alongside several other peripherals, via two PCIe\nendpoint functions. The PCIe function driver creates an auxiliary\ndevice for the GPIO block, and that device gets bound to this auxiliary\ndevice driver.\n\nCo-developed-by: Daniel Thompson <daniel@riscstar.com>\nSigned-off-by: Daniel Thompson <daniel@riscstar.com>\nSigned-off-by: Alex Elder <elder@riscstar.com>\n---\n drivers/gpio/Kconfig | 11 ++\n drivers/gpio/Makefile | 1 +\n drivers/gpio/gpio-tc956x.c | 209 +++++++++++++++++++++++++++++++++++++\n 3 files changed, 221 insertions(+)\n create mode 100644 drivers/gpio/gpio-tc956x.c", "diff": "diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig\nindex 020e51e30317a..746cedea7e91d 100644\n--- a/drivers/gpio/Kconfig\n+++ b/drivers/gpio/Kconfig\n@@ -1646,6 +1646,17 @@ config GPIO_TC3589X\n \t This enables support for the GPIOs found on the TC3589X\n \t I/O Expander.\n \n+config GPIO_TC956X\n+\ttristate \"Toshiba TC956X GPIO support\"\n+\tdepends on TOSHIBA_TC956X_PCI\n+\tdefault m if TOSHIBA_TC956X_PCI\n+\thelp\n+\t This enables support for the GPIO controller embedded in the Toshiba\n+\t TC956X (and Qualcomm QPS615). This device connects to the host\n+\t via PCIe port, which is the upstream port on an internal PCIe\n+\t switch. On some platforms, a few of the GPIO lines are used to\n+\t manage external resets.\n+\n config GPIO_TIMBERDALE\n \tbool \"Support for timberdale GPIO IP\"\n \tdepends on MFD_TIMBERDALE\ndiff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile\nindex b267598b517de..c3584e7cba9b4 100644\n--- a/drivers/gpio/Makefile\n+++ b/drivers/gpio/Makefile\n@@ -178,6 +178,7 @@ obj-$(CONFIG_GPIO_SYSCON)\t\t+= gpio-syscon.o\n obj-$(CONFIG_GPIO_TANGIER)\t\t+= gpio-tangier.o\n obj-$(CONFIG_GPIO_TB10X)\t\t+= gpio-tb10x.o\n obj-$(CONFIG_GPIO_TC3589X)\t\t+= gpio-tc3589x.o\n+obj-$(CONFIG_GPIO_TC956X)\t\t+= gpio-tc956x.o\n obj-$(CONFIG_GPIO_TEGRA186)\t\t+= gpio-tegra186.o\n obj-$(CONFIG_GPIO_TEGRA)\t\t+= gpio-tegra.o\n obj-$(CONFIG_GPIO_THUNDERX)\t\t+= gpio-thunderx.o\ndiff --git a/drivers/gpio/gpio-tc956x.c b/drivers/gpio/gpio-tc956x.c\nnew file mode 100644\nindex 0000000000000..12221d8f812d9\n--- /dev/null\n+++ b/drivers/gpio/gpio-tc956x.c\n@@ -0,0 +1,209 @@\n+// SPDX-License-Identifier: GPL-2.0\n+\n+/*\n+ * Copyright (C) 2026 by RISCstar Solutions Corporation. All rights reserved.\n+ */\n+\n+/*\n+ * The Toshiba TC956X implements a PCIe Gen 3 switch that connects an\n+ * upstream x4 port to two downstream PCIe x2 ports. It incorporates\n+ * an internal endpoint on a internal PCIe port that implements two\n+ * Synopsys XGMAC Ethernet interfaces.\n+ *\n+ * 35 GPIOs are also implemented by an embedded GPIO controller. Three\n+ * registers control the first 32 GPIOs (other than 20 and 21, which are\n+ * reserved). Three other registers control GPIOs 32 through 36. GPIOs\n+ * 22-24, 27-28, 31, and 34 are treated as \"input only\".\n+ *\n+ * There is a TC956X PCI power controller driver that accesses the\n+ * direction and output value registers for GPIOs 2 and 3. These\n+ * GPIOs control the reset signal for the two downstream PCIe ports.\n+ * Their values will never change during operation of this driver, and\n+ * this driver reserves these two GPIOS.\n+ */\n+\n+#include <linux/auxiliary_bus.h>\n+#include <linux/dev_printk.h>\n+#include <linux/gpio/driver.h>\n+#include <linux/module.h>\n+#include <linux/platform_device.h>\n+#include <linux/regmap.h>\n+\n+#define DRIVER_NAME\t\t\"tc956x-gpio\"\n+\n+#define TC956X_GPIO_COUNT\t37\t/* Number of GPIOs (20-21 reserved) */\n+\n+/* The GPIO offsets are relative to 0x1200 in TC956X SFR space */\n+#define GPIO_IN0_OFFSET\t\t0x00\t\t/* Input value (0-31) */\n+#define GPIO_EN0_OFFSET\t\t0x08\t\t/* 0: out; 1: in (0-31) */\n+#define GPIO_OUT0_OFFSET\t0x10\t\t/* Output value (0-31) */\n+\n+#define GPIO_IN1_OFFSET\t\t0x04\t\t/* Input value (32-36) */\n+#define GPIO_EN1_OFFSET\t\t0x0c\t\t/* 0: out; 1: in (32-36) */\n+#define GPIO_OUT1_OFFSET\t0x14\t\t/* Output value (32-36) */\n+\n+/*\n+ * struct tc956x_gpio - Information related to the embedded GPIO controller\n+ * @chip:\t\tGPIO chip structure\n+ * @regmap:\t\tMMIO register map for SFR GPIO region access\n+ * @input_only:\t\tBitmap indicating which GPIOs are input-only\n+ */\n+struct tc956x_gpio {\n+\tstruct gpio_chip chip;\n+\tstruct regmap *regmap;\n+\tDECLARE_BITMAP(input_only, TC956X_GPIO_COUNT);\n+};\n+\n+static int tc956x_gpio_get_direction(struct gpio_chip *gc, unsigned int offset)\n+{\n+\tstruct tc956x_gpio *gpio = gpiochip_get_data(gc);\n+\tu32 reg;\n+\tu32 val;\n+\n+\tif (test_bit(offset, gpio->input_only))\n+\t\treturn GPIO_LINE_DIRECTION_IN;\n+\n+\treg = offset < 32 ? GPIO_EN0_OFFSET : GPIO_EN1_OFFSET;\n+\n+\tregmap_read(gpio->regmap, reg, &val);\n+\tif (val & BIT(offset % 32))\n+\t\treturn GPIO_LINE_DIRECTION_IN;\n+\n+\treturn GPIO_LINE_DIRECTION_OUT;\n+}\n+\n+static int tc956x_gpio_direction_input(struct gpio_chip *gc,\n+\t\t\t\t unsigned int offset)\n+{\n+\tu32 reg = offset < 32 ? GPIO_EN0_OFFSET : GPIO_EN1_OFFSET;\n+\tstruct tc956x_gpio *gpio = gpiochip_get_data(gc);\n+\tu32 mask = BIT(offset % 32);\n+\n+\treturn regmap_update_bits(gpio->regmap, reg, mask, mask);\n+}\n+\n+static int tc956x_gpio_direction_output(struct gpio_chip *gc,\n+\t\t\t\t\tunsigned int offset, int value)\n+{\n+\tstruct tc956x_gpio *gpio = gpiochip_get_data(gc);\n+\tu32 vreg;\n+\tu32 dreg;\n+\tu32 mask;\n+\n+\tif (test_bit(offset, gpio->input_only))\n+\t\treturn -EINVAL;\n+\n+\tif (offset < 32) {\n+\t\tvreg = GPIO_OUT0_OFFSET;\n+\t\tdreg = GPIO_EN0_OFFSET;\n+\t} else {\n+\t\tvreg = GPIO_OUT1_OFFSET;\n+\t\tdreg = GPIO_EN1_OFFSET;\n+\t}\n+\tmask = BIT(offset % 32);\n+\n+\t/* Set output value first, then direction */\n+\tregmap_update_bits(gpio->regmap, vreg, mask, value ? mask : 0);\n+\n+\treturn regmap_update_bits(gpio->regmap, dreg, mask, 0);\n+}\n+\n+static int tc956x_gpio_get(struct gpio_chip *gc, unsigned int offset)\n+{\n+\tu32 reg = offset < 32 ? GPIO_IN0_OFFSET : GPIO_IN1_OFFSET;\n+\tstruct tc956x_gpio *gpio = gpiochip_get_data(gc);\n+\tu32 val;\n+\n+\tregmap_read(gpio->regmap, reg, &val);\n+\n+\treturn val & BIT(offset % 32) ? 1 : 0;\n+}\n+\n+static int tc956x_gpio_set(struct gpio_chip *gc, unsigned int offset, int value)\n+{\n+\tu32 reg = offset < 32 ? GPIO_OUT0_OFFSET : GPIO_OUT1_OFFSET;\n+\tstruct tc956x_gpio *gpio = gpiochip_get_data(gc);\n+\tu32 mask = BIT(offset % 32);\n+\n+\treturn regmap_update_bits(gpio->regmap, reg, mask, value ? mask : 0);\n+}\n+\n+static int tc956x_gpio_init_valid_mask(struct gpio_chip *gc,\n+\t\t\t\t unsigned long *valid_mask,\n+\t\t\t\t unsigned int ngpios)\n+{\n+\t/*\n+\t * GPIOs 2 and 3 are used by the PCI power control driver, and\n+\t * we don't allow them to be used. GPIOs 20 and 21 are reserved\n+\t * (and not usable).\n+\t */\n+\tbitmap_fill(valid_mask, ngpios);\n+\tbitmap_clear(valid_mask, 2, 2);\n+\tbitmap_clear(valid_mask, 20, 2);\n+\n+\treturn 0;\n+}\n+\n+static int tc956x_gpio_probe(struct auxiliary_device *adev,\n+\t\t\t const struct auxiliary_device_id *id)\n+{\n+\tstruct device *dev = &adev->dev;\n+\tstruct tc956x_gpio *gpio;\n+\tstruct gpio_chip *gc;\n+\n+\tif (!dev->platform_data)\n+\t\treturn -EINVAL;\n+\n+\tgpio = devm_kzalloc(dev, sizeof(*gpio), GFP_KERNEL);\n+\tif (!gpio)\n+\t\treturn -ENOMEM;\n+\tgpio->regmap = dev->platform_data;\n+\n+\t/* Mark GPIOs 22, 23, 24, 27, 28, 31, and 34 as input only */\n+\tbitmap_set(gpio->input_only, 22, 3);\n+\tbitmap_set(gpio->input_only, 27, 2);\n+\tset_bit(31, gpio->input_only);\n+\tset_bit(34, gpio->input_only);\n+\n+\tgc = &gpio->chip;\n+\n+\tgc->label = DRIVER_NAME;\n+\tgc->parent = dev->parent;\n+\n+\tgc->get_direction = tc956x_gpio_get_direction;\n+\tgc->direction_input = tc956x_gpio_direction_input;\n+\tgc->direction_output = tc956x_gpio_direction_output;\n+\tgc->get = tc956x_gpio_get;\n+\tgc->set = tc956x_gpio_set;\n+\tgc->init_valid_mask = tc956x_gpio_init_valid_mask;\n+\n+\tgc->base = -1;\n+\tgc->ngpio = TC956X_GPIO_COUNT;\n+\tgc->can_sleep = false;\n+\n+\tdev_set_drvdata(dev, gpio);\n+\n+\treturn devm_gpiochip_add_data(dev, gc, gpio);\n+}\n+\n+static const struct auxiliary_device_id tc956x_gpio_ids[] = {\n+\t{ .name = \"tc956x_pci.tc9564-gpio\", },\n+\t{ }\n+};\n+MODULE_DEVICE_TABLE(auxiliary, tc956x_gpio_ids);\n+\n+static struct auxiliary_driver tc956x_gpio_driver = {\n+\t.name\t\t= DRIVER_NAME,\n+\t.probe = tc956x_gpio_probe,\n+\t.id_table = tc956x_gpio_ids,\n+\t.driver = {\n+\t\t.name\t\t= DRIVER_NAME,\n+\t\t.owner\t\t= THIS_MODULE,\n+\t\t.probe_type\t= PROBE_PREFER_ASYNCHRONOUS,\n+\t},\n+};\n+module_auxiliary_driver(tc956x_gpio_driver);\n+\n+MODULE_DESCRIPTION(\"Toshiba TC956X PCIe GPIO Driver\");\n+MODULE_LICENSE(\"GPL\");\n+MODULE_ALIAS(\"auxiliary:\" DRIVER_NAME);\n", "prefixes": [ "net-next", "09/12" ] }