[{"id":3685206,"web_url":"http://patchwork.ozlabs.org/comment/3685206/","msgid":"<736fb3b7-c88a-4ec4-96ad-d1b79cc48d30@lunn.ch>","list_archive_url":null,"date":"2026-05-01T18:36:08","subject":"Re: [PATCH net-next 09/12] gpio: tc956x: add TC956x/QPS615 support","submitter":{"id":13608,"url":"http://patchwork.ozlabs.org/api/people/13608/","name":"Andrew Lunn","email":"andrew@lunn.ch"},"content":"> + * There is a TC956X PCI power controller driver that accesses the\n> + * direction and output value registers for GPIOs 2 and 3. These\n> + * GPIOs control the reset signal for the two downstream PCIe ports.\n> + * Their values will never change during operation of this driver, and\n> + * this driver reserves these two GPIOS.\n\nWhy doesn't this power controller driver actually use this driver to\ncontrol the GPIOs? Chicken/egg?\n\nMaybe add a comment why gpio-regmap.c cannot be used. You probably\nneed to instantiate it twice, but i still think you will end up with\nless code.\n\n\tAndrew","headers":{"Return-Path":"\n ","X-Original-To":["incoming@patchwork.ozlabs.org","linux-gpio@vger.kernel.org"],"Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (1024-bit key;\n unprotected) header.d=lunn.ch header.i=@lunn.ch header.a=rsa-sha256\n header.s=20171124 header.b=hzVyVIJz;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=172.234.253.10; helo=sea.lore.kernel.org;\n envelope-from=linux-gpio+bounces-35972-incoming=patchwork.ozlabs.org@vger.kernel.org;\n receiver=patchwork.ozlabs.org)","smtp.subspace.kernel.org;\n\tdkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch\n header.b=\"hzVyVIJz\"","smtp.subspace.kernel.org;\n arc=none smtp.client-ip=156.67.10.101","smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=lunn.ch","smtp.subspace.kernel.org;\n spf=pass smtp.mailfrom=lunn.ch"],"Received":["from sea.lore.kernel.org (sea.lore.kernel.org [172.234.253.10])\n\t(using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)\n\t key-exchange x25519)\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g6ft342f3z1xvV\n\tfor ; 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a=rsa-sha256; d=subspace.kernel.org;\n\ts=arc-20240116; t=1777660616; c=relaxed/simple;\n\tbh=SsTIJvA1/Pjq/mpqisHV0VFtuk11C+ZGfXQJ+O2QUbs=;\n\th=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version:\n\t Content-Type:Content-Disposition:In-Reply-To;\n b=ra3Xq1A+AGLwK4eIbY0+/LiDWq8qf38UebGMfaNugXfwUu9mVdEp0lfMm5C/cOQOYe/X8UHSZ7QngX4lp7n65CfULnnimA6MdpFexxr0hASDY2egVc2s2Te3bGqqGi87VvQbDyk63zE1VVFwbZB/sDbofZDTN6unc+NvLNH4YGE=","ARC-Authentication-Results":"i=1; smtp.subspace.kernel.org;\n dmarc=pass (p=none dis=none) header.from=lunn.ch;\n spf=pass smtp.mailfrom=lunn.ch;\n dkim=pass (1024-bit key) header.d=lunn.ch header.i=@lunn.ch\n header.b=hzVyVIJz; arc=none smtp.client-ip=156.67.10.101","DKIM-Signature":"v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lunn.ch;\n\ts=20171124; h=In-Reply-To:Content-Disposition:Content-Type:MIME-Version:\n\tReferences:Message-ID:Subject:Cc:To:From:Date:From:Sender:Reply-To:Subject:\n\tDate:Message-ID:To:Cc:MIME-Version:Content-Type:Content-Transfer-Encoding:\n\tContent-ID:Content-Description:Content-Disposition:In-Reply-To:References;\n\tbh=vZ9dw2mmSr8oO8ubiqu0GGlDjqOspeWOnHecTqU4Gd8=; b=hzVyVIJzIvvnJ54VdeHNnhi8AK\n\tzIylf+U+zVcjdHUutgFEFHRNzDG2YixlAqAdlyVtEXWaV2UvZzwy61r3/8b3JbZNCVvdci7WZ3Jvn\n\teViWLhZtZXjzloI1SeBIJZCETP/b5a1/VhdT+EnqR0vo8tWQ0+SFqyUCaKkooPQgMl4g=;","Date":"Fri, 1 May 2026 20:36:08 +0200","From":"Andrew Lunn ","To":"Alex Elder ","Cc":"andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com,\n\tkuba@kernel.org, pabeni@redhat.com, maxime.chevallier@bootlin.com,\n\trmk+kernel@armlinux.org.uk, andersson@kernel.org,\n\tkonradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org,\n\tconor+dt@kernel.org, linusw@kernel.org, brgl@kernel.org,\n\tarnd@arndb.de, gregkh@linuxfoundation.org, daniel@riscstar.com,\n\tmohd.anwar@oss.qualcomm.com, a0987203069@gmail.com,\n\talexandre.torgue@foss.st.com, ast@kernel.org,\n\tboon.khai.ng@altera.com, chenchuangyu@xiaomi.com,\n\tchenhuacai@kernel.org, daniel@iogearbox.net, hawk@kernel.org,\n\thkallweit1@gmail.com, inochiama@gmail.com, john.fastabend@gmail.com,\n\tjulianbraha@gmail.com, livelycarpet87@gmail.com,\n\tmatthew.gerlach@altera.com, mcoquelin.stm32@gmail.com, me@ziyao.cc,\n\tprabhakar.mahadev-lad.rj@bp.renesas.com, richardcochran@gmail.com,\n\trohan.g.thomas@altera.com, sdf@fomichev.me,\n\tsiyanteng@cqsoftware.com.cn, weishangjuan@eswincomputing.com,\n\twens@kernel.org, netdev@vger.kernel.org, bpf@vger.kernel.org,\n\tlinux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,\n\tlinux-gpio@vger.kernel.org,\n\tlinux-stm32@st-md-mailman.stormreply.com,\n\tlinux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org","Subject":"Re: [PATCH net-next 09/12] gpio: tc956x: add TC956x/QPS615 support","Message-ID":"<736fb3b7-c88a-4ec4-96ad-d1b79cc48d30@lunn.ch>","References":"<20260501155421.3329862-1-elder@riscstar.com>\n <20260501155421.3329862-10-elder@riscstar.com>","Precedence":"bulk","X-Mailing-List":"linux-gpio@vger.kernel.org","List-Id":"","List-Subscribe":"","List-Unsubscribe":"","MIME-Version":"1.0","Content-Type":"text/plain; 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