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GET /api/1.2/patches/2231942/?format=api
{ "id": 2231942, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2231942/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260501155421.3329862-6-elder@riscstar.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.2/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260501155421.3329862-6-elder@riscstar.com>", "list_archive_url": null, "date": "2026-05-01T15:54:13", "name": "[net-next,05/12] net: stmmac: dwxgmac2: Add multi MSI interrupt mode", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "cf83d62da5b1ac84c5565abc6bde2c5581a72380", "submitter": { "id": 89551, "url": "http://patchwork.ozlabs.org/api/1.2/people/89551/?format=api", "name": "Alex Elder", "email": "elder@riscstar.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260501155421.3329862-6-elder@riscstar.com/mbox/", "series": [ { "id": 502478, "url": "http://patchwork.ozlabs.org/api/1.2/series/502478/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=502478", "date": "2026-05-01T15:54:09", "name": "net: enable TC956x support", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/502478/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2231942/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2231942/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-35957-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", "linux-gpio@vger.kernel.org" ], "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=riscstar-com.20251104.gappssmtp.com\n header.i=@riscstar-com.20251104.gappssmtp.com header.a=rsa-sha256\n header.s=20251104 header.b=U/FsVG6P;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=vger.kernel.org\n (client-ip=2600:3c15:e001:75::12fc:5321; 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In other words no existing driver sets both\nDWMAC_CORE_XGMAC and STMMAC_FLAG_MULTI_MSI_EN.\n\nIn order to support systems that do enable both options (such as the\nToshiba TC9564 whose driver is currently being developed) we need to\nadd logic to the XGMAC DMA callbacks. Happily we can simply\nreplicate similar code from GMAC4. Let's do that!\n\nSigned-off-by: Daniel Thompson <daniel@riscstar.com>\nSigned-off-by: Alex Elder <elder@riscstar.com>\n---\n drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h | 2 ++\n drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c | 8 ++++++++\n 2 files changed, 10 insertions(+)", "diff": "diff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\nindex 51943705a2b03..9b0b5cc619556 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2.h\n@@ -320,6 +320,8 @@\n /* DMA Registers */\n #define XGMAC_DMA_MODE\t\t\t0x00003000\n #define XGMAC_SWR\t\t\tBIT(0)\n+#define XGMAC_INTM_MASK\t\t\tGENMASK(13, 12)\n+#define XGMAC_INTM_MODE1\t\t0x1\n #define XGMAC_DMA_SYSBUS_MODE\t\t0x00003004\n #define XGMAC_WR_OSR_LMT\t\tGENMASK(29, 24)\n #define XGMAC_RD_OSR_LMT\t\tGENMASK(21, 16)\ndiff --git a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\nindex 03437f1cf3df3..a84601ac32153 100644\n--- a/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\n+++ b/drivers/net/ethernet/stmicro/stmmac/dwxgmac2_dma.c\n@@ -31,6 +31,14 @@ static void dwxgmac2_dma_init(void __iomem *ioaddr,\n \t\tvalue |= XGMAC_EAME;\n \n \twritel(value, ioaddr + XGMAC_DMA_SYSBUS_MODE);\n+\n+\tvalue = readl(ioaddr + XGMAC_DMA_MODE);\n+\n+\tif (dma_cfg->multi_msi_en)\n+\t\tvalue = u32_replace_bits(value, XGMAC_INTM_MODE1,\n+\t\t\t\t\t XGMAC_INTM_MASK);\n+\n+\twritel(value, ioaddr + XGMAC_DMA_MODE);\n }\n \n static void dwxgmac2_dma_init_chan(struct stmmac_priv *priv,\n", "prefixes": [ "net-next", "05/12" ] }