Patch Detail
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Show a patch.
patch:
Update a patch.
put:
Update a patch.
GET /api/1.2/patches/2227927/?format=api
{ "id": 2227927, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2227927/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260424111330.702272-2-changhuang.liang@starfivetech.com/", "project": { "id": 42, "url": "http://patchwork.ozlabs.org/api/1.2/projects/42/?format=api", "name": "Linux GPIO development", "link_name": "linux-gpio", "list_id": "linux-gpio.vger.kernel.org", "list_email": "linux-gpio@vger.kernel.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260424111330.702272-2-changhuang.liang@starfivetech.com>", "list_archive_url": null, "date": "2026-04-24T11:13:11", "name": "[v1,01/20] dt-bindings: pinctrl: Add starfive,jhb100-sys0-pinctrl", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "d003cff076471b4631b16dfd0a370f03f4865cb7", "submitter": { "id": 85771, "url": "http://patchwork.ozlabs.org/api/1.2/people/85771/?format=api", "name": "Changhuang Liang", "email": "changhuang.liang@starfivetech.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/linux-gpio/patch/20260424111330.702272-2-changhuang.liang@starfivetech.com/mbox/", "series": [ { "id": 501347, "url": "http://patchwork.ozlabs.org/api/1.2/series/501347/?format=api", "web_url": "http://patchwork.ozlabs.org/project/linux-gpio/list/?series=501347", "date": "2026-04-24T11:13:16", "name": "Add basic pinctrl drivers for JHB100 SoC", "version": 1, "mbox": "http://patchwork.ozlabs.org/series/501347/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2227927/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2227927/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "\n <linux-gpio+bounces-35505-incoming=patchwork.ozlabs.org@vger.kernel.org>", "X-Original-To": [ "incoming@patchwork.ozlabs.org", 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<changhuang.liang@starfivetech.com>", "To": "Linus Walleij <linusw@kernel.org>,\n\tRob Herring <robh@kernel.org>,\n\tKrzysztof Kozlowski <krzk+dt@kernel.org>,\n\tConor Dooley <conor+dt@kernel.org>,\n\tEmil Renner Berthing <kernel@esmil.dk>,\n\tPaul Walmsley <pjw@kernel.org>,\n\tAlbert Ou <aou@eecs.berkeley.edu>,\n\tPalmer Dabbelt <palmer@dabbelt.com>,\n\tAlexandre Ghiti <alex@ghiti.fr>,\n\tPhilipp Zabel <p.zabel@pengutronix.de>,\n\tBartosz Golaszewski <brgl@kernel.org>", "Cc": "linux-gpio@vger.kernel.org,\n\tlinux-kernel@vger.kernel.org,\n\tdevicetree@vger.kernel.org,\n\tlinux-riscv@lists.infradead.org,\n\tLianfeng Ouyang <lianfeng.ouyang@starfivetech.com>,\n\tChanghuang Liang <changhuang.liang@starfivetech.com>", "Subject": "[PATCH v1 01/20] dt-bindings: pinctrl: Add\n starfive,jhb100-sys0-pinctrl", "Date": "Fri, 24 Apr 2026 04:13:11 -0700", "Message-Id": "<20260424111330.702272-2-changhuang.liang@starfivetech.com>", "X-Mailer": "git-send-email 2.25.1", "In-Reply-To": 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"X-OriginatorOrg": "starfivetech.com", "X-MS-Exchange-CrossTenant-Network-Message-Id": "\n 794e887d-9d9d-490d-0401-08dea1f28987", "X-MS-Exchange-CrossTenant-AuthSource": "\n ZQ4PR01MB1202.CHNPR01.prod.partner.outlook.cn", "X-MS-Exchange-CrossTenant-AuthAs": "Internal", "X-MS-Exchange-CrossTenant-OriginalArrivalTime": "24 Apr 2026 11:13:39.5857\n (UTC)", "X-MS-Exchange-CrossTenant-FromEntityHeader": "Hosted", "X-MS-Exchange-CrossTenant-Id": "06fe3fa3-1221-43d3-861b-5a4ee687a85c", "X-MS-Exchange-CrossTenant-MailboxType": "HOSTED", "X-MS-Exchange-CrossTenant-UserPrincipalName": "\n T/z1a4HmHtSOf7KVa2BjnYdiT7kueB+a+WKvh5e62X0LNo/a5HQxusEXDL9RT9p28nKvEc9q/NlaCpRphyok6zXb9SnGuDwliWWfi+UbAGXTlNZopLyGkF0BgDiUPDwG", "X-MS-Exchange-Transport-CrossTenantHeadersStamped": "ZQ4PR01MB1299" }, "content": "Add pinctrl bindings for StarFive JHB100 SoC System-0(sys0) pinctrl\ncontroller.\n\nSigned-off-by: Changhuang Liang <changhuang.liang@starfivetech.com>\n---\n .../pinctrl/starfive,jhb100-sys0-pinctrl.yaml | 155 ++++++++++++++++++\n 1 file changed, 155 insertions(+)\n create mode 100644 Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml", "diff": "diff --git a/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml\nnew file mode 100644\nindex 000000000000..21be5717cb74\n--- /dev/null\n+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jhb100-sys0-pinctrl.yaml\n@@ -0,0 +1,155 @@\n+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause\n+%YAML 1.2\n+---\n+$id: http://devicetree.org/schemas/pinctrl/starfive,jhb100-sys0-pinctrl.yaml#\n+$schema: http://devicetree.org/meta-schemas/core.yaml#\n+\n+title: StarFive JHB100 System-0 Pin Controller\n+\n+description: |\n+ Pinctrl bindings for JHB100 RISC-V SoC from StarFive Technology Ltd.\n+\n+ The JHB100 SoC has 13 pinctrl domains - sys0, sys0h, sys1, sys2, per0, per1,\n+ per2, per2pok, per3, adc0, adc1, emmc, and vga.\n+ This document provides an overview of the \"sys0\" pinctrl domain.\n+\n+ The \"sys0\" domain has a pin controller which provides\n+ - function selection for GPIO pads.\n+ - GPIO pad configuration.\n+ - GPIO interrupt handling.\n+\n+ In the SYS0 Pin Controller, there are 4 multi-function GPIO_PADs. Each of them can be multiplexed\n+ to different hardware blocks through function selection and each iopad has a maximum of up to 2\n+ functions - 0 and 1. Function 0 is the default function which is generally the GPIO function\n+ (or occasionally, it can be a peripheral signal). Function 1 is the alternate function or\n+ peripheral signal that can be routed to the iopad. The function selection is carried out by\n+ writing the function number to the iopad function select register.\n+ Each iopad is configurable with parameters such as input-enable, internal pull-up/pull-down bias,\n+ drive strength, schmitt trigger, slew rate, and debounce width.\n+\n+maintainers:\n+ - Alex Soo <yuklin.soo@starfivetech.com>\n+\n+properties:\n+ compatible:\n+ items:\n+ - const: starfive,jhb100-sys0-pinctrl\n+\n+ reg:\n+ maxItems: 1\n+\n+ clocks:\n+ maxItems: 1\n+\n+ resets:\n+ maxItems: 1\n+\n+ interrupts:\n+ maxItems: 1\n+\n+ interrupt-controller: true\n+\n+ '#interrupt-cells':\n+ const: 2\n+\n+ gpio-controller: true\n+\n+ '#gpio-cells':\n+ const: 2\n+\n+ gpio-ranges:\n+ maxItems: 1\n+\n+ gpio-line-names: true\n+\n+patternProperties:\n+ '-grp$':\n+ type: object\n+ additionalProperties: false\n+ patternProperties:\n+ '-pins$':\n+ type: object\n+ description: |\n+ A pinctrl node should contain at least one subnode representing the\n+ pinctrl groups available in the domain. Each subnode will list the\n+ pins it needs, and how they should be configured, with regard to\n+ function selection, bias, input enable/disable, input schmitt\n+ trigger enable/disable, slew-rate and drive strength.\n+ allOf:\n+ - $ref: /schemas/pinctrl/pincfg-node.yaml\n+ - $ref: /schemas/pinctrl/pinmux-node.yaml\n+ unevaluatedProperties: false\n+\n+ properties:\n+ pinmux:\n+ description: |\n+ The list of GPIOs and their function select.\n+ The PINMUX macros are used to configure the\n+ function selection.\n+\n+ bias-disable: true\n+\n+ bias-pull-up:\n+ type: boolean\n+\n+ bias-pull-down:\n+ type: boolean\n+\n+ drive-strength:\n+ enum: [ 2, 4, 8, 12 ]\n+\n+ drive-strength-microamp:\n+ enum: [ 2000, 4000, 8000, 12000 ]\n+\n+ input-enable: true\n+\n+ input-disable: true\n+\n+ input-schmitt-enable: true\n+\n+ input-schmitt-disable: true\n+\n+ slew-rate:\n+ enum: [ 0, 1 ]\n+ default: 0\n+ description: |\n+ 0: slow (half frequency)\n+ 1: fast\n+\n+ starfive,debounce-width:\n+ $ref: /schemas/types.yaml#/definitions/uint32\n+ default: 0\n+ description:\n+ Debounce width 0 = Disabled, Others = 80ns*N stages\n+\n+required:\n+ - compatible\n+ - reg\n+ - resets\n+ - interrupts\n+ - interrupt-controller\n+ - '#interrupt-cells'\n+ - gpio-controller\n+ - '#gpio-cells'\n+ - gpio-ranges\n+\n+additionalProperties: false\n+\n+examples:\n+ - |\n+ soc {\n+ #address-cells = <2>;\n+ #size-cells = <2>;\n+\n+ pinctrl_sys0: pinctrl@13080000 {\n+ compatible = \"starfive,jhb100-sys0-pinctrl\";\n+ reg = <0x0 0x13080000 0x0 0x800>;\n+ resets = <&sys0crg 2>;\n+ interrupts = <56>;\n+ interrupt-controller;\n+ #interrupt-cells = <2>;\n+ gpio-controller;\n+ #gpio-cells = <2>;\n+ gpio-ranges = <&pinctrl_sys0 0 0 4>;\n+ };\n+ };\n", "prefixes": [ "v1", "01/20" ] }