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GET /api/1.2/patches/2225875/?format=api
{ "id": 2225875, "url": "http://patchwork.ozlabs.org/api/1.2/patches/2225875/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-6-a0791df188c9@gmail.com/", "project": { "id": 14, "url": "http://patchwork.ozlabs.org/api/1.2/projects/14/?format=api", "name": "QEMU Development", "link_name": "qemu-devel", "list_id": "qemu-devel.nongnu.org", "list_email": "qemu-devel@nongnu.org", "web_url": "", "scm_url": "", "webscm_url": "", "list_archive_url": "", "list_archive_url_format": "", "commit_url_format": "" }, "msgid": "<20260421-mips-octeon-missing-insns-v2-v2-6-a0791df188c9@gmail.com>", "list_archive_url": null, "date": "2026-04-21T17:27:33", "name": "[v2,06/13] target/mips: add Octeon LA* atomic instructions", "commit_ref": null, "pull_url": null, "state": "new", "archived": false, "hash": "dfa9e5065e5e5952b90d6ba9298ef51068f1b40b", "submitter": { "id": 66301, "url": "http://patchwork.ozlabs.org/api/1.2/people/66301/?format=api", "name": "James Hilliard", "email": "james.hilliard1@gmail.com" }, "delegate": null, "mbox": "http://patchwork.ozlabs.org/project/qemu-devel/patch/20260421-mips-octeon-missing-insns-v2-v2-6-a0791df188c9@gmail.com/mbox/", "series": [ { "id": 500858, "url": "http://patchwork.ozlabs.org/api/1.2/series/500858/?format=api", "web_url": "http://patchwork.ozlabs.org/project/qemu-devel/list/?series=500858", "date": "2026-04-21T17:27:27", "name": "target/mips: add missing Octeon user-mode support", "version": 2, "mbox": "http://patchwork.ozlabs.org/series/500858/mbox/" } ], "comments": "http://patchwork.ozlabs.org/api/patches/2225875/comments/", "check": "pending", "checks": "http://patchwork.ozlabs.org/api/patches/2225875/checks/", "tags": {}, "related": [], "headers": { "Return-Path": "<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>", "X-Original-To": "incoming@patchwork.ozlabs.org", "Delivered-To": "patchwork-incoming@legolas.ozlabs.org", "Authentication-Results": [ "legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=gmail.com header.i=@gmail.com header.a=rsa-sha256\n header.s=20251104 header.b=WsDcpe8t;\n\tdkim-atps=neutral", "legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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charset=\"utf-8\"", "Content-Transfer-Encoding": "8bit", "Message-Id": "\n <20260421-mips-octeon-missing-insns-v2-v2-6-a0791df188c9@gmail.com>", "References": "\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>", "In-Reply-To": "\n <20260421-mips-octeon-missing-insns-v2-v2-0-a0791df188c9@gmail.com>", "To": "qemu-devel@nongnu.org", "Cc": "Laurent Vivier <laurent@vivier.eu>,\n Pierrick Bouvier <pierrick.bouvier@linaro.org>, =?utf-8?q?Philippe_Mathieu?=\n\t=?utf-8?q?-Daud=C3=A9?= <philmd@linaro.org>,\n Aurelien Jarno <aurelien@aurel32.net>,\n Jiaxun Yang <jiaxun.yang@flygoat.com>,\n Aleksandar Rikalo <arikalo@gmail.com>, Huacai Chen <chenhuacai@kernel.org>,\n James Hilliard <james.hilliard1@gmail.com>", "X-Mailer": "b4 0.15.2", "Received-SPF": "pass client-ip=2607:f8b0:4864:20::32b;\n envelope-from=james.hilliard1@gmail.com; helo=mail-ot1-x32b.google.com", "X-Spam_score_int": "-7", "X-Spam_score": "-0.8", "X-Spam_bar": "/", "X-Spam_report": "(-0.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_GMAIL_RCVD=1,\n FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=no autolearn_force=no", "X-Spam_action": "no action", "X-BeenThere": "qemu-devel@nongnu.org", "X-Mailman-Version": "2.1.29", "Precedence": "list", "List-Id": "qemu development <qemu-devel.nongnu.org>", "List-Unsubscribe": "<https://lists.nongnu.org/mailman/options/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>", "List-Archive": "<https://lists.nongnu.org/archive/html/qemu-devel>", "List-Post": "<mailto:qemu-devel@nongnu.org>", "List-Help": "<mailto:qemu-devel-request@nongnu.org?subject=help>", "List-Subscribe": "<https://lists.nongnu.org/mailman/listinfo/qemu-devel>,\n <mailto:qemu-devel-request@nongnu.org?subject=subscribe>", "Errors-To": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org", "Sender": "qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org" }, "content": "Implement the Octeon LA* read-modify-write atomic instruction family:\nLAI/LAID, LAD/LADD, LAA/LAAD, LAS/LASD, LAC/LACD, and LAW/LAWD.\n\nThese operations are architecturally distinct from SAA/SAAD and are used\nby existing Octeon user-mode code for atomic counters, bit operations,\nand exchange-style updates.\n\nSigned-off-by: James Hilliard <james.hilliard1@gmail.com>\n---\nChanges v1 -> v2:\n - Keep LA* atomics naturally aligned per Octeon L2 transaction\n semantics.\n - Use explicit i64 TCG ops in the LA* translator paths. (suggested by\n Philippe Mathieu-Daudé)\n---\n target/mips/tcg/octeon.decode | 17 ++++\n target/mips/tcg/octeon_translate.c | 170 +++++++++++++++++++++++++++++++++++++\n 2 files changed, 187 insertions(+)", "diff": "diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\nindex 2eb15aa17f..9dcc5a6ae0 100644\n--- a/target/mips/tcg/octeon.decode\n+++ b/target/mips/tcg/octeon.decode\n@@ -60,6 +60,23 @@ V3MULU 011100 ..... ..... ..... 00000 010001 @r3\n SAA 011100 ..... ..... 00000 00000 011000 @saa\n SAAD 011100 ..... ..... 00000 00000 011001 @saa\n \n+&la base rd\n+&laa base add rd\n+@la ...... base:5 ..... rd:5 ........... &la\n+@laa ...... base:5 add:5 rd:5 ........... &laa\n+LAI 011100 ..... 00000 ..... 00010 011111 @la\n+LAID 011100 ..... 00000 ..... 00011 011111 @la\n+LAD 011100 ..... 00000 ..... 00110 011111 @la\n+LADD 011100 ..... 00000 ..... 00111 011111 @la\n+LAA 011100 ..... ..... ..... 10010 011111 @laa\n+LAAD 011100 ..... ..... ..... 10011 011111 @laa\n+LAS 011100 ..... 00000 ..... 01010 011111 @la\n+LASD 011100 ..... 00000 ..... 01011 011111 @la\n+LAC 011100 ..... 00000 ..... 01110 011111 @la\n+LACD 011100 ..... 00000 ..... 01111 011111 @la\n+LAW 011100 ..... ..... ..... 10110 011111 @laa\n+LAWD 011100 ..... ..... ..... 10111 011111 @laa\n+\n &zcb base\n ZCB 011100 base:5 00000 00000 11100 011111 &zcb\n ZCBT 011100 base:5 00000 00000 11101 011111 &zcb\ndiff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\nindex cdb4d36c8e..6309cd5fff 100644\n--- a/target/mips/tcg/octeon_translate.c\n+++ b/target/mips/tcg/octeon_translate.c\n@@ -254,6 +254,164 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)\n return true;\n }\n \n+static bool trans_la_common(DisasContext *ctx, int base, int add_reg, int rd,\n+ int64_t imm, bool dw)\n+{\n+ if (dw && !octeon_check_64(ctx)) {\n+ return true;\n+ }\n+\n+ TCGv_i64 addr = tcg_temp_new_i64();\n+\n+ gen_base_offset_addr(ctx, addr, base, 0);\n+\n+ if (dw) {\n+#if TARGET_LONG_BITS == 64\n+ TCGv_i64 value = tcg_temp_new_i64();\n+ TCGv_i64 old = tcg_temp_new_i64();\n+ MemOp amo = mo_endian(ctx) | MO_UQ | MO_ALIGN;\n+\n+ if (add_reg >= 0) {\n+ gen_load_gpr(value, add_reg);\n+ } else {\n+ tcg_gen_movi_i64(value, imm);\n+ }\n+\n+ tcg_gen_atomic_fetch_add_i64(old, addr, value, ctx->mem_idx, amo);\n+ gen_store_gpr(old, rd);\n+#endif\n+ } else {\n+ TCGv_i64 old = tcg_temp_new_i64();\n+ TCGv_i32 value32 = tcg_temp_new_i32();\n+ TCGv_i32 old32 = tcg_temp_new_i32();\n+ MemOp amo = mo_endian(ctx) | MO_UL | MO_ALIGN;\n+\n+ if (add_reg < 0) {\n+ tcg_gen_movi_i32(value32, imm);\n+ } else {\n+ TCGv_i64 value = tcg_temp_new_i64();\n+\n+ gen_load_gpr(value, add_reg);\n+ tcg_gen_extrl_i64_i32(value32, value);\n+ }\n+\n+ tcg_gen_atomic_fetch_add_i32(old32, addr, value32, ctx->mem_idx, amo);\n+ tcg_gen_ext_i32_i64(old, old32);\n+ gen_store_gpr(old, rd);\n+ }\n+\n+ return true;\n+}\n+\n+static bool trans_law_common(DisasContext *ctx, int base, int add_reg, int rd,\n+ int64_t imm, bool dw)\n+{\n+ if (dw && !octeon_check_64(ctx)) {\n+ return true;\n+ }\n+\n+ TCGv_i64 addr = tcg_temp_new_i64();\n+\n+ gen_base_offset_addr(ctx, addr, base, 0);\n+\n+ if (dw) {\n+#if TARGET_LONG_BITS == 64\n+ TCGv_i64 value = tcg_temp_new_i64();\n+ TCGv_i64 old = tcg_temp_new_i64();\n+ MemOp amo = mo_endian(ctx) | MO_UQ | MO_ALIGN;\n+\n+ if (add_reg >= 0) {\n+ gen_load_gpr(value, add_reg);\n+ } else {\n+ tcg_gen_movi_i64(value, imm);\n+ }\n+\n+ tcg_gen_atomic_xchg_i64(old, addr, value, ctx->mem_idx, amo);\n+ gen_store_gpr(old, rd);\n+#endif\n+ } else {\n+ TCGv_i64 old = tcg_temp_new_i64();\n+ TCGv_i32 value32 = tcg_temp_new_i32();\n+ TCGv_i32 old32 = tcg_temp_new_i32();\n+ MemOp amo = mo_endian(ctx) | MO_UL | MO_ALIGN;\n+\n+ if (add_reg >= 0) {\n+ TCGv_i64 value = tcg_temp_new_i64();\n+\n+ gen_load_gpr(value, add_reg);\n+ tcg_gen_extrl_i64_i32(value32, value);\n+ } else {\n+ tcg_gen_movi_i32(value32, imm);\n+ }\n+\n+ tcg_gen_atomic_xchg_i32(old32, addr, value32, ctx->mem_idx, amo);\n+ tcg_gen_ext_i32_i64(old, old32);\n+ gen_store_gpr(old, rd);\n+ }\n+\n+ return true;\n+}\n+\n+static bool trans_lai(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, -1, a->rd, 1, false);\n+}\n+\n+static bool trans_laid(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, -1, a->rd, 1, true);\n+}\n+\n+static bool trans_lad(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, -1, a->rd, -1, false);\n+}\n+\n+static bool trans_ladd(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, -1, a->rd, -1, true);\n+}\n+\n+static bool trans_laa(DisasContext *ctx, arg_laa *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, a->add, a->rd, 0, false);\n+}\n+\n+static bool trans_laad(DisasContext *ctx, arg_laa *a, int unused)\n+{\n+ return trans_la_common(ctx, a->base, a->add, a->rd, 0, true);\n+}\n+\n+static bool trans_las(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, -1, a->rd, -1, false);\n+}\n+\n+static bool trans_lasd(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, -1, a->rd, -1, true);\n+}\n+\n+static bool trans_lac(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, -1, a->rd, 0, false);\n+}\n+\n+static bool trans_lacd(DisasContext *ctx, arg_la *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, -1, a->rd, 0, true);\n+}\n+\n+static bool trans_law(DisasContext *ctx, arg_laa *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, a->add, a->rd, 0, false);\n+}\n+\n+static bool trans_lawd(DisasContext *ctx, arg_laa *a, int unused)\n+{\n+ return trans_law_common(ctx, a->base, a->add, a->rd, 0, true);\n+}\n+\n static bool trans_ZCB(DisasContext *ctx, arg_zcb *a)\n {\n TCGv_i64 addr = tcg_temp_new_i64();\n@@ -376,6 +534,18 @@ static bool trans_vmul(DisasContext *ctx, arg_decode_ext_octeon1 *a,\n \n TRANS(SAA, trans_saa, MO_UL);\n TRANS(SAAD, trans_saa, MO_UQ);\n+TRANS(LAI, trans_lai, 0);\n+TRANS(LAID, trans_laid, 0);\n+TRANS(LAD, trans_lad, 0);\n+TRANS(LADD, trans_ladd, 0);\n+TRANS(LAA, trans_laa, 0);\n+TRANS(LAAD, trans_laad, 0);\n+TRANS(LAS, trans_las, 0);\n+TRANS(LASD, trans_lasd, 0);\n+TRANS(LAC, trans_lac, 0);\n+TRANS(LACD, trans_lacd, 0);\n+TRANS(LAW, trans_law, 0);\n+TRANS(LAWD, trans_lawd, 0);\n TRANS(LBX, trans_lx, MO_SB);\n TRANS(LBUX, trans_lx, MO_UB);\n TRANS(LHX, trans_lx, MO_SW);\n", "prefixes": [ "v2", "06/13" ] }