[{"id":3680215,"web_url":"http://patchwork.ozlabs.org/comment/3680215/","msgid":"<2c6bf45a-cf64-4879-9cec-3dac35a4905c@linaro.org>","list_archive_url":null,"date":"2026-04-22T03:45:55","subject":"Re: [PATCH v2 06/13] target/mips: add Octeon LA* atomic instructions","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/22/26 03:27, James Hilliard wrote:\n> Implement the Octeon LA* read-modify-write atomic instruction family:\n> LAI/LAID, LAD/LADD, LAA/LAAD, LAS/LASD, LAC/LACD, and LAW/LAWD.\n> \n> These operations are architecturally distinct from SAA/SAAD and are used\n> by existing Octeon user-mode code for atomic counters, bit operations,\n> and exchange-style updates.\n> \n> Signed-off-by: James Hilliard \n> ---\n> Changes v1 -> v2:\n> - Keep LA* atomics naturally aligned per Octeon L2 transaction\n> semantics.\n> - Use explicit i64 TCG ops in the LA* translator paths. (suggested by\n> Philippe Mathieu-Daudé)\n> ---\n> target/mips/tcg/octeon.decode | 17 ++++\n> target/mips/tcg/octeon_translate.c | 170 +++++++++++++++++++++++++++++++++++++\n> 2 files changed, 187 insertions(+)\n> \n> diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode\n> index 2eb15aa17f..9dcc5a6ae0 100644\n> --- a/target/mips/tcg/octeon.decode\n> +++ b/target/mips/tcg/octeon.decode\n> @@ -60,6 +60,23 @@ V3MULU 011100 ..... ..... ..... 00000 010001 @r3\n> SAA 011100 ..... ..... 00000 00000 011000 @saa\n> SAAD 011100 ..... ..... 00000 00000 011001 @saa\n> \n> +&la base rd\n> +&laa base add rd\n> +@la ...... base:5 ..... rd:5 ........... &la\n> +@laa ...... base:5 add:5 rd:5 ........... &laa\n> +LAI 011100 ..... 00000 ..... 00010 011111 @la\n> +LAID 011100 ..... 00000 ..... 00011 011111 @la\n> +LAD 011100 ..... 00000 ..... 00110 011111 @la\n> +LADD 011100 ..... 00000 ..... 00111 011111 @la\n> +LAA 011100 ..... ..... ..... 10010 011111 @laa\n> +LAAD 011100 ..... ..... ..... 10011 011111 @laa\n> +LAS 011100 ..... 00000 ..... 01010 011111 @la\n> +LASD 011100 ..... 00000 ..... 01011 011111 @la\n> +LAC 011100 ..... 00000 ..... 01110 011111 @la\n> +LACD 011100 ..... 00000 ..... 01111 011111 @la\n> +LAW 011100 ..... ..... ..... 10110 011111 @laa\n> +LAWD 011100 ..... ..... ..... 10111 011111 @laa\n> +\n> &zcb base\n> ZCB 011100 base:5 00000 00000 11100 011111 &zcb\n> ZCBT 011100 base:5 00000 00000 11101 011111 &zcb\n> diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c\n> index cdb4d36c8e..6309cd5fff 100644\n> --- a/target/mips/tcg/octeon_translate.c\n> +++ b/target/mips/tcg/octeon_translate.c\n> @@ -254,6 +254,164 @@ static bool trans_saa(DisasContext *ctx, arg_saa *a, MemOp mop)\n> return true;\n> }\n> \n> +static bool trans_la_common(DisasContext *ctx, int base, int add_reg, int rd,\n> + int64_t imm, bool dw)\n> +{\n> + if (dw && !octeon_check_64(ctx)) {\n> + return true;\n> + }\n> +\n> + TCGv_i64 addr = tcg_temp_new_i64();\n> +\n> + gen_base_offset_addr(ctx, addr, base, 0);\n> +\n> + if (dw) {\n> +#if TARGET_LONG_BITS == 64\n> + TCGv_i64 value = tcg_temp_new_i64();\n> + TCGv_i64 old = tcg_temp_new_i64();\n> + MemOp amo = mo_endian(ctx) | MO_UQ | MO_ALIGN;\n> +\n> + if (add_reg >= 0) {\n> + gen_load_gpr(value, add_reg);\n> + } else {\n> + tcg_gen_movi_i64(value, imm);\n> + }\n> +\n> + tcg_gen_atomic_fetch_add_i64(old, addr, value, ctx->mem_idx, amo);\n> + gen_store_gpr(old, rd);\n> +#endif\n\n\nSurely patch 2 was all about octeon being only for 64-bit cpus. Why the ifdef?\n\n\nr~","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=nsQhFTFu;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; helo=lists1p.gnu.org;\n envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n receiver=patchwork.ozlabs.org)"],"Received":["from lists1p.gnu.org (lists1p.gnu.org [209.51.188.17])\n\t(using TLSv1.2 with cipher ECDHE-ECDSA-AES256-GCM-SHA384 (256/256 bits))\n\t(No client certificate requested)\n\tby legolas.ozlabs.org (Postfix) with ESMTPS id 4g0lX154ybz1y2d\n\tfor ; Wed, 22 Apr 2026 13:46:41 +1000 (AEST)","from localhost ([::1] helo=lists1p.gnu.org)\n\tby lists1p.gnu.org with esmtp (Exim 4.90_1)\n\t(envelope-from )\n\tid 1wFOXT-0001zd-Kv; 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charset=UTF-8; format=flowed","Content-Transfer-Encoding":"8bit","Received-SPF":"pass client-ip=2607:f8b0:4864:20::52e;\n envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com","X-Spam_score_int":"-20","X-Spam_score":"-2.1","X-Spam_bar":"--","X-Spam_report":"(-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1,\n DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1,\n RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001,\n SPF_PASS=-0.001 autolearn=ham autolearn_force=no","X-Spam_action":"no action","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.29","Precedence":"list","List-Id":"qemu development ","List-Unsubscribe":",\n ","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n ","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org"}},{"id":3680217,"web_url":"http://patchwork.ozlabs.org/comment/3680217/","msgid":"<4b76083f-cbf4-484f-935f-7174a9d4a3c9@linaro.org>","list_archive_url":null,"date":"2026-04-22T03:55:51","subject":"Re: [PATCH v2 06/13] target/mips: add Octeon LA* atomic instructions","submitter":{"id":72104,"url":"http://patchwork.ozlabs.org/api/people/72104/","name":"Richard Henderson","email":"richard.henderson@linaro.org"},"content":"On 4/22/26 03:27, James Hilliard wrote:\n> +static bool trans_lai(DisasContext *ctx, arg_la *a, int unused)\n> +{\n> + return trans_la_common(ctx, a->base, -1, a->rd, 1, false);\n> +}\n> +\n> +static bool trans_laid(DisasContext *ctx, arg_la *a, int unused)\n> +{\n> + return trans_la_common(ctx, a->base, -1, a->rd, 1, true);\n> +}\n> +\n> +static bool trans_lad(DisasContext *ctx, arg_la *a, int unused)\n> +{\n> + return trans_la_common(ctx, a->base, -1, a->rd, -1, false);\n> +}\n> +\n> +static bool trans_ladd(DisasContext *ctx, arg_la *a, int unused)\n> +{\n> + return trans_la_common(ctx, a->base, -1, a->rd, -1, true);\n> +}\n> +\n> +static bool trans_laa(DisasContext *ctx, arg_laa *a, int unused)\n> +{\n> + return trans_la_common(ctx, a->base, a->add, a->rd, 0, false);\n> +}\n> +\n> +static bool trans_laad(DisasContext *ctx, arg_laa *a, int unused)\n> +{\n> + return trans_la_common(ctx, a->base, a->add, a->rd, 0, true);\n> +}\n> +\n> +static bool trans_las(DisasContext *ctx, arg_la *a, int unused)\n> +{\n> + return trans_law_common(ctx, a->base, -1, a->rd, -1, false);\n> +}\n> +\n> +static bool trans_lasd(DisasContext *ctx, arg_la *a, int unused)\n> +{\n> + return trans_law_common(ctx, a->base, -1, a->rd, -1, true);\n> +}\n> +\n> +static bool trans_lac(DisasContext *ctx, arg_la *a, int unused)\n> +{\n> + return trans_law_common(ctx, a->base, -1, a->rd, 0, false);\n> +}\n> +\n> +static bool trans_lacd(DisasContext *ctx, arg_la *a, int unused)\n> +{\n> + return trans_law_common(ctx, a->base, -1, a->rd, 0, true);\n> +}\n> +\n> +static bool trans_law(DisasContext *ctx, arg_laa *a, int unused)\n> +{\n> + return trans_law_common(ctx, a->base, a->add, a->rd, 0, false);\n> +}\n> +\n> +static bool trans_lawd(DisasContext *ctx, arg_laa *a, int unused)\n> +{\n> + return trans_law_common(ctx, a->base, a->add, a->rd, 0, true);\n> +}\n> +\n> static bool trans_ZCB(DisasContext *ctx, arg_zcb *a)\n> {\n> TCGv_i64 addr = tcg_temp_new_i64();\n> @@ -376,6 +534,18 @@ static bool trans_vmul(DisasContext *ctx, arg_decode_ext_octeon1 *a,\n> \n> TRANS(SAA, trans_saa, MO_UL);\n> TRANS(SAAD, trans_saa, MO_UQ);\n> +TRANS(LAI, trans_lai, 0);\n> +TRANS(LAID, trans_laid, 0);\n> +TRANS(LAD, trans_lad, 0);\n> +TRANS(LADD, trans_ladd, 0);\n> +TRANS(LAA, trans_laa, 0);\n> +TRANS(LAAD, trans_laad, 0);\n> +TRANS(LAS, trans_las, 0);\n> +TRANS(LASD, trans_lasd, 0);\n> +TRANS(LAC, trans_lac, 0);\n> +TRANS(LACD, trans_lacd, 0);\n> +TRANS(LAW, trans_law, 0);\n> +TRANS(LAWD, trans_lawd, 0);\n> TRANS(LBX, trans_lx, MO_SB);\n> TRANS(LBUX, trans_lx, MO_UB);\n> TRANS(LHX, trans_lx, MO_SW);\n\nThis is incorrect usage of TRANS(), or a mis-feature of the mips version of TRANS().\n\nIf TRANS() is changed such that 'a' is not implied, then you can expand the macro here:\n\nTRANS(LAI, trans_la_common, a->base, -1, a->rd, 1, false)\n\nOtherwise, isolate common usage within each argument set:\n\nTRANS(LAI, do_lai, 1, false)\nTRANS(LAID, do_lai, 1, true)\nTRANS(LAD, do_lai, -1, false)\nTRANS(LADD, do_lai, -1, true)\n\nTRANS(LAA, do_laa, 1, false)\nTRANS(LAAD, do_laa, 1, true)\n\netc.","headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@legolas.ozlabs.org","Authentication-Results":["legolas.ozlabs.org;\n\tdkim=pass (2048-bit key;\n unprotected) header.d=linaro.org header.i=@linaro.org header.a=rsa-sha256\n header.s=google header.b=zjJe5eC+;\n\tdkim-atps=neutral","legolas.ozlabs.org;\n spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org\n (client-ip=209.51.188.17; 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